Update to Hekate bdk 5.5.0, prelim Mariko support
This commit is contained in:
parent
04378b322d
commit
5d101cad50
89 changed files with 12779 additions and 2210 deletions
|
@ -72,6 +72,7 @@
|
|||
#define EMC_PDEX2MRR 0xb4
|
||||
#define EMC_ODT_WRITE 0xb0
|
||||
#define EMC_WEXT 0xb8
|
||||
#define EMC_CTT 0xBC
|
||||
#define EMC_RFC_SLR 0xc0
|
||||
#define EMC_MRS_WAIT_CNT2 0xc4
|
||||
#define EMC_MRS_WAIT_CNT 0xc8
|
||||
|
@ -86,8 +87,13 @@
|
|||
#define EMC_MRR 0xec
|
||||
#define EMC_CMDQ 0xf0
|
||||
#define EMC_MC2EMCQ 0xf4
|
||||
#define EMC_FBIO_TWTM 0xF8
|
||||
#define EMC_FBIO_TRATM 0xFC
|
||||
#define EMC_FBIO_TWATM 0x108
|
||||
#define EMC_FBIO_TR2REF 0x10C
|
||||
#define EMC_FBIO_SPARE 0x100
|
||||
#define EMC_FBIO_CFG5 0x104
|
||||
#define EMC_FBIO_CFG6 0x114
|
||||
#define EMC_CFG_RSV 0x120
|
||||
#define EMC_ACPD_CONTROL 0x124
|
||||
#define EMC_MPC 0x128
|
||||
|
@ -211,6 +217,7 @@
|
|||
#define EMC_AUTO_CAL_CONFIG6 0x5cc
|
||||
#define EMC_AUTO_CAL_CONFIG7 0x574
|
||||
#define EMC_AUTO_CAL_CONFIG8 0x2dc
|
||||
#define EMC_AUTO_CAL_CONFIG9 0x42C
|
||||
#define EMC_AUTO_CAL_VREF_SEL_0 0x2f8
|
||||
#define EMC_AUTO_CAL_VREF_SEL_1 0x300
|
||||
#define EMC_AUTO_CAL_INTERVAL 0x2a8
|
||||
|
@ -232,7 +239,7 @@
|
|||
#define EMC_COMP_PAD_SW_CTRL 0x57c
|
||||
#define EMC_REQ_CTRL 0x2b0
|
||||
#define EMC_EMC_STATUS 0x2b4
|
||||
#define EMC_STATUS_MRR_DIVLD (1 << 20)
|
||||
#define EMC_STATUS_MRR_DIVLD BIT(20)
|
||||
#define EMC_CFG_2 0x2b8
|
||||
#define EMC_CFG_DIG_DLL 0x2bc
|
||||
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
|
||||
|
@ -386,6 +393,8 @@
|
|||
#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4
|
||||
#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8
|
||||
#define EMC_TRAINING_DRAMC_TIMING 0xedc
|
||||
#define EMC_PMACRO_DATA_PI_CTRL 0x110
|
||||
#define EMC_PMACRO_CMD_PI_CTRL 0x114
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
|
||||
|
@ -650,6 +659,7 @@
|
|||
#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60
|
||||
#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64
|
||||
#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
|
||||
#define EMC_PMACRO_DSR_VTTGEN_CTRL0 0xC6C
|
||||
#define EMC_PMACRO_BRICK_MAPPING_0 0xc80
|
||||
#define EMC_PMACRO_BRICK_MAPPING_1 0xc84
|
||||
#define EMC_PMACRO_BRICK_MAPPING_2 0xc88
|
||||
|
@ -662,6 +672,24 @@
|
|||
#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c
|
||||
#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8
|
||||
#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xD40
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xD44
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xD48
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xD4C
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xD50
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xD54
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xD60
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xD64
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xD68
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xD6C
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xD70
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xD74
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xD80
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xD84
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xD88
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xD8C
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xD90
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xD94
|
||||
#define EMC_PMC_SCRATCH1 0x440
|
||||
#define EMC_PMC_SCRATCH2 0x444
|
||||
#define EMC_PMC_SCRATCH3 0x448
|
||||
|
@ -684,10 +712,13 @@ enum
|
|||
|
||||
typedef struct _emc_mr_data_t
|
||||
{
|
||||
u8 dev0_ch0;
|
||||
u8 dev0_ch1;
|
||||
u8 dev1_ch0;
|
||||
u8 dev1_ch1;
|
||||
// Device 0.
|
||||
u8 rank0_ch0;
|
||||
u8 rank0_ch1;
|
||||
|
||||
// Device 1.
|
||||
u8 rank1_ch0;
|
||||
u8 rank1_ch1;
|
||||
} emc_mr_data_t;
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue