Update to Hekate bdk 5.5.0, prelim Mariko support
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shchmue
parent
04378b322d
commit
5d101cad50
89 changed files with 12779 additions and 2210 deletions
100
bdk/soc/t210.h
100
bdk/soc/t210.h
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@ -61,6 +61,9 @@
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#define EMC_BASE 0x7001B000
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#define EMC0_BASE 0x7001E000
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#define EMC1_BASE 0x7001F000
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#define XUSB_HOST_BASE 0x70090000
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#define XUSB_PADCTL_BASE 0x7009F000
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#define XUSB_DEV_BASE 0x700D0000
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#define MIPI_CAL_BASE 0x700E3000
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#define CL_DVFS_BASE 0x70110000
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#define I2S_BASE 0x702D1000
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@ -79,7 +82,7 @@
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#define VIC(off) _REG(VIC_BASE, off)
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * cidx), off)
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#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * (cidx)), off)
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
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@ -109,6 +112,12 @@
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#define EMC(off) _REG(EMC_BASE, off)
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#define EMC_CH0(off) _REG(EMC0_BASE, off)
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#define EMC_CH1(off) _REG(EMC1_BASE, off)
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#define XUSB_HOST(off) _REG(XUSB_HOST_BASE, off)
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#define XUSB_PADCTL(off) _REG(XUSB_PADCTL_BASE, off)
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#define XUSB_DEV(off) _REG(XUSB_DEV_BASE, off)
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#define XUSB_DEV_XHCI(off) _REG(XUSB_DEV_BASE, off)
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#define XUSB_DEV_PCI(off) _REG(XUSB_DEV_BASE + 0x8000, off)
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#define XUSB_DEV_DEV(off) _REG(XUSB_DEV_BASE + 0x9000, off)
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#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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@ -149,14 +158,33 @@
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/*! AHB Gizmo registers. */
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
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#define ARBITRATION_PRIORITY_CTRL_ENB_FAST_REARBITRATE (1 << 6)
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#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29)
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#define PRIORITY_SELECT_USB BIT(6) // USB-OTG.
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#define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC.
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#define PRIORITY_SELECT_USB3 BIT(17) // XUSB.
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#define AHB_GIZMO_AHB_MEM 0x10
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#define AHB_MEM_ENB_FAST_REARBITRATE (1 << 2)
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#define AHB_MEM_ENB_FAST_REARBITRATE BIT(2)
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#define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7)
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#define AHB_MEM_IMMEDIATE BIT(18)
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#define AHB_GIZMO_APB_DMA 0x14
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#define AHB_GIZMO_USB 0x20
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#define AHB_GIZMO_USB_IMMEDIATE (1 << 18)
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#define AHB_GIZMO_SDMMC4 0x48
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#define AHB_GIZMO_USB2 0x7C
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#define AHB_GIZMO_USB3 0x80
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#define AHB_GIZMO_IMMEDIATE BIT(18)
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#define AHB_ARBITRATION_XBAR_CTRL 0xE0
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#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4
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#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8
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#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
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#define MEM_PREFETCH_ENABLE (1 << 31)
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#define MEM_PREFETCH_AHB_MST_USB 6
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#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4
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#define MST_ID(x) (((x) & 0x1F) << 26)
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#define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5)
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#define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG.
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#define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC.
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#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
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#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
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#define MEM_PREFETCH_ENABLE BIT(31)
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#define AHB_AHB_SPARE_REG 0x110
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/*! Misc registers. */
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#define APB_MISC_PP_STRAPPING_OPT_A 0x08
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@ -170,19 +198,16 @@
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
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#define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
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#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
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/*! System registers. */
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#define AHB_ARBITRATION_XBAR_CTRL 0xE0
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#define AHB_AHB_SPARE_REG 0x110
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/*! Secure boot registers. */
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#define SB_CSR 0x0
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#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
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#define SB_CSR_PIROM_DISABLE (1 << 4)
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#define SB_CSR_NS_RST_VEC_WR_DIS BIT(1)
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#define SB_CSR_PIROM_DISABLE BIT(4)
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#define SB_AA64_RESET_LOW 0x30
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#define SB_AA64_RST_AARCH64_MODE_EN (1 << 0)
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#define SB_AA64_RST_AARCH64_MODE_EN BIT(0)
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#define SB_AA64_RESET_HIGH 0x34
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/*! SOR registers. */
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@ -217,20 +242,20 @@
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#define TIMERUS_USEC_CFG (0x10 + 0x4)
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#define TIMER_TMR8_TMR_PTV 0x78
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#define TIMER_TMR9_TMR_PTV 0x80
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#define TIMER_EN (1 << 31)
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#define TIMER_PER_EN (1 << 30)
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#define TIMER_PER_EN BIT(30)
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#define TIMER_EN BIT(31)
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#define TIMER_TMR8_TMR_PCR 0x7C
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#define TIMER_TMR9_TMR_PCR 0x8C
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#define TIMER_INTR_CLR (1 << 30)
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#define TIMER_INTR_CLR BIT(30)
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#define TIMER_WDT4_CONFIG (0x100 + 0x80)
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#define TIMER_SRC(TMR) (TMR & 0xF)
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#define TIMER_PER(PER) ((PER & 0xFF) << 4)
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#define TIMER_SYSRESET_EN (1 << 14)
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#define TIMER_PMCRESET_EN (1 << 15)
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#define TIMER_SRC(TMR) ((TMR) & 0xF)
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#define TIMER_PER(PER) (((PER) & 0xFF) << 4)
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#define TIMER_SYSRESET_EN BIT(14)
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#define TIMER_PMCRESET_EN BIT(15)
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#define TIMER_WDT4_COMMAND (0x108 + 0x80)
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#define TIMER_START_CNT (1 << 0)
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#define TIMER_CNT_DISABLE (1 << 1)
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#define TIMER_START_CNT BIT(0)
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#define TIMER_CNT_DISABLE BIT(1)
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#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
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#define TIMER_MAGIC_PTRN 0xC45A
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@ -245,29 +270,29 @@
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#define I2S4_CTRL 0x3A0
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#define I2S5_CG 0x488
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#define I2S5_CTRL 0x4A0
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#define I2S_CG_SLCG_ENABLE (1 << 0)
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#define I2S_CTRL_MASTER_EN (1 << 10)
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#define I2S_CG_SLCG_ENABLE BIT(0)
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#define I2S_CTRL_MASTER_EN BIT(10)
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/*! PWM registers. */
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#define PWM_CONTROLLER_PWM_CSR_0 0x00
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#define PWM_CONTROLLER_PWM_CSR_1 0x10
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#define PWM_CSR_EN (1 << 31)
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#define PWM_CSR_EN BIT(31)
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/*! Special registers. */
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#define EMC_SCRATCH0 0x324
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#define EMC_HEKA_UPD (1 << 30)
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#define EMC_SEPT_RUN (1 << 31)
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#define EMC_HEKA_UPD BIT(30)
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#define EMC_SEPT_RUN BIT(31)
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/*! Flow controller registers. */
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#define FLOW_CTLR_HALT_COP_EVENTS 0x4
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#define HALT_COP_GIC_IRQ (1 << 9)
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#define HALT_COP_LIC_IRQ (1 << 11)
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#define HALT_COP_SEC (1 << 23)
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#define HALT_COP_MSEC (1 << 24)
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#define HALT_COP_USEC (1 << 25)
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#define HALT_COP_JTAG (1 << 28)
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#define HALT_COP_WAIT_EVENT (1 << 30)
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#define HALT_COP_STOP_UNTIL_IRQ (1 << 31)
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#define HALT_COP_GIC_IRQ BIT(9)
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#define HALT_COP_LIC_IRQ BIT(11)
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#define HALT_COP_SEC BIT(23)
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#define HALT_COP_MSEC BIT(24)
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#define HALT_COP_USEC BIT(25)
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#define HALT_COP_JTAG BIT(28)
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#define HALT_COP_WAIT_EVENT BIT(30)
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#define HALT_COP_STOP_UNTIL_IRQ BIT(31)
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#define HALT_COP_MAX_CNT 0xFF
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#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
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#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
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@ -280,9 +305,4 @@
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#define FLOW_CTLR_RAM_REPAIR 0x40
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
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/*! USB controller registers. */
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#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
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#define BAT_CHRG_CFG0_OP_SRC_EN (1 << 3)
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#define BAT_CHRG_CFG0_PWRDOWN_CHRG (1 << 0)
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#endif
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