Update to hekate bdk 5.6.0
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shchmue
parent
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commit
f2f3c5daf0
43 changed files with 1530 additions and 1533 deletions
142
bdk/mem/sdram.c
142
bdk/mem/sdram.c
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@ -1,7 +1,7 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 balika011
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* Copyright (c) 2019-2020 CTCaer
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* Copyright (c) 2019-2021 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -36,22 +36,46 @@
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#define CONFIG_SDRAM_KEEP_ALIVE
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//#define CONFIG_SDRAM_COMPRESS_CFG
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typedef struct _sdram_vendor_patch_t
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{
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u32 val;
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u32 addr:10;
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u32 dramid:22;
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u32 offset:16;
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u32 dramcf:16;
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} sdram_vendor_patch_t;
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#ifdef CONFIG_SDRAM_COMPRESS_CFG
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#include <libs/compr/lz.h>
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#include "sdram_config_lz.inl"
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#else
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#include "sdram_config.inl"
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#endif
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static const u8 dram_encoding_t210b01[] = {
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LPDDR4X_UNUSED,
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LPDDR4X_UNUSED,
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LPDDR4X_UNUSED,
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LPDDR4X_4GB_HYNIX_1Y_A,
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LPDDR4X_UNUSED,
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LPDDR4X_4GB_HYNIX_1Y_A,
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LPDDR4X_4GB_HYNIX_1Y_A,
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LPDDR4X_4GB_SAMSUNG_X1X2,
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LPDDR4X_NO_PATCH,
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LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ,
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LPDDR4X_NO_PATCH,
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LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046,
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LPDDR4X_NO_PATCH,
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LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ,
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LPDDR4X_NO_PATCH,
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LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046,
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LPDDR4X_4GB_SAMSUNG_Y,
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LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
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LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
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LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
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LPDDR4X_4GB_SAMSUNG_1Y_Y,
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LPDDR4X_8GB_SAMSUNG_1Y_Y,
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LPDDR4X_UNUSED, // Removed.
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LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
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LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
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LPDDR4X_4GB_MICRON_1Y_A,
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LPDDR4X_4GB_MICRON_1Y_A,
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LPDDR4X_4GB_MICRON_1Y_A,
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LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
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};
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#include "sdram_config.inl"
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#include "sdram_config_t210b01.inl"
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static bool _sdram_wait_emc_status(u32 reg_offset, u32 bit_mask, bool updated_state, s32 emc_channel)
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@ -1350,57 +1374,21 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
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SYSREG(AHB_ARBITRATION_XBAR_CTRL) = (SYSREG(AHB_ARBITRATION_XBAR_CTRL) & 0xFFFEFFFF) | (params->ahb_arbitration_xbar_ctrl_meminit_done << 16);
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}
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#ifndef CONFIG_SDRAM_COMPRESS_CFG
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static void _sdram_patch_model_params_t210(u32 dramid, u32 *params)
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{
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for (u32 i = 0; i < ARRAY_SIZE(sdram_cfg_vendor_patches_t210); i++)
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if (sdram_cfg_vendor_patches_t210[i].dramid & DRAM_ID(dramid))
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params[sdram_cfg_vendor_patches_t210[i].addr] = sdram_cfg_vendor_patches_t210[i].val;
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}
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#endif
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static void _sdram_patch_model_params_t210b01(u32 dramid, u32 *params)
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{
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for (u32 i = 0; i < ARRAY_SIZE(sdram_cfg_vendor_patches_t210b01); i++)
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if (sdram_cfg_vendor_patches_t210b01[i].dramid & DRAM_ID2(dramid))
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params[sdram_cfg_vendor_patches_t210b01[i].addr] = sdram_cfg_vendor_patches_t210b01[i].val;
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}
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static void *_sdram_get_params_t210()
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{
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// Check if id is proper.
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u32 dramid = fuse_read_dramid(false);
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#ifdef CONFIG_SDRAM_COMPRESS_CFG
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// Copy base parameters.
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u32 *params = (u32 *)SDRAM_PARAMS_ADDR;
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memcpy(params, &_dram_cfg_0_samsung_4gb, sizeof(sdram_params_t210_t));
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u8 *buf = (u8 *)SDRAM_PARAMS_ADDR;
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LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz));
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return (void *)&buf[sizeof(sdram_params_t210_t) * dramid];
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// Patch parameters if needed.
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for (u32 i = 0; i < ARRAY_SIZE(sdram_cfg_vendor_patches_t210); i++)
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if (sdram_cfg_vendor_patches_t210[i].dramcf & DRAM_ID(dramid))
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params[sdram_cfg_vendor_patches_t210[i].offset] = sdram_cfg_vendor_patches_t210[i].val;
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#else
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u32 *buf = (u32 *)SDRAM_PARAMS_ADDR;
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memcpy(buf, &_dram_cfg_0_samsung_4gb, sizeof(sdram_params_t210_t));
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switch (dramid)
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{
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case LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH:
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case LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT:
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break;
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case LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE:
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case LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH:
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#ifdef CONFIG_SDRAM_COPPER_SUPPORT
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case LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH:
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case LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE:
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case LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT:
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#endif
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_sdram_patch_model_params_t210(dramid, (u32 *)buf);
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break;
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}
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return (void *)buf;
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#endif
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return (void *)params;
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}
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void *sdram_get_params_t210b01()
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@ -1408,38 +1396,20 @@ void *sdram_get_params_t210b01()
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// Check if id is proper.
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u32 dramid = fuse_read_dramid(false);
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u32 *buf = (u32 *)SDRAM_PARAMS_ADDR;
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memcpy(buf, &_dram_cfg_08_10_12_14_samsung_hynix_4gb, sizeof(sdram_params_t210b01_t));
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// Copy base parameters.
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u32 *params = (u32 *)SDRAM_PARAMS_ADDR;
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memcpy(params, &_dram_cfg_08_10_12_14_samsung_hynix_4gb, sizeof(sdram_params_t210b01_t));
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switch (dramid)
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{
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case LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ:
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case LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME:
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case LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ:
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case LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME:
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break;
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// Patch parameters if needed.
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u8 dram_code = dram_encoding_t210b01[dramid];
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if (!dram_code)
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return (void *)params;
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case LPDDR4X_IOWA_4GB_SAMSUNG_X1X2:
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case LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ:
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case LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WT:
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case LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ:
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case LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WT:
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case LPDDR4X_IOWA_4GB_SAMSUNG_Y:
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case LPDDR4X_IOWA_4GB_SAMSUNG_1Y_X:
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case LPDDR4X_IOWA_8GB_SAMSUNG_1Y_X:
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case LPDDR4X_HOAG_4GB_SAMSUNG_1Y_X:
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case LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y:
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case LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y:
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case LPDDR4X_AULA_4GB_SAMSUNG_1Y_A:
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case LPDDR4X_AULA_8GB_SAMSUNG_1Y_X:
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case LPDDR4X_AULA_4GB_SAMSUNG_1Y_X:
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case LPDDR4X_IOWA_4GB_MICRON_1Y_A:
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case LPDDR4X_HOAG_4GB_MICRON_1Y_A:
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case LPDDR4X_AULA_4GB_MICRON_1Y_A:
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_sdram_patch_model_params_t210b01(dramid, (u32 *)buf);
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break;
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}
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return (void *)buf;
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for (u32 i = 0; i < ARRAY_SIZE(sdram_cfg_vendor_patches_t210b01); i++)
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if (sdram_cfg_vendor_patches_t210b01[i].dramcf == dram_code)
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params[sdram_cfg_vendor_patches_t210b01[i].offset] = sdram_cfg_vendor_patches_t210b01[i].val;
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return (void *)params;
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}
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/*
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@ -1485,7 +1455,7 @@ static void _sdram_init_t210()
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const sdram_params_t210_t *params = (const sdram_params_t210_t *)_sdram_get_params_t210();
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// Set DRAM voltage.
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max7762x_regulator_set_voltage(REGULATOR_SD1, 1100000);
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max7762x_regulator_set_voltage(REGULATOR_SD1, 1100000); // HOS uses 1.125V
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// VDDP Select.
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PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
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