Bump version to v1.9.10

Support 16.0.0 keys

.gitignore

@@ -1,4 +1,10 @@
+.vs
 .vscode
-build
+build/*
-output
+output/*
-research
+research/*
+loader/payload_00.h
+loader/payload_01.h
+tools/bin2c/bin2c
+keygen/tsec_keygen.h
+tools/lz/lz77

Makefile

@@ -8,19 +8,21 @@ include $(DEVKITARM)/base_rules
 
 ################################################################################
 
-IPL_LOAD_ADDR := 0x40003000
+IPL_LOAD_ADDR := 0x40008000
-LPVERSION_MAJOR := 1
+MAGIC = 0x4B434F4C #"LOCK"
-LPVERSION_MINOR := 8
+include ./Versions.inc
-LPVERSION_BUGFX := 5
 
 ################################################################################
 
 TARGET := Lockpick_RCM
 BUILDDIR := build
 OUTPUTDIR := output
-SOURCEDIR = source
+SOURCEDIR := source
 BDKDIR := bdk
 BDKINC := -I./$(BDKDIR)
+KEYGENDIR := keygen
+KEYGEN := tsec_keygen
+KEYGENH := tsec_keygen.h
 VPATH = $(dir ./$(SOURCEDIR)/) $(dir $(wildcard ./$(SOURCEDIR)/*/)) $(dir $(wildcard ./$(SOURCEDIR)/*/*/))
 VPATH += $(dir $(wildcard ./$(BDKDIR)/)) $(dir $(wildcard ./$(BDKDIR)/*/)) $(dir $(wildcard ./$(BDKDIR)/*/*/))
 
@@ -36,48 +38,93 @@ FFCFG_INC := '"../$(SOURCEDIR)/libs/fatfs/ffconf.h"'
 
 ################################################################################
 
-CUSTOMDEFINES := -DIPL_LOAD_ADDR=$(IPL_LOAD_ADDR)
+CUSTOMDEFINES := -DIPL_LOAD_ADDR=$(IPL_LOAD_ADDR) -DLP_MAGIC=$(MAGIC)
-CUSTOMDEFINES += -DLP_VER_MJ=$(LPVERSION_MAJOR) -DLP_VER_MN=$(LPVERSION_MINOR) -DLP_VER_BF=$(LPVERSION_BUGFX)
+CUSTOMDEFINES += -DLP_VER_MJ=$(LPVERSION_MAJOR) -DLP_VER_MN=$(LPVERSION_MINOR) -DLP_VER_BF=$(LPVERSION_BUGFX) -DLP_RESERVED=$(LPVERSION_RSVD)
 CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC)
 
+#CUSTOMDEFINES += -DDEBUG
+
+# UART Logging: Max baudrate 12.5M.
+# DEBUG_UART_PORT - 0: UART_A, 1: UART_B, 2: UART_C.
+#CUSTOMDEFINES += -DDEBUG_UART_BAUDRATE=115200 -DDEBUG_UART_INVERT=0 -DDEBUG_UART_PORT=0
+
+#TODO: Considering reinstating some of these when pointer warnings have been fixed.
+WARNINGS := -Wall -Wno-array-bounds -Wno-stringop-overread -Wno-stringop-overflow
+
 ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-CFLAGS = $(ARCH) -O2 -nostdlib -ffunction-sections -fno-inline -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall $(CUSTOMDEFINES)
+CFLAGS = $(ARCH) -O2 -g -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 $(WARNINGS) $(CUSTOMDEFINES)
 LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections -Xlinker --defsym=IPL_LOAD_ADDR=$(IPL_LOAD_ADDR)
 
+LDRDIR := $(wildcard loader)
+TOOLSLZ := $(wildcard tools/lz)
+TOOLSB2C := $(wildcard tools/bin2c)
+TOOLS := $(TOOLSLZ) $(TOOLSB2C)
+
 ################################################################################
 
-.PHONY: all clean
+.PHONY: all clean $(LDRDIR) $(TOOLS)
 
-all: $(OUTPUTDIR)/$(TARGET).bin
+all: $(OUTPUTDIR)/$(TARGET).bin $(LDRDIR)
-	@echo -n "Payload size is "
+	@echo "--------------------------------------"
+	@echo -n "Uncompr size: "
+	$(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET)_unc.bin))
+	@echo $(BIN_SIZE)" Bytes"
+	@echo "Uncompr Max:  140288 Bytes + 3 KiB BSS"
+	@if [ ${BIN_SIZE} -gt 140288 ]; then echo "\e[1;33mUncompr size exceeds limit!\e[0m"; fi
+	@echo -n "Payload size: "
 	$(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET).bin))
-	@echo $(BIN_SIZE)
+	@echo $(BIN_SIZE)" Bytes"
-	@echo "Max size is 126296 Bytes."
+	@echo "Payload Max:  126296 Bytes"
 	@if [ ${BIN_SIZE} -gt 126296 ]; then echo "\e[1;33mPayload size exceeds limit!\e[0m"; fi
+	@echo "--------------------------------------"
 
-clean:
+clean: $(TOOLS)
 	@rm -rf $(BUILDDIR)
 	@rm -rf $(OUTPUTDIR)
 
-$(OUTPUTDIR)/$(TARGET).bin: $(BUILDDIR)/$(TARGET)/$(TARGET).elf
+$(LDRDIR): $(OUTPUTDIR)/$(TARGET).bin
+	@$(TOOLSLZ)/lz77 $(OUTPUTDIR)/$(TARGET).bin
+	mv $(OUTPUTDIR)/$(TARGET).bin $(OUTPUTDIR)/$(TARGET)_unc.bin
+	@mv $(OUTPUTDIR)/$(TARGET).bin.00.lz payload_00
+	@mv $(OUTPUTDIR)/$(TARGET).bin.01.lz payload_01
+	@$(TOOLSB2C)/bin2c payload_00 > $(LDRDIR)/payload_00.h
+	@$(TOOLSB2C)/bin2c payload_01 > $(LDRDIR)/payload_01.h
+	@rm payload_00
+	@rm payload_01
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS) PAYLOAD_NAME=$(TARGET)
+
+$(TOOLS):
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)
+
+$(OUTPUTDIR)/$(TARGET).bin: $(BUILDDIR)/$(TARGET)/$(TARGET).elf $(TOOLS)
 	@mkdir -p "$(@D)"
 	$(OBJCOPY) -S -O binary $< $@
 
 $(BUILDDIR)/$(TARGET)/$(TARGET).elf: $(OBJS)
-	$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@
+	@$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@
+	@echo "Lockpick_RCM was built with the following flags:\nCFLAGS:  "$(CFLAGS)"\nLDFLAGS: "$(LDFLAGS)
+
+$(OBJS): | $(KEYGENDIR)
+
+$(KEYGENDIR): $(TOOLS)
+	@cd $(KEYGENDIR) && ../$(TOOLSB2C)/bin2c $(KEYGEN) > $(KEYGENH)
 
 $(BUILDDIR)/$(TARGET)/%.o: $(SOURCEDIR)/%.c
 	@mkdir -p "$(@D)"
-	$(CC) $(CFLAGS) $(BDKINC) -c $< -o $@
+	@echo Building $@
+	@$(CC) $(CFLAGS) $(BDKINC) -c $< -o $@
 
 $(BUILDDIR)/$(TARGET)/%.o: $(SOURCEDIR)/%.S
 	@mkdir -p "$(@D)"
-	$(CC) $(CFLAGS) -c $< -o $@
+	@echo Building $@
+	@$(CC) $(CFLAGS) -c $< -o $@
 
 $(BUILDDIR)/$(TARGET)/%.o: $(BDKDIR)/%.c
 	@mkdir -p "$(@D)"
-	$(CC) $(CFLAGS) $(BDKINC) -c $< -o $@
+	@echo Building $@
+	@$(CC) $(CFLAGS) $(BDKINC) -c $< -o $@
 
 $(BUILDDIR)/$(TARGET)/%.o: $(BDKDIR)/%.S
 	@mkdir -p "$(@D)"
-	$(CC) $(CFLAGS) -c $< -o $@
+	@echo Building $@
+	@$(CC) $(CFLAGS) -c $< -o $@

README.md

@@ -9,7 +9,30 @@ Usage
 * It is highly recommended, but not required, to place Minerva on SD from the latest [Hekate](https://github.com/CTCaer/hekate/releases) for best performance, especially while dumping titlekeys - the file and path is `/bootloader/sys/libsys_minerva.bso`
 * Launch Lockpick_RCM.bin using your favorite payload injector or chainloader
 * Upon completion, keys will be saved to `/switch/prod.keys` and titlekeys to `/switch/title.keys` on SD
-* If the console has Firmware 7.x or higher, the `/sept/` folder from [Atmosphère](https://github.com/Atmosphere-NX/Atmosphere/releases) or [Kosmos](https://github.com/AtlasNX/Kosmos/releases) release zip must be present on SD or else only keyblob master key derivation is possible (ie. up to `master_key_05` only)
+* This release bundles the Falcon keygen from [Atmosphère-NX](https://github.com/Atmosphere-NX/Atmosphere)
+
+Mariko-Specific Keys
+=
+Mariko consoles have several unique keys and protected keyslots. To get your SBK or the Mariko specific keys, you will need to use the `/switch/partialaes.keys` file along with a brute forcing tool such as <https://files.sshnuke.net/PartialAesKeyCrack.zip>. The contents of this file are the keyslot number followed by the result of that keyslot encrypting 16 null bytes. With the tool linked above, enter them in sequence for a given keyslot you want the contents of, for example: `PartialAesKeyCrack.exe <num1> <num2> <num3> <num4>` with the `--numthreads=N` where N is the number of threads you can dedicate to the brute force.
+
+The keyslots are as follows, with names recognized by `hactool`:
+* 0-11 - `mariko_aes_class_key_xx` (this is not used by the Switch but is set by the bootrom; hactoolnet recognizes it but it serves no purpose)
+* 12 - `mariko_kek` (not unique - this is used for master key derivation)
+* 13 - `mariko_bek` (not unique - this is used for BCT and package1 decryption)
+* 14 - `secure_boot_key` (console unique - this isn't needed for further key derivation than what Lockpick_RCM does but might be nice to have for your records)
+* 15 - Secure storage key (console unique - this is not used on retail or dev consoles and not recognized by any tools)
+
+So if you want to brute force the `mariko_kek`, open your `partialaes.keys` and observe the numbers beneath keyslot 12. Here's an example with fake numbers:
+```
+12
+11111111111111111111111111111111 22222222222222222222222222222222 33333333333333333333333333333333 44444444444444444444444444444444
+```
+Then take those numbers and open a command prompt window at the location of the exe linked above and type:
+`PartialAesKeyCrack.exe 11111111111111111111111111111111 22222222222222222222222222222222 33333333333333333333333333333333 44444444444444444444444444444444` and if you're on a powerful enough multicore system, add ` --numthreads=[whatever number of threads]`, ideally not your system's maximum if it's, for example, an older laptop with a low-end dual core CPU. On a Ryzen 3900x with 24 threads this generates a lot of heat but finishes in about 45 seconds.
+
+These keys never change so a brute force need only be conducted once.
+
+This works due to the security engine immediately flushing writes to keyslots which can be written one 32-bit chunk at a time. See: <https://switchbrew.org/wiki/Switch_System_Flaws#Hardware>
 
 Building
 =

Versions.inc

@@ -0,0 +1,5 @@
+# LP Version.
+LPVERSION_MAJOR := 1
+LPVERSION_MINOR := 9
+LPVERSION_BUGFX := 10
+LPVERSION_RSVD := 0

bdk/display/di.c

@@ -0,0 +1,867 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2021 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "di.h"
+#include <power/max77620.h>
+#include <power/max7762x.h>
+#include <mem/heap.h>
+#include <soc/clock.h>
+#include <soc/fuse.h>
+#include <soc/gpio.h>
+#include <soc/hw_init.h>
+#include <soc/i2c.h>
+#include <soc/pinmux.h>
+#include <soc/pmc.h>
+#include <soc/t210.h>
+#include <utils/util.h>
+
+#include "di.inl"
+
+extern volatile nyx_storage_t *nyx_str;
+
+static u32 _display_id = 0;
+static bool nx_aula = false;
+
+static void _display_panel_and_hw_end(bool no_panel_deinit);
+
+static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
+{
+	u32 end = get_tmr_us() + timeout;
+	while (get_tmr_us() < end && DSI(off) & mask)
+		;
+	usleep(5);
+}
+
+static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
+{
+	DSI(_DSIREG(DSI_WR_DATA)) = (param << 8) | cmd;
+	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+
+	if (wait)
+		usleep(wait);
+}
+
+static void _display_dsi_read_rx_fifo(u32 *data)
+{
+	u32 fifo_count = DSI(_DSIREG(DSI_STATUS)) & DSI_STATUS_RX_FIFO_SIZE;
+	for (u32 i = 0; i < fifo_count; i++)
+	{
+		// Read or Drain RX FIFO.
+		if (data)
+			data[i] = DSI(_DSIREG(DSI_RD_DATA));
+		else
+			(void)DSI(_DSIREG(DSI_RD_DATA));
+	}
+}
+
+int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled)
+{
+	int res = 0;
+	u32 host_control = 0;
+	u32 cmd_timeout = video_enabled ? 0 : 250000;
+	u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0};
+
+	// Drain RX FIFO.
+	_display_dsi_read_rx_fifo(NULL);
+
+	// Save host control and enable host cmd packets during video.
+	if (video_enabled)
+	{
+		host_control = DSI(_DSIREG(DSI_HOST_CONTROL));
+
+		// Enable vblank interrupt.
+		DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT;
+
+		// Use the 4th line to transmit the host cmd packet.
+		DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4);
+
+		// Wait for vblank before starting the transfer.
+		DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
+		while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
+			;
+	}
+
+	// Set reply size.
+	_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
+	_display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
+
+	// Request register read.
+	_display_dsi_send_cmd(MIPI_DSI_DCS_READ, cmd, 0);
+	_display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
+
+	// Transfer bus control to device for transmitting the reply.
+	u32 high_speed = video_enabled ? DSI_HOST_CONTROL_HS : 0;
+	DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC | high_speed;
+	_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
+
+	// Wait a bit for the reply.
+	usleep(5000);
+
+	// Read RX FIFO.
+	_display_dsi_read_rx_fifo(fifo);
+
+	// Parse packet and copy over the data.
+	if ((fifo[0] & 0xFF) == DSI_ESCAPE_CMD)
+	{
+		// Act based on reply type.
+		switch (fifo[1] & 0xFF)
+		{
+		case GEN_LONG_RD_RES:
+		case DCS_LONG_RD_RES:
+			memcpy(data, &fifo[2], MIN((fifo[1] >> 8) & 0xFFFF, len));
+			break;
+
+		case GEN_1_BYTE_SHORT_RD_RES:
+		case DCS_1_BYTE_SHORT_RD_RES:
+			memcpy(data, &fifo[2], 1);
+			break;
+
+		case GEN_2_BYTE_SHORT_RD_RES:
+		case DCS_2_BYTE_SHORT_RD_RES:
+			memcpy(data, &fifo[2], 2);
+			break;
+
+		case ACK_ERROR_RES:
+		default:
+			res = 1;
+			break;
+		}
+	}
+	else
+		res = 1;
+
+	// Disable host cmd packets during video and restore host control.
+	if (video_enabled)
+	{
+		// Wait for vblank before reseting sync points.
+		DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
+		while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
+			;
+
+		// Reset all states of syncpt block.
+		DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET;
+		usleep(300); // Stabilization delay.
+
+		// Clear syncpt block reset.
+		DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0;
+		usleep(300); // Stabilization delay.
+
+		// Restore video mode and host control.
+		DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
+		DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control;
+
+		// Disable and clear vblank interrupt.
+		DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0;
+		DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT;
+	}
+
+	return res;
+}
+
+void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled)
+{
+	u8  *fifo8;
+	u32 *fifo32;
+	u32 host_control;
+
+	// Enable host cmd packets during video and save host control.
+	if (video_enabled)
+		DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
+	host_control = DSI(_DSIREG(DSI_HOST_CONTROL));
+
+	// Enable host transfer trigger.
+	DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control | DSI_HOST_CONTROL_TX_TRIG_HOST;
+
+	switch (len)
+	{
+	case 0:
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
+		break;
+
+	case 1:
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd | (*(u8 *)data << 8), 0);
+		break;
+
+	default:
+		fifo32 = calloc(DSI_STATUS_RX_FIFO_SIZE * 8, 4);
+		fifo8 = (u8 *)fifo32;
+		fifo32[0] = (len << 8) | MIPI_DSI_DCS_LONG_WRITE;
+		fifo8[4] = cmd;
+		memcpy(&fifo8[5], data, len);
+		len += 4 + 1; // Increase length by CMD/length word and DCS CMD.
+		for (u32 i = 0; i < (ALIGN(len, 4) / 4); i++)
+			DSI(_DSIREG(DSI_WR_DATA)) = fifo32[i];
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		free(fifo32);
+		break;
+	}
+
+	// Wait for the write to happen.
+	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST);
+
+	// Disable host cmd packets during video and restore host control.
+	if (video_enabled)
+		DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
+	DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control;
+}
+
+void display_dsi_vblank_write(u8 cmd, u32 len, void *data)
+{
+	u8  *fifo8;
+	u32 *fifo32;
+
+	// Enable vblank interrupt.
+	DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT;
+
+	// Use the 4th line to transmit the host cmd packet.
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4);
+
+	// Wait for vblank before starting the transfer.
+	DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
+	while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
+		;
+
+	switch (len)
+	{
+	case 0:
+		DSI(_DSIREG(DSI_WR_DATA)) = (cmd << 8) | MIPI_DSI_DCS_SHORT_WRITE;
+		break;
+
+	case 1:
+		DSI(_DSIREG(DSI_WR_DATA)) = ((cmd | (*(u8 *)data << 8)) << 8) | MIPI_DSI_DCS_SHORT_WRITE_PARAM;
+		break;
+
+	default:
+		fifo32 = calloc(DSI_STATUS_RX_FIFO_SIZE * 8, 4);
+		fifo8 = (u8 *)fifo32;
+		fifo32[0] = (len << 8) | MIPI_DSI_DCS_LONG_WRITE;
+		fifo8[4] = cmd;
+		memcpy(&fifo8[5], data, len);
+		len += 4 + 1; // Increase length by CMD/length word and DCS CMD.
+		for (u32 i = 0; i < (ALIGN(len, 4) / 4); i++)
+			DSI(_DSIREG(DSI_WR_DATA)) = fifo32[i];
+		free(fifo32);
+		break;
+	}
+
+	// Wait for vblank before reseting sync points.
+	DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
+	while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
+		;
+
+	// Reset all states of syncpt block.
+	DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET;
+	usleep(300); // Stabilization delay.
+
+	// Clear syncpt block reset.
+	DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0;
+	usleep(300); // Stabilization delay.
+
+	// Restore video mode and host control.
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
+
+	// Disable and clear vblank interrupt.
+	DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0;
+	DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT;
+}
+
+void display_init()
+{
+	// Get Hardware type, as it's used in various DI functions.
+	nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA;
+
+	// Check if display is already initialized.
+	if (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_DISP1))
+		_display_panel_and_hw_end(true);
+
+	// Get Chip ID.
+	bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
+
+	// T210B01: Power on SD2 regulator for supplying LDO0.
+	if (!tegra_t210)
+	{
+		// Set SD2 regulator voltage.
+		max7762x_regulator_set_voltage(REGULATOR_SD2, 1325000);
+
+		// Set slew rate and enable SD2 regulator.
+		i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) | MAX77620_SD_CFG1_FSRADE_SD_ENABLE);
+		max7762x_regulator_enable(REGULATOR_SD2, true);
+
+	}
+
+	// Enable power to display panel controller.
+	max7762x_regulator_set_voltage(REGULATOR_LDO0, 1200000);
+	max7762x_regulator_enable(REGULATOR_LDO0, true);
+
+	if (tegra_t210)
+		max77620_config_gpio(7, MAX77620_GPIO_OUTPUT_ENABLE); // T210: LD0 -> GPIO7 -> Display panel.
+
+	// Enable Display Interface specific clocks.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL);
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
+
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP);
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10;           // Set PLLP_OUT and div 6 (68MHz).
+
+	// Bring every IO rail out of deep power down.
+	PMC(APBDEV_PMC_IO_DPD_REQ)  = PMC_IO_DPD_REQ_DPD_OFF;
+	PMC(APBDEV_PMC_IO_DPD2_REQ) = PMC_IO_DPD_REQ_DPD_OFF;
+
+	// Configure LCD pins.
+	PINMUX_AUX(PINMUX_AUX_NFC_EN)     &= ~PINMUX_TRISTATE; // PULL_DOWN
+	PINMUX_AUX(PINMUX_AUX_NFC_INT)    &= ~PINMUX_TRISTATE; // PULL_DOWN
+	PINMUX_AUX(PINMUX_AUX_LCD_RST)    &= ~PINMUX_TRISTATE; // PULL_DOWN
+
+	// Configure Backlight pins.
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_EN)  &= ~PINMUX_TRISTATE; // PULL_DOWN
+
+	if (nx_aula)
+	{
+		// Configure LCD RST pin.
+		gpio_config(GPIO_PORT_V, GPIO_PIN_2, GPIO_MODE_GPIO);
+		gpio_output_enable(GPIO_PORT_V, GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
+	}
+	else
+	{
+		// Set LCD +-5V pins mode and direction
+		gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO);
+		gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE);
+
+		// Enable LCD power.
+		gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // LCD +5V enable.
+		usleep(10000);
+		gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // LCD -5V enable.
+		usleep(10000);
+
+		// Configure Backlight PWM/EN and LCD RST pins (BL PWM, BL EN, LCD RST).
+		gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO);
+		gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
+
+		 // Enable Backlight power.
+		gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH);
+	}
+
+	// Power up supply regulator for display interface.
+	MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0;
+
+	if (!tegra_t210)
+	{
+		MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG0)) = 0;
+		APB_MISC(APB_MISC_GP_DSI_PAD_CONTROL) = 0;
+	}
+
+	// Set DISP1 clock source and parent clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT.
+	u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 97.5 MHz (offset).
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
+
+	if (tegra_t210)
+	{
+		CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;     // PLLD_SETUP.
+		CLOCK(CLK_RST_CONTROLLER_PLLD_MISC)  = 0x2D0AAA; // PLLD_ENABLE_CLK.
+	}
+	else
+	{
+		CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0;
+		CLOCK(CLK_RST_CONTROLLER_PLLD_MISC)  = 0x2DFC00; // PLLD_ENABLE_CLK.
+	}
+
+	// Setup Display Interface initial window configuration.
+	exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94);
+
+	// Setup display communication interfaces.
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part1, 8);
+	if (tegra_t210)
+		DSI(_DSIREG(DSI_INIT_SEQ_DATA_15)) = 0;
+	else
+		DSI(_DSIREG(DSI_INIT_SEQ_DATA_15_B01)) = 0;
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part2, 14);
+	if (!tegra_t210)
+		exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part3_t210b01, 7);
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part4, 10);
+	DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part5, 12);
+	DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part6, 14);
+	usleep(10000);
+
+	// Enable LCD Reset.
+	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH);
+	usleep(60000);
+
+	// Setup DSI device takeover timeout.
+	DSI(_DSIREG(DSI_BTA_TIMING)) = nx_aula ? 0x40103 : 0x50204;
+
+	// Get Display ID.
+	_display_id = 0xCCCCCC;
+	for (u32 i = 0; i < 3; i++)
+	{
+		if (!display_dsi_read(MIPI_DCS_GET_DISPLAY_ID, 3, &_display_id, DSI_VIDEO_DISABLED))
+			break;
+
+		usleep(10000);
+	}
+
+	// Save raw Display ID to Nyx storage.
+	nyx_str->info.disp_id = _display_id;
+
+	// Decode Display ID.
+	_display_id = ((_display_id >> 8) & 0xFF00) | (_display_id & 0xFF);
+
+	if ((_display_id & 0xFF) == PANEL_JDI_XXX062M)
+		_display_id = PANEL_JDI_XXX062M;
+
+	// For Aula ensure that we have a compatible panel id.
+	if (nx_aula && _display_id == 0xCCCC)
+		_display_id = PANEL_SAM_AMS699VC01;
+
+	// Initialize display panel.
+	switch (_display_id)
+	{
+	case PANEL_SAM_AMS699VC01:
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xA0, 0); // Write 0 to 0xA0.
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_SET_CONTROL_DISPLAY | (DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL << 8), 0); // Enable brightness control.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x339;    // MIPI_DSI_DCS_LONG_WRITE: 3 bytes.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x000051; // MIPI_DCS_SET_BRIGHTNESS 0000: 0%. FF07: 100%.
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+		break;
+
+	case PANEL_JDI_XXX062M:
+		exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43);
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
+		break;
+
+	case PANEL_INL_P062CCA_AZ1:
+	case PANEL_AUO_A062TAN01:
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
+
+		// Unlock extension cmds.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x439;          // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9;     // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+
+		// Set Power control.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x739;          // MIPI_DSI_DCS_LONG_WRITE: 7 bytes.
+		if (_display_id == PANEL_INL_P062CCA_AZ1)
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
+		else // PANEL_AUO_A062TAN01.
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x143209;       // (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32).
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+		break;
+
+	case PANEL_INL_2J055IA_27A:
+	case PANEL_AUO_A055TAN01:
+	case PANEL_V40_55_UNK:
+	default: // Allow spare part displays to work.
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 120000);
+		break;
+	}
+
+	// Unblank display.
+	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000);
+
+	// Configure PLLD for DISP1.
+	plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 234 MHz (offset, it's ddr btw, so normally div2).
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
+
+	if (tegra_t210)
+		CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; // PLLD_SETUP.
+	else
+		CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0;
+	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00;  // Use new PLLD_SDM_DIN.
+
+	// Finalize DSI configuration.
+	DSI(_DSIREG(DSI_PAD_CONTROL_1)) = 0;
+	DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 19);
+	// Set pixel clock dividers: 234 / 3 / 1 = 78 MHz (offset) for 60 Hz.
+	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4); // 4: div3.
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10);
+	usleep(10000);
+
+	// Calibrate display communication pads.
+	u32 loops = tegra_t210 ? 1 : 2; // Find out why this is done 2 times on Mariko.
+	exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 4);
+	for (u32 i = 0; i < loops; i++)
+	{
+		// Set MIPI bias pad config.
+		MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0x10010;
+		MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG1)) = tegra_t210 ? 0x300 : 0;
+
+		// Set pad trimmers and set MIPI DSI cal offsets.
+		if (tegra_t210)
+		{
+			exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config_t210, 4);
+			exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_dsi_cal_offsets_config_t210, 4);
+		}
+		else
+		{
+			exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config_t210b01, 7);
+			exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_dsi_cal_offsets_config_t210b01, 4);
+		}
+
+		// Set the rest of MIPI cal offsets and apply calibration.
+		exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 12);
+	}
+	usleep(10000);
+
+	// Enable video display controller.
+	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113);
+}
+
+void display_backlight_pwm_init()
+{
+	if (_display_id == PANEL_SAM_AMS699VC01)
+		return;
+
+	clock_enable_pwm();
+
+	PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; // Enable PWM and set it to 25KHz PFM. 29.5KHz is stock.
+
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode.
+	gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
+}
+
+void display_backlight(bool enable)
+{
+	gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO.
+}
+
+void display_dsi_backlight_brightness(u32 brightness)
+{
+	// Normalize brightness value by 82% and a base of 45 duty.
+	if (brightness)
+		brightness = (brightness * PANEL_OLED_BL_COEFF / 100) + PANEL_OLED_BL_OFFSET;
+
+	u16 bl_ctrl = byte_swap_16((u16)(brightness * 8));
+	display_dsi_vblank_write(MIPI_DCS_SET_BRIGHTNESS, 2, &bl_ctrl);
+}
+
+void display_pwm_backlight_brightness(u32 brightness, u32 step_delay)
+{
+	u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF;
+	if (brightness == old_value)
+		return;
+
+	if (old_value < brightness)
+	{
+		for (u32 i = old_value; i < brightness + 1; i++)
+		{
+			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16);
+			usleep(step_delay);
+		}
+	}
+	else
+	{
+		for (u32 i = old_value; i > brightness; i--)
+		{
+			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16);
+			usleep(step_delay);
+		}
+	}
+	if (!brightness)
+		PWM(PWM_CONTROLLER_PWM_CSR_0) = 0;
+}
+
+void display_backlight_brightness(u32 brightness, u32 step_delay)
+{
+	if (brightness > 255)
+		brightness = 255;
+
+	if (_display_id != PANEL_SAM_AMS699VC01)
+		display_pwm_backlight_brightness(brightness, step_delay);
+	else
+		display_dsi_backlight_brightness(brightness);
+}
+
+u32 display_get_backlight_brightness()
+{
+	return ((PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF);
+}
+
+static void _display_panel_and_hw_end(bool no_panel_deinit)
+{
+	if (no_panel_deinit)
+		goto skip_panel_deinit;
+
+	display_backlight_brightness(0, 1000);
+
+	// Enable host cmd packets during video.
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
+
+	// Blank display.
+	DSI(_DSIREG(DSI_WR_DATA)) = (MIPI_DCS_SET_DISPLAY_OFF << 8) | MIPI_DSI_DCS_SHORT_WRITE;
+
+	// Propagate changes to all register buffers and disable host cmd packets during video.
+	DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
+
+	// De-initialize video controller.
+	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17);
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16);
+
+	if (_display_id != PANEL_SAM_AMS699VC01)
+		usleep(10000);
+
+	// De-initialize display panel.
+	switch (_display_id)
+	{
+	case PANEL_JDI_XXX062M:
+		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22);
+		break;
+
+	case PANEL_AUO_A062TAN01:
+		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_auo, 37);
+		break;
+
+	case PANEL_INL_2J055IA_27A:
+	case PANEL_AUO_A055TAN01:
+	case PANEL_V40_55_UNK:
+		// Unlock extension cmds.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x439;          // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9;     // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+
+		// Set Power control.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0xB39;          // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
+		if (_display_id == PANEL_INL_2J055IA_27A)
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
+		else if (_display_id == PANEL_AUO_A055TAN01)
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
+		else // PANEL_V40_55_UNK.
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x731348B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT3 / XDK, VRH gamma volt adj 51 / x40).
+		if (_display_id == PANEL_INL_2J055IA_27A || _display_id == PANEL_AUO_A055TAN01)
+		{
+			// (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x71143209;
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x114D31;   // (Unknown).
+		}
+		else // PANEL_V40_55_UNK.
+		{
+			// (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/48, Enter standby / PON / VCOMG).
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x71243209;
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x004C31;   // (Unknown).
+		}
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+		break;
+
+	case PANEL_INL_P062CCA_AZ1:
+	default:
+		break;
+	}
+
+	// Blank - powerdown.
+	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_ENTER_SLEEP_MODE,
+		(_display_id == PANEL_SAM_AMS699VC01) ? 120000 : 50000);
+
+skip_panel_deinit:
+	// Disable LCD power pins.
+	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW);     // LCD Reset disable.
+
+	if (!nx_aula) // HOS uses panel id.
+	{
+		usleep(10000);
+		gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); // LCD -5V disable.
+		usleep(10000);
+		gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); // LCD +5V disable.
+		usleep(10000);
+	}
+	else
+		usleep(30000); // Aula Panel.
+
+	// Disable Display Interface specific clocks.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+
+	// Power down pads.
+	DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
+	DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
+
+	// Switch LCD PWM backlight pin to special function mode and enable PWM0 mode.
+	if (!nx_aula)
+	{
+		gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
+		PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
+		PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode.
+	}
+}
+
+void display_end() { _display_panel_and_hw_end(false); };
+
+u16 display_get_decoded_panel_id()
+{
+	return _display_id;
+}
+
+void display_set_decoded_panel_id(u32 id)
+{
+	// Get Hardware type, as it's used in various DI functions.
+	nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA;
+
+	// Decode Display ID.
+	_display_id = ((id >> 8) & 0xFF00) | (id & 0xFF);
+
+	if ((_display_id & 0xFF) == PANEL_JDI_XXX062M)
+		_display_id = PANEL_JDI_XXX062M;
+
+	// For Aula ensure that we have a compatible panel id.
+	if (nx_aula && _display_id == 0xCCCC)
+		_display_id = PANEL_SAM_AMS699VC01;
+}
+
+void display_color_screen(u32 color)
+{
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8);
+
+	// Configure display to show single color.
+	DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
+	DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
+	DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
+	DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
+	usleep(35000); // No need to wait on Aula.
+
+	if (_display_id != PANEL_SAM_AMS699VC01)
+		display_backlight(true);
+	else
+		display_backlight_brightness(255, 0);
+}
+
+u32 *display_init_framebuffer_pitch()
+{
+	// Sanitize framebuffer area.
+	memset((u32 *)IPL_FB_ADDRESS, 0, 0x3C0000);
+
+	// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32);
+	usleep(35000); // No need to wait on Aula.
+
+	return (u32 *)IPL_FB_ADDRESS;
+}
+
+u32 *display_init_framebuffer_pitch_inv()
+{
+	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch_inv, 34);
+	usleep(35000); // No need to wait on Aula.
+
+	return (u32 *)NYX_FB_ADDRESS;
+}
+
+u32 *display_init_framebuffer_block()
+{
+	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 34);
+	usleep(35000); // No need to wait on Aula.
+
+	return (u32 *)NYX_FB_ADDRESS;
+}
+
+u32 *display_init_framebuffer_log()
+{
+	// This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_log, 20);
+
+	return (u32 *)LOG_FB_ADDRESS;
+}
+
+void display_activate_console()
+{
+	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D.
+	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD.
+	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+
+	for (u32 i = 0xFF80; i < 0x10000; i++)
+	{
+		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+		usleep(1000);
+	}
+
+	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+}
+
+void display_deactivate_console()
+{
+	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D.
+
+	for (u32 i = 0xFFFF; i > 0xFF7F; i--)
+	{
+		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+		usleep(500);
+	}
+
+	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
+	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; // Disable window DD.
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+}
+
+void display_init_cursor(void *crs_fb, u32 size)
+{
+	// Setup cursor.
+	DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10);
+	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) =
+		CURSOR_BLEND_R8G8B8A8 | CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF;
+
+	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) |= CURSOR_ENABLE;
+
+	// Arm and activate changes.
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
+}
+
+void display_set_pos_cursor(u32 x, u32 y)
+{
+	DISPLAY_A(_DIREG(DC_DISP_CURSOR_POSITION)) = x | (y << 16);
+
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
+}
+
+void display_deinit_cursor()
+{
+	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = 0;
+	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) &= ~CURSOR_ENABLE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
+}

bdk/display/di.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -21,6 +21,9 @@
 #include <memory_map.h>
 #include <utils/types.h>
 
+#define DSI_VIDEO_DISABLED 0
+#define DSI_VIDEO_ENABLED  1
+
 /*! Display registers. */
 #define _DIREG(reg) ((reg) * 4)
 
@@ -42,11 +45,11 @@
 #define DC_CMD_GENERAL_INCR_SYNCPT 0x00
 
 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
-#define  SYNCPT_CNTRL_NO_STALL   (1 << 8)
+#define  SYNCPT_CNTRL_SOFT_RESET BIT(0)
-#define  SYNCPT_CNTRL_SOFT_RESET (1 << 0)
+#define  SYNCPT_CNTRL_NO_STALL   BIT(8)
 
 #define DC_CMD_CONT_SYNCPT_VSYNC 0x28
-#define  SYNCPT_VSYNC_ENABLE (1 << 8)
+#define  SYNCPT_VSYNC_ENABLE BIT(8)
 
 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
 
@@ -57,42 +60,43 @@
 #define  DISP_CTRL_MODE_MASK       (3 << 5)
 
 #define DC_CMD_DISPLAY_POWER_CONTROL 0x36
-#define  PW0_ENABLE (1 <<  0)
+#define  PW0_ENABLE BIT(0)
-#define  PW1_ENABLE (1 <<  2)
+#define  PW1_ENABLE BIT(2)
-#define  PW2_ENABLE (1 <<  4)
+#define  PW2_ENABLE BIT(4)
-#define  PW3_ENABLE (1 <<  6)
+#define  PW3_ENABLE BIT(6)
-#define  PW4_ENABLE (1 <<  8)
+#define  PW4_ENABLE BIT(8)
-#define  PM0_ENABLE (1 << 16)
+#define  PM0_ENABLE BIT(16)
-#define  PM1_ENABLE (1 << 18)
+#define  PM1_ENABLE BIT(18)
 
 #define DC_CMD_INT_STATUS 0x37
 #define DC_CMD_INT_MASK 0x38
 #define DC_CMD_INT_ENABLE 0x39
+#define  DC_CMD_INT_FRAME_END_INT BIT(1)
 
 #define DC_CMD_STATE_ACCESS 0x40
-#define  READ_MUX  (1 << 0)
+#define  READ_MUX  BIT(0)
-#define  WRITE_MUX (1 << 2)
+#define  WRITE_MUX BIT(2)
 
 #define DC_CMD_STATE_CONTROL 0x41
-#define  GENERAL_ACT_REQ (1 <<  0)
+#define  GENERAL_ACT_REQ BIT(0)
-#define  WIN_A_ACT_REQ   (1 <<  1)
+#define  WIN_A_ACT_REQ   BIT(1)
-#define  WIN_B_ACT_REQ   (1 <<  2)
+#define  WIN_B_ACT_REQ   BIT(2)
-#define  WIN_C_ACT_REQ   (1 <<  3)
+#define  WIN_C_ACT_REQ   BIT(3)
-#define  WIN_D_ACT_REQ   (1 <<  4)
+#define  WIN_D_ACT_REQ   BIT(4)
-#define  CURSOR_ACT_REQ  (1 <<  7)
+#define  CURSOR_ACT_REQ  BIT(7)
-#define  GENERAL_UPDATE  (1 <<  8)
+#define  GENERAL_UPDATE  BIT(8)
-#define  WIN_A_UPDATE    (1 <<  9)
+#define  WIN_A_UPDATE    BIT(9)
-#define  WIN_B_UPDATE    (1 << 10)
+#define  WIN_B_UPDATE    BIT(10)
-#define  WIN_C_UPDATE    (1 << 11)
+#define  WIN_C_UPDATE    BIT(11)
-#define  WIN_D_UPDATE    (1 << 12)
+#define  WIN_D_UPDATE    BIT(12)
-#define  CURSOR_UPDATE   (1 << 15)
+#define  CURSOR_UPDATE   BIT(15)
-#define  NC_HOST_TRIG    (1 << 24)
+#define  NC_HOST_TRIG    BIT(24)
 
 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
-#define  WINDOW_A_SELECT (1 << 4)
+#define  WINDOW_A_SELECT BIT(4)
-#define  WINDOW_B_SELECT (1 << 5)
+#define  WINDOW_B_SELECT BIT(5)
-#define  WINDOW_C_SELECT (1 << 6)
+#define  WINDOW_C_SELECT BIT(6)
-#define  WINDOW_D_SELECT (1 << 7)
+#define  WINDOW_D_SELECT BIT(7)
 
 #define DC_CMD_REG_ACT_CONTROL 0x043
 
@@ -125,12 +129,13 @@
 
 // DC_DISP shadowed registers.
 #define DC_DISP_DISP_WIN_OPTIONS 0x402
-#define  HDMI_ENABLE     (1 << 30)
+#define  CURSOR_ENABLE   BIT(16)
-#define  DSI_ENABLE      (1 << 29)
+#define  SOR_ENABLE      BIT(25)
-#define  SOR1_TIMING_CYA (1 << 27)
+#define  SOR1_ENABLE     BIT(26)
-#define  SOR1_ENABLE     (1 << 26)
+#define  SOR1_TIMING_CYA BIT(27)
-#define  SOR_ENABLE      (1 << 25)
+#define  DSI_ENABLE      BIT(29)
-#define  CURSOR_ENABLE   (1 << 16)
+#define  HDMI_ENABLE     BIT(30)
+
 
 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
@@ -142,6 +147,7 @@
 #define DC_DISP_FRONT_PORCH 0x40A
 
 #define DC_DISP_DISP_CLOCK_CONTROL 0x42E
+#define  SHIFT_CLK_DIVIDER(x)    ((x) & 0xff)
 #define  PIXEL_CLK_DIVIDER_PCD1  (0 << 8)
 #define  PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
 #define  PIXEL_CLK_DIVIDER_PCD2  (2 << 8)
@@ -155,7 +161,6 @@
 #define  PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
 #define  PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
 #define  PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
-#define  SHIFT_CLK_DIVIDER(x)    ((x) & 0xff)
 
 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
 #define  DISP_DATA_FORMAT_DF1P1C    (0 << 0)
@@ -189,8 +194,8 @@
 #define  BASE_COLOR_SIZE_888    (8 << 0)
 
 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
-#define  SC1_H_QUALIFIER_NONE	(1 << 16)
+#define  SC0_H_QUALIFIER_NONE	BIT(0)
-#define  SC0_H_QUALIFIER_NONE	(1 <<  0)
+#define  SC1_H_QUALIFIER_NONE	BIT(16)
 
 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432
 #define  DE_SELECT_ACTIVE_BLANK  (0 << 0)
@@ -217,6 +222,7 @@
 #define  CURSOR_SIZE_128 (2 << 24)
 #define  CURSOR_SIZE_256 (3 << 24)
 #define DC_DISP_CURSOR_POSITION      0x440
+#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
 #define DC_DISP_CURSOR_START_ADDR_HI 0x4EC
 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1
 #define  CURSOR_BLEND_2BIT     (0 << 24)
@@ -247,12 +253,12 @@
 
 // The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
 #define DC_WIN_WIN_OPTIONS 0x700
-#define  H_DIRECTION  (1 <<  0)
+#define  H_DIRECTION  BIT(0)
-#define  V_DIRECTION  (1 <<  2)
+#define  V_DIRECTION  BIT(2)
-#define  SCAN_COLUMN  (1 <<  4)
+#define  SCAN_COLUMN  BIT(4)
-#define  COLOR_EXPAND (1 <<  6)
+#define  COLOR_EXPAND BIT(6)
-#define  CSC_ENABLE   (1 << 18)
+#define  CSC_ENABLE   BIT(18)
-#define  WIN_ENABLE   (1 << 30)
+#define  WIN_ENABLE   BIT(30)
 
 #define DC_WIN_BUFFER_CONTROL 0x702
 #define  BUFFER_CONTROL_HOST  0
@@ -358,6 +364,10 @@
 /*! Display serial interface registers. */
 #define _DSIREG(reg) ((reg) * 4)
 
+#define DSI_INCR_SYNCPT_CNTRL 0x1
+#define  DSI_INCR_SYNCPT_SOFT_RESET BIT(0)
+#define  DSI_INCR_SYNCPT_NO_STALL   BIT(8)
+
 #define DSI_RD_DATA 0x9
 #define DSI_WR_DATA 0xA
 
@@ -369,39 +379,42 @@
 #define DSI_INT_MASK 0xE
 
 #define DSI_HOST_CONTROL 0xF
-#define  DSI_HOST_CONTROL_FIFO_RESET   (1 << 21)
+#define  DSI_HOST_CONTROL_ECC          BIT(0)
-#define  DSI_HOST_CONTROL_CRC_RESET    (1 << 20)
+#define  DSI_HOST_CONTROL_CS           BIT(1)
+#define  DSI_HOST_CONTROL_PKT_BTA      BIT(2)
+#define  DSI_HOST_CONTROL_IMM_BTA      BIT(3)
+#define  DSI_HOST_CONTROL_FIFO_SEL     BIT(4)
+#define  DSI_HOST_CONTROL_HS           BIT(5)
+#define  DSI_HOST_CONTROL_RAW          BIT(6)
 #define  DSI_HOST_CONTROL_TX_TRIG_SOL  (0 << 12)
 #define  DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
 #define  DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
-#define  DSI_HOST_CONTROL_RAW          (1 << 6)
+#define  DSI_HOST_CONTROL_CRC_RESET    BIT(20)
-#define  DSI_HOST_CONTROL_HS           (1 << 5)
+#define  DSI_HOST_CONTROL_FIFO_RESET   BIT(21)
-#define  DSI_HOST_CONTROL_FIFO_SEL     (1 << 4)
-#define  DSI_HOST_CONTROL_IMM_BTA      (1 << 3)
-#define  DSI_HOST_CONTROL_PKT_BTA      (1 << 2)
-#define  DSI_HOST_CONTROL_CS           (1 << 1)
-#define  DSI_HOST_CONTROL_ECC          (1 << 0)
 
 #define DSI_CONTROL 0x10
-#define  DSI_CONTROL_HS_CLK_CTRL  (1 << 20)
+#define  DSI_CONTROL_HOST_ENABLE  BIT(0)
-#define  DSI_CONTROL_CHANNEL(c)   (((c) & 0x3) << 16)
+#define  DSI_CONTROL_VIDEO_ENABLE BIT(1)
-#define  DSI_CONTROL_FORMAT(f)    (((f) & 0x3) << 12)
-#define  DSI_CONTROL_TX_TRIG(x)   (((x) & 0x3) <<  8)
-#define  DSI_CONTROL_LANES(n)     (((n) & 0x3) <<  4)
-#define  DSI_CONTROL_DCS_ENABLE   (1 << 3)
 #define  DSI_CONTROL_SOURCE(s)    (((s) & 0x1) <<  2)
-#define  DSI_CONTROL_VIDEO_ENABLE (1 << 1)
+#define  DSI_CONTROL_DCS_ENABLE   BIT(3)
-#define  DSI_CONTROL_HOST_ENABLE  (1 << 0)
+#define  DSI_CONTROL_LANES(n)     (((n) & 0x3) <<  4)
+#define  DSI_CONTROL_TX_TRIG(x)   (((x) & 0x3) <<  8)
+#define  DSI_CONTROL_FORMAT(f)    (((f) & 0x3) << 12)
+#define  DSI_CONTROL_CHANNEL(c)   (((c) & 0x3) << 16)
+#define  DSI_CONTROL_HS_CLK_CTRL  BIT(20)
 
 #define DSI_SOL_DELAY 0x11
 #define DSI_MAX_THRESHOLD 0x12
 
 #define DSI_TRIGGER 0x13
-#define  DSI_TRIGGER_HOST  (1 << 1)
+#define  DSI_TRIGGER_VIDEO BIT(0)
-#define  DSI_TRIGGER_VIDEO (1 << 0)
+#define  DSI_TRIGGER_HOST  BIT(1)
 
 #define DSI_TX_CRC 0x14
+
 #define DSI_STATUS 0x15
+#define  DSI_STATUS_RX_FIFO_SIZE 0x1F
+
 #define DSI_INIT_SEQ_CONTROL 0x1A
 #define DSI_INIT_SEQ_DATA_0 0x1B
 #define DSI_INIT_SEQ_DATA_1 0x1C
@@ -430,36 +443,53 @@
 #define DSI_BTA_TIMING 0x3F
 
 #define DSI_TIMEOUT_0 0x44
-#define  DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
 #define  DSI_TIMEOUT_HTX(x) (((x) & 0xffff) <<  0)
+#define  DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
 
 #define DSI_TIMEOUT_1 0x45
-#define  DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
 #define  DSI_TIMEOUT_TA(x) (((x) & 0xffff) <<  0)
+#define  DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
 
 #define DSI_TO_TALLY 0x46
 
 #define DSI_PAD_CONTROL_0 0x4B
-#define  DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
+#define  DSI_PAD_CONTROL_VS1_PDIO_CLK   BIT(8)
-#define  DSI_PAD_CONTROL_VS1_PULLDN(x)  (((x) & 0xf) << 16)
-#define  DSI_PAD_CONTROL_VS1_PDIO_CLK   (1 <<  8)
 #define  DSI_PAD_CONTROL_VS1_PDIO(x)    (((x) & 0xf) <<  0)
+#define  DSI_PAD_CONTROL_VS1_PULLDN_CLK BIT(24)
+#define  DSI_PAD_CONTROL_VS1_PULLDN(x)  (((x) & 0xf) << 16)
 
 #define DSI_PAD_CONTROL_CD 0x4C
 #define DSI_VIDEO_MODE_CONTROL 0x4E
 #define  DSI_CMD_PKT_VID_ENABLE 1
+#define  DSI_DSI_LINE_TYPE(x) ((x) << 1)
 
 #define DSI_PAD_CONTROL_1 0x4F
 #define DSI_PAD_CONTROL_2 0x50
 
 #define DSI_PAD_CONTROL_3 0x51
-#define  DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
-#define  DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
-#define  DSI_PAD_PREEMP_PD(x)     (((x) & 0x3) << 4)
 #define  DSI_PAD_PREEMP_PU(x)     (((x) & 0x3) << 0)
+#define  DSI_PAD_PREEMP_PD(x)     (((x) & 0x3) << 4)
+#define  DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
+#define  DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
 
 #define DSI_PAD_CONTROL_4 0x52
+#define DSI_PAD_CONTROL_5_B01 0x53
+#define DSI_PAD_CONTROL_6_B01 0x54
+#define DSI_PAD_CONTROL_7_B01 0x55
 #define DSI_INIT_SEQ_DATA_15 0x5F
+#define DSI_INIT_SEQ_DATA_15_B01 0x62
+
+/*! DSI packet defines */
+#define DSI_ESCAPE_CMD	0x87
+#define DSI_ACK_NO_ERR	0x84
+
+#define ACK_ERROR_RES   0x02
+#define GEN_LONG_RD_RES 0x1A
+#define DCS_LONG_RD_RES 0x1C
+#define GEN_1_BYTE_SHORT_RD_RES 0x11
+#define DCS_1_BYTE_SHORT_RD_RES 0x21
+#define GEN_2_BYTE_SHORT_RD_RES 0x12
+#define DCS_2_BYTE_SHORT_RD_RES 0x22
 
 /*! MIPI registers. */
 #define MIPI_CAL_MIPI_CAL_CTRL          (0x00 / 0x4)
@@ -483,25 +513,187 @@
 #define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4)
 
 /*! MIPI CMDs. */
+#define MIPI_DSI_V_SYNC_START        0x01
+#define MIPI_DSI_COLOR_MODE_OFF      0x02
+#define MIPI_DSI_END_OF_TRANSMISSION 0x08
+#define MIPI_DSI_NULL_PACKET         0x09
+#define MIPI_DSI_V_SYNC_END          0x11
+#define MIPI_DSI_COLOR_MODE_ON       0x12
+#define MIPI_DSI_BLANKING_PACKET     0x19
+#define MIPI_DSI_H_SYNC_START        0x21
+#define MIPI_DSI_SHUTDOWN_PERIPHERAL 0x22
+#define MIPI_DSI_H_SYNC_END          0x31
+#define MIPI_DSI_TURN_ON_PERIPHERAL  0x32
+#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
+
 #define MIPI_DSI_DCS_SHORT_WRITE       0x05
 #define MIPI_DSI_DCS_READ              0x06
 #define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15
-#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
 #define MIPI_DSI_DCS_LONG_WRITE        0x39
 
+#define MIPI_DSI_GENERIC_LONG_WRITE           0x29
+#define MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM  0x03
+#define MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM  0x13
+#define MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM  0x23
+#define MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM 0x04
+#define MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM 0x14
+#define MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM 0x24
+
 /*! MIPI DCS CMDs. */
+#define MIPI_DCS_NOP                   0x00
+#define MIPI_DCS_SOFT_RESET            0x01
+#define MIPI_DCS_GET_COMPRESSION_MODE  0x03
 #define MIPI_DCS_GET_DISPLAY_ID        0x04
+#define MIPI_DCS_GET_DISPLAY_ID1       0xDA // GET_DISPLAY_ID Byte0, Module Manufacturer ID.
+#define MIPI_DCS_GET_DISPLAY_ID2       0xDB // GET_DISPLAY_ID Byte1, Module/Driver Version ID.
+#define MIPI_DCS_GET_DISPLAY_ID3       0xDC // GET_DISPLAY_ID Byte2, Module/Driver ID.
+#define MIPI_DCS_GET_NUM_ERRORS        0x05 // 1 byte.
+#define MIPI_DCS_GET_RED_CHANNEL       0x06
+#define MIPI_DCS_GET_GREEN_CHANNEL     0x07
+#define MIPI_DCS_GET_BLUE_CHANNEL      0x08
+#define MIPI_DCS_GET_DISPLAY_STATUS    0x09 // 4 bytes.
+#define MIPI_DCS_GET_POWER_MODE	       0x0A // 1 byte. 2: DISON, 3: NORON, 4: SLPOUT, 7: BSTON.
+#define MIPI_DCS_GET_ADDRESS_MODE      0x0B // Display Access Control. 1 byte. 0: GS, 1: SS, 3: BGR.
+#define MIPI_DCS_GET_PIXEL_FORMAT      0x0C // 1 byte. 4-6: DPI.
+#define MIPI_DCS_GET_DISPLAY_MODE      0x0D // 1 byte. 0-2: GCS, 3: ALLPOFF, 4: ALLPON, 5: INVON.
+#define MIPI_DCS_GET_SIGNAL_MODE       0x0E // 1 byte. 0: EODSI, 2: DEON, 3: PCLKON, 4: VSON, 5: HSON, 7: TEON.
+#define MIPI_DCS_GET_DIAGNOSTIC_RESULT 0x0F // 1 byte. 6: FUNDT, 7: REGLD.
 #define MIPI_DCS_ENTER_SLEEP_MODE      0x10
 #define MIPI_DCS_EXIT_SLEEP_MODE       0x11
+#define MIPI_DCS_ENTER_PARTIAL_MODE    0x12
+#define MIPI_DCS_ENTER_NORMAL_MODE     0x13
+#define MIPI_DCS_EXIT_INVERT_MODE      0x20
+#define MIPI_DCS_ENTER_INVERT_MODE     0x21
+#define MIPI_DCS_ALL_PIXELS_OFF        0x22
+#define MIPI_DCS_ALL_PIXELS_ON         0x23
+#define MIPI_DCS_SET_CONTRAST          0x25 // VCON in 40mV steps. 7-bit integer.
+#define MIPI_DCS_SET_GAMMA_CURVE       0x26 // 1 byte. 0-7: GC.
+#define MIPI_DCS_SET_DISPLAY_OFF       0x28
 #define MIPI_DCS_SET_DISPLAY_ON        0x29
+#define MIPI_DCS_SET_COLUMN_ADDRESS    0x2A
+#define MIPI_DCS_SET_PAGE_ADDRESS      0x2B
+#define MIPI_DCS_WRITE_MEMORY_START    0x2C
+#define MIPI_DCS_WRITE_LUT             0x2D // 24-bit: 192 bytes.
+#define MIPI_DCS_READ_MEMORY_START     0x2E
+#define MIPI_DCS_SET_PARTIAL_ROWS      0x30
+#define MIPI_DCS_SET_PARTIAL_COLUMNS   0x31
+#define MIPI_DCS_SET_SCROLL_AREA       0x33
+#define MIPI_DCS_SET_TEAR_OFF          0x34
+#define MIPI_DCS_SET_TEAR_ON           0x35
+#define MIPI_DCS_SET_ADDRESS_MODE      0x36 // Display Access Control. 1 byte. 0: GS, 1: SS, 3: BGR.
+#define MIPI_DCS_SET_SCROLL_START      0x37
+#define MIPI_DCS_EXIT_IDLE_MODE        0x38
+#define MIPI_DCS_ENTER_IDLE_MODE       0x39
+#define MIPI_DCS_SET_PIXEL_FORMAT      0x3A // 1 byte. 4-6: DPI.
+#define MIPI_DCS_WRITE_MEMORY_CONTINUE 0x3C
+#define MIPI_DCS_READ_MEMORY_CONTINUE  0x3E
+#define MIPI_DCS_GET_3D_CONTROL        0x3F
+#define MIPI_DCS_SET_VSYNC_TIMING      0x40
+#define MIPI_DCS_SET_TEAR_SCANLINE     0x44
+#define MIPI_DCS_GET_SCANLINE          0x45
+#define MIPI_DCS_SET_TEAR_SCANLINE_WIDTH 0x46
+#define MIPI_DCS_GET_SCANLINE_WIDTH    0x47
+#define MIPI_DCS_SET_BRIGHTNESS        0x51 // DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL. 1 byte. 0-7: DBV.
+#define MIPI_DCS_GET_BRIGHTNESS        0x52 // 1 byte. 0-7: DBV.
+#define MIPI_DCS_SET_CONTROL_DISPLAY   0x53 // 1 byte. 2: BL, 3: DD, 5: BCTRL.
+#define MIPI_DCS_GET_CONTROL_DISPLAY   0x54 // 1 byte. 2: BL, 3: DD, 5: BCTRL.
+#define MIPI_DCS_SET_CABC_VALUE        0x55 // 1 byte. 0-32: C, 4-7: C.
+#define MIPI_DCS_GET_CABC_VALUE        0x56 // 1 byte. 0-32: C, 4-7: C.
+#define MIPI_DCS_SET_CABC_MIN_BRI      0x5E // 1 byte. 0-7: CMB.
+#define MIPI_DCS_GET_CABC_MIN_BRI      0x5F // 1 byte. 0-7: CMB.
+#define MIPI_DCS_GET_AUTO_BRI_DIAG_RES 0x68 // 1 byte. 6-7: D.
+#define MIPI_DCS_READ_DDB_START        0xA1
+#define MIPI_DCS_READ_DDB_CONTINUE     0xA8 // 0x100 size.
+
+/*! MIPI DCS Panel Private CMDs. */
+#define MIPI_DCS_PRIV_UNK_A0            0xA0
+#define MIPI_DCS_PRIV_SET_POWER_CONTROL 0xB1
+#define MIPI_DCS_PRIV_SET_EXTC          0xB9 // Enable extended commands.
+#define MIPI_DCS_PRIV_UNK_BD            0xBD
+#define MIPI_DCS_PRIV_UNK_D5            0xD5
+#define MIPI_DCS_PRIV_UNK_D6            0xD6
+#define MIPI_DCS_PRIV_UNK_D8            0xD8
+#define MIPI_DCS_PRIV_UNK_D9            0xD9
+#define MIPI_DCS_PRIV_READ_EXTC_CMD_SPI 0xFE // Read EXTC Command In SPI. 1 byte. 0-6: EXT_SPI_CNT, 7:EXT_SP.
+#define MIPI_DCS_PRIV_SET_EXTC_CMD_REG  0xFF // EXTC Command Set enable register. 5 bytes. Pass: FF 98 06 04, PAGE.
+
+/*! MIPI DCS Panel Private CMDs PAGE 1. */
+#define MIPI_DCS_PRIV_GET_DISPLAY_ID4   0x00
+#define MIPI_DCS_PRIV_GET_DISPLAY_ID5   0x01
+#define MIPI_DCS_PRIV_GET_DISPLAY_ID6   0x02
+
+/*! MIPI DCS CMD Defines. */
+#define DCS_POWER_MODE_DISPLAY_ON           BIT(2)
+#define DCS_POWER_MODE_NORMAL_MODE          BIT(3)
+#define DCS_POWER_MODE_SLEEP_MODE           BIT(4)
+#define DCS_POWER_MODE_PARTIAL_MODE         BIT(5)
+#define DCS_POWER_MODE_IDLE_MODE            BIT(6)
+
+#define DCS_ADDRESS_MODE_V_FLIP             BIT(0)
+#define DCS_ADDRESS_MODE_H_FLIP             BIT(1)
+#define DCS_ADDRESS_MODE_LATCH_RL           BIT(2) // Latch Data Order.
+#define DCS_ADDRESS_MODE_BGR_COLOR          BIT(3)
+#define DCS_ADDRESS_MODE_LINE_ORDER         BIT(4) // Line Refresh Order.
+#define DCS_ADDRESS_MODE_SWAP_XY            BIT(5) // Page/Column Addressing Reverse Order.
+#define DCS_ADDRESS_MODE_MIRROR_X           BIT(6) // Column Address Order.
+#define DCS_ADDRESS_MODE_MIRROR_Y           BIT(7) // Page Address Order.
+#define DCS_ADDRESS_MODE_ROTATION_MASK      (0xF << 4)
+#define DCS_ADDRESS_MODE_ROTATION_90        (DCS_ADDRESS_MODE_SWAP_XY | DCS_ADDRESS_MODE_LINE_ORDER)
+#define DCS_ADDRESS_MODE_ROTATION_180       (DCS_ADDRESS_MODE_MIRROR_X | DCS_ADDRESS_MODE_LINE_ORDER)
+#define DCS_ADDRESS_MODE_ROTATION_270       (DCS_ADDRESS_MODE_SWAP_XY)
+
+#define DCS_GAMMA_CURVE_NONE                0
+#define DCS_GAMMA_CURVE_GC0_1_8             BIT(0)
+#define DCS_GAMMA_CURVE_GC1_2_5             BIT(1)
+#define DCS_GAMMA_CURVE_GC2_1_0             BIT(2)
+#define DCS_GAMMA_CURVE_GC3_1_0             BIT(3) // Are there more?
+
+#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL  BIT(2)
+#define DCS_CONTROL_DISPLAY_DIMMING_CTRL    BIT(3)
+#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5)
+
+#define PANEL_OLED_BL_COEFF  82 // 82%.
+#define PANEL_OLED_BL_OFFSET 45 // Least legible backlight duty.
 
 /* Switch Panels:
+ *
+ * 6.2" panels for Icosa and Iowa skus:
  * [10] 81 [26]: JDI LPM062M326A
  * [10] 96 [09]: JDI LAM062M109A
  * [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
- * [20] XX [10]: InnoLux P062CCA-AZ2 [UNCONFIRMED ID]
+ * [20] 95 [0F]: InnoLux P062CCA-AZ2 (Rev B1)
+ * [20] 96 [0F]: InnoLux P062CCA-AZ3 [UNCONFIRMED MODEL REV]
+ * [20] 98 [0F]: InnoLux P062CCA-??? [UNCONFIRMED MODEL REV]
  * [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
- * [30] XX [10]: AUO A062TAN02 (59.06A33.002) [UNCONFIRMED ID]
+ * [30] 95 [0F]: AUO A062TAN02 (59.06A33.002)
+ * [30] XX [0F]: AUO A062TAN03 (59.06A33.003) [UNCONFIRMED ID]
+ *
+ * 5.5" panels for Hoag skus:
+ * [20] 94 [10]: InnoLux 2J055IA-27A (Rev B1)
+ * [30] 93 [10]: AUO A055TAN01 (59.05A30.001)
+ * [40] XX [10]: Vendor 40 [UNCONFIRMED ID]
+ *
+ * 7.0" OLED panels for Aula skus:
+ * [50] 9B [20]: Samsung AMS699VC01-0 (Rev 2.5)
+ */
+
+/* Display ID Decoding:
+ *
+ * byte0: Vendor
+ * byte1: Model
+ * byte2: Board
+ *
+ * Vendors:
+ * 10h: Japan Display Inc.
+ * 20h: InnoLux Corporation
+ * 30h: AU Optronics
+ * 40h: Unknown0
+ * 50h: Samsung
+ *
+ * Boards, Panel Size:
+ * 0Fh: Icosa/Iowa, 6.2"
+ * 10h: Hoag,       5.5"
+ * 20h: Aula,       7.0"
  */
 
 enum
@@ -511,20 +703,27 @@ enum
 	PANEL_JDI_LPM062M326A = 0x2610,
 	PANEL_INL_P062CCA_AZ1 = 0x0F20,
 	PANEL_AUO_A062TAN01   = 0x0F30,
-	PANEL_INL_P062CCA_AZ2 = 0x1020,
+	PANEL_INL_2J055IA_27A = 0x1020,
-	PANEL_AUO_A062TAN02   = 0x1030
+	PANEL_AUO_A055TAN01   = 0x1030,
+	PANEL_V40_55_UNK      = 0x1040,
+	PANEL_SAM_AMS699VC01  = 0x2050
 };
 
 void display_init();
 void display_backlight_pwm_init();
 void display_end();
 
+/*! Get/Set Display panel ID. */
+u16  display_get_decoded_panel_id();
+void display_set_decoded_panel_id(u32 id);
+
 /*! Show one single color on the display. */
 void display_color_screen(u32 color);
 
 /*! Switches screen backlight ON/OFF. */
 void display_backlight(bool enable);
 void display_backlight_brightness(u32 brightness, u32 step_delay);
+u32  display_get_backlight_brightness();
 
 /*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
 u32 *display_init_framebuffer_pitch();
@@ -537,4 +736,7 @@ void display_init_cursor(void *crs_fb, u32 size);
 void display_set_pos_cursor(u32 x, u32 y);
 void display_deinit_cursor();
 
+void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled);
+int  display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled);
+
 #endif

bdk/display/di.inl

@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
-* Copyright (c) 2018-2019 CTCaer
+* Copyright (c) 2018-2020 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -20,7 +20,7 @@ static const cfg_op_t _display_dc_setup_win_config[94] = {
 	{DC_CMD_STATE_ACCESS, 0},
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_REG_ACT_CONTROL, 0x54},
+	{DC_CMD_REG_ACT_CONTROL, 0x54}, // Select H counter for win A/B/C.
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
@@ -96,16 +96,16 @@ static const cfg_op_t _display_dc_setup_win_config[94] = {
 	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
 	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
 	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-	{0x4E4, 0},
+	{DC_DISP_BLEND_BACKGROUND_COLOR, 0},
 	{DC_COM_CRC_CONTROL, 0},
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
@@ -120,7 +120,7 @@ static const cfg_op_t _display_dc_setup_win_config[94] = {
 };
 
 //DSI Init config.
-static const cfg_op_t _display_dsi_init_config[61] = {
+static const cfg_op_t _display_dsi_init_config_part1[8] = {
 	{DSI_WR_DATA, 0},
 	{DSI_INT_ENABLE, 0},
 	{DSI_INT_STATUS, 0},
@@ -128,8 +128,9 @@ static const cfg_op_t _display_dsi_init_config[61] = {
 	{DSI_INIT_SEQ_DATA_0, 0},
 	{DSI_INIT_SEQ_DATA_1, 0},
 	{DSI_INIT_SEQ_DATA_2, 0},
-	{DSI_INIT_SEQ_DATA_3, 0},
+	{DSI_INIT_SEQ_DATA_3, 0}
-	{DSI_INIT_SEQ_DATA_15, 0},
+};
+static const cfg_op_t _display_dsi_init_config_part2[14] = {
 	{DSI_DCS_CMDS, 0},
 	{DSI_PKT_SEQ_0_LO, 0},
 	{DSI_PKT_SEQ_1_LO, 0},
@@ -143,7 +144,18 @@ static const cfg_op_t _display_dsi_init_config[61] = {
 	{DSI_PKT_SEQ_3_HI, 0},
 	{DSI_PKT_SEQ_4_HI, 0},
 	{DSI_PKT_SEQ_5_HI, 0},
-	{DSI_CONTROL, 0},
+	{DSI_CONTROL, 0}
+};
+static const cfg_op_t _display_dsi_init_config_part3_t210b01[7] = {
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PAD_CONTROL_2, 0},
+	{DSI_PAD_CONTROL_3, 0},
+	{DSI_PAD_CONTROL_4, 0},
+	{DSI_PAD_CONTROL_5_B01, 0},
+	{DSI_PAD_CONTROL_6_B01, 0},
+	{DSI_PAD_CONTROL_7_B01, 0}
+};
+static const cfg_op_t _display_dsi_init_config_part4[10] = {
 	{DSI_PAD_CONTROL_CD, 0},
 	{DSI_SOL_DELAY, 0x18},
 	{DSI_MAX_THRESHOLD, 0x1E0},
@@ -153,8 +165,9 @@ static const cfg_op_t _display_dsi_init_config[61] = {
 	{DSI_PKT_LEN_2_3, 0},
 	{DSI_PKT_LEN_4_5, 0},
 	{DSI_PKT_LEN_6_7, 0},
-	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PAD_CONTROL_1, 0}
-	{DSI_PHY_TIMING_0, 0x6070601},
+};
+static const cfg_op_t _display_dsi_init_config_part5[12] = {
 	{DSI_PHY_TIMING_1, 0x40A0E05},
 	{DSI_PHY_TIMING_2, 0x30109},
 	{DSI_BTA_TIMING, 0x190A14},
@@ -166,8 +179,9 @@ static const cfg_op_t _display_dsi_init_config[61] = {
 	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
 	{DSI_POWER_CONTROL, 0},
 	{DSI_POWER_CONTROL, 0},
-	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PAD_CONTROL_1, 0}
-	{DSI_PHY_TIMING_0, 0x6070601},
+};
+static const cfg_op_t _display_dsi_init_config_part6[14] = {
 	{DSI_PHY_TIMING_1, 0x40A0E05},
 	{DSI_PHY_TIMING_2, 0x30118},
 	{DSI_BTA_TIMING, 0x190A14},
@@ -186,13 +200,13 @@ static const cfg_op_t _display_dsi_init_config[61] = {
 
 //DSI panel config.
 static const cfg_op_t _display_init_config_jdi[43] = {
-	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x0439},     // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
+	{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD.
+	{DSI_WR_DATA, 0xBD15},     // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0 to 0xBD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x1939},     // MIPI_DSI_DCS_LONG_WRITE: 25 bytes.
-	{DSI_WR_DATA, 0xAAAAAAD8},
+	{DSI_WR_DATA, 0xAAAAAAD8}, // Register: 0xD8.
 	{DSI_WR_DATA, 0xAAAAAAEB},
 	{DSI_WR_DATA, 0xAAEBAAAA},
 	{DSI_WR_DATA, 0xAAAAAAAA},
@@ -200,10 +214,10 @@ static const cfg_op_t _display_init_config_jdi[43] = {
 	{DSI_WR_DATA, 0xAAEBAAAA},
 	{DSI_WR_DATA, 0xAA},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x01BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x1BD.
+	{DSI_WR_DATA, 0x01BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 1 to 0xBD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x2739},     // MIPI_DSI_DCS_LONG_WRITE: 39 bytes.
-	{DSI_WR_DATA, 0xFFFFFFD8},
+	{DSI_WR_DATA, 0xFFFFFFD8}, // Register: 0xD8.
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFFFF},
@@ -214,27 +228,25 @@ static const cfg_op_t _display_init_config_jdi[43] = {
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFF},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x02BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x2BD.
+	{DSI_WR_DATA, 0x02BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 2 to 0xBD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0xF39},      // MIPI_DSI_DCS_LONG_WRITE: 15 bytes.
-	{DSI_WR_DATA, 0xFFFFFFD8},
+	{DSI_WR_DATA, 0xFFFFFFD8}, // Register: 0xD8.
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFF},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD.
+	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0 to 0xBD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x06D915},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x6D9.
+	{DSI_WR_DATA, 0x06D915},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 6 to 0xD9.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
+	{DSI_WR_DATA, 0x000000B9}, // MIPI_DCS_PRIV_SET_EXTC. Disable.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST}
 };
 
 //DSI packet config.
-static const cfg_op_t _display_dsi_packet_config[21] = {
+static const cfg_op_t _display_dsi_packet_config[19] = {
-	{DSI_PAD_CONTROL_1, 0},
-	{DSI_PHY_TIMING_0, 0x6070601},
 	{DSI_PHY_TIMING_1, 0x40A0E05},
 	{DSI_PHY_TIMING_2, 0x30172},
 	{DSI_BTA_TIMING, 0x190A14},
@@ -253,7 +265,7 @@ static const cfg_op_t _display_dsi_packet_config[21] = {
 	{DSI_PKT_LEN_2_3, 0x87001A2},
 	{DSI_PKT_LEN_4_5, 0x190},
 	{DSI_PKT_LEN_6_7, 0x190},
-	{DSI_HOST_CONTROL, 0},
+	{DSI_HOST_CONTROL, 0}
 };
 
 //DSI mode config.
@@ -271,29 +283,44 @@ static const cfg_op_t _display_dsi_mode_config[10] = {
 };
 
 //MIPI CAL config.
-static const cfg_op_t _display_mipi_pad_cal_config[6] = {
+static const cfg_op_t _display_mipi_pad_cal_config[4] = {
 	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0},
 	{MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000},
 	{MIPI_CAL_MIPI_BIAS_PAD_CFG0,  0},
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0},
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0}
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0x10010},
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG1,  0x300}
 };
 
 //DSI config.
-static const cfg_op_t _display_dsi_pad_cal_config[4] = {
+static const cfg_op_t _display_dsi_pad_cal_config_t210[4] = {
 	{DSI_PAD_CONTROL_1, 0},
 	{DSI_PAD_CONTROL_2, 0},
 	{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
 	{DSI_PAD_CONTROL_4, 0}
 };
+static const cfg_op_t _display_dsi_pad_cal_config_t210b01[7] = {
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PAD_CONTROL_2, 0},
+	{DSI_PAD_CONTROL_3, 0},
+	{DSI_PAD_CONTROL_4, 0x77777},
+	{DSI_PAD_CONTROL_5_B01, 0x77777},
+	{DSI_PAD_CONTROL_6_B01, 0x1111},
+	{DSI_PAD_CONTROL_7_B01, 0}
+};
 
 //MIPI CAL config.
-static const cfg_op_t _display_mipi_apply_dsi_cal_config[16] = {
+static const cfg_op_t _display_mipi_dsi_cal_offsets_config_t210[4] = {
 	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG,   0x200200},
 	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG,   0x200200},
 	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002},
-	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}
+};
+static const cfg_op_t _display_mipi_dsi_cal_offsets_config_t210b01[4] = {
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG,   0x200006},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG,   0x200006},
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}
+};
+static const cfg_op_t _display_mipi_apply_dsi_cal_config[12] = {
 	{MIPI_CAL_CILA_MIPI_CAL_CONFIG,   0},
 	{MIPI_CAL_CILB_MIPI_CAL_CONFIG,   0},
 	{MIPI_CAL_CILC_MIPI_CAL_CONFIG,   0},
@@ -372,16 +399,16 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
 	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
 	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
 	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-	{0x4E4, 0},
+	{DC_DISP_BLEND_BACKGROUND_COLOR, 0},
 	{DC_COM_CRC_CONTROL, 0},
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
@@ -394,14 +421,37 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
 	{DC_CMD_STATE_ACCESS, 0},
-	/* Set Display timings */
+
+	/* Set Display timings
+	 *
+	 * DC_DISP_REF_TO_SYNC:
+	 *  V_REF_TO_SYNC - 1
+	 *  H_REF_TO_SYNC - 0
+	 *
+	 * DC_DISP_SYNC_WIDTH:
+	 *  V_SYNC_WIDTH - 1
+	 *  H_SYNC_WIDTH - 72
+	 *
+	 * DC_DISP_BACK_PORCH:
+	 *  V_BACK_PORCH - 9
+	 *  H_BACK_PORCH - 72
+	 *
+	 * DC_DISP_ACTIVE:
+	 *  V_DISP_ACTIVE - 1280
+	 *  H_DISP_ACTIVE - 720
+	 *
+	 * DC_DISP_FRONT_PORCH:
+	 *  V_FRONT_PORCH - 10
+	 *  H_FRONT_PORCH - 136
+	 */
 	{DC_DISP_DISP_TIMING_OPTIONS, 0},
-	{DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
+	{DC_DISP_REF_TO_SYNC, 0x10000},
 	{DC_DISP_SYNC_WIDTH,  0x10048},
 	{DC_DISP_BACK_PORCH,  0x90048},
 	{DC_DISP_ACTIVE,      0x50002D0},
-	{DC_DISP_FRONT_PORCH, 0xA0088},   // Sources say that this should be above the DC_DISP_ACTIVE cmd.
+	{DC_DISP_FRONT_PORCH, 0xA0088},   // Sources say that this should happen before DC_DISP_ACTIVE cmd.
 	/* End of Display timings */
+
 	{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
 	{DC_COM_PIN_OUTPUT_ENABLE(1), 0},
 	{DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
@@ -477,10 +527,10 @@ static const cfg_op_t _display_dsi_timing_deinit_config[16] = {
 //DSI config (if ver == 0x10).
 static const cfg_op_t _display_deinit_config_jdi[22] = {
 	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
+	{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x2139},     // MIPI_DSI_DCS_LONG_WRITE: 33 bytes.
-	{DSI_WR_DATA, 0x191919D5},
+	{DSI_WR_DATA, 0x191919D5}, // Register: 0xD5.
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19191919},
@@ -491,21 +541,21 @@ static const cfg_op_t _display_deinit_config_jdi[22] = {
 	{DSI_WR_DATA, 0x19},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
-	{DSI_WR_DATA, 0x4F0F41B1}, // Set Power control.
+	{DSI_WR_DATA, 0x4F0F41B1}, // MIPI_DCS_PRIV_SET_POWER_CONTROL.
 	{DSI_WR_DATA, 0xF179A433},
 	{DSI_WR_DATA, 0x002D81},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
+	{DSI_WR_DATA, 0x000000B9}, // MIPI_DCS_PRIV_SET_EXTC. Disable.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST}
 };
 
 static const cfg_op_t _display_deinit_config_auo[37] = {
 	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
+	{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
-	{DSI_WR_DATA, 0x191919D5},
+	{DSI_WR_DATA, 0x191919D5}, // Register: 0xD5.
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19191919},
@@ -518,7 +568,7 @@ static const cfg_op_t _display_deinit_config_auo[37] = {
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
-	{DSI_WR_DATA, 0x191919D6},
+	{DSI_WR_DATA, 0x191919D6}, // Register: 0xD6.
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19191919},
@@ -531,13 +581,13 @@ static const cfg_op_t _display_deinit_config_auo[37] = {
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
-	{DSI_WR_DATA, 0x711148B1}, // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
+	{DSI_WR_DATA, 0x711148B1}, // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
-	// Set Power control. (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
+	// (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
 	{DSI_WR_DATA, 0x71143209},
-	{DSI_WR_DATA, 0x114D31},   // Set Power control. (Unknown).
+	{DSI_WR_DATA, 0x114D31},   // (Unknown).
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
 	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
+	{DSI_WR_DATA, 0x000000B9}, // MIPI_DCS_PRIV_SET_EXTC. Disable.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST}
 };
 

bdk/gfx/di.c

@@ -1,446 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <string.h>
-
-#include "di.h"
-#include <power/max77620.h>
-#include <power/max7762x.h>
-#include <soc/clock.h>
-#include <soc/gpio.h>
-#include <soc/i2c.h>
-#include <soc/pinmux.h>
-#include <soc/pmc.h>
-#include <soc/t210.h>
-#include <utils/util.h>
-
-#include "di.inl"
-
-extern volatile nyx_storage_t *nyx_str;
-
-static u32 _display_id = 0;
-
-void display_end();
-
-static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
-{
-	u32 end = get_tmr_us() + timeout;
-	while (get_tmr_us() < end && DSI(off) & mask)
-		;
-	usleep(5);
-}
-
-static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
-{
-	DSI(_DSIREG(DSI_WR_DATA)) = (param << 8) | cmd;
-	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-
-	if (wait)
-		usleep(wait);
-}
-
-void display_init()
-{
-	// Check if display is already initialized.
-	if (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) & 0x18000000)
-		display_end();
-
-	// Power on.
-	max77620_regulator_set_volt_and_flags(REGULATOR_LDO0, 1200000, MAX77620_POWER_MODE_NORMAL); // Configure to 1.2V.
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL);
-
-	// Enable Display Interface specific clocks.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000;  // Clear reset DSI, MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000;  // Set enable clock DSI, MIPI_CAL.
-
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000; // Set enable clock DISP1, HOST1X.
-
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000;    // Set enable clock UART_FST_MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
-
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000;    // Set enable clock DSIA_LP.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10;    // Set PLLP_OUT and div 6 (68MHz).
-
-	// Disable deep power down.
-	PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
-	PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
-
-	// Config LCD and Backlight pins.
-	PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE;     // PULL_DOWN
-	PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE;    // PULL_DOWN
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE;  // PULL_DOWN
-	PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE;    // PULL_DOWN
-
-	// Set Backlight +-5V pins mode and direction
-	gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO);
-	gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE);
-
-	// Enable Backlight power.
-	gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // Backlight +5V enable.
-	usleep(10000);
-	gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // Backlight -5V enable.
-	usleep(10000);
-
-	// Configure Backlight pins (PWM, EN, RST).
-	gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO);
-	gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
-	gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Enable Backlight EN.
-
-	// Power up supply regulator for display interface.
-	MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0;
-
-	// Set DISP1 clock source and parent clock.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT.
-	u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 96 MHz.
-	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;    // PLLD_SETUP.
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2D0AAA; // PLLD_ENABLE_CLK.
-
-	// Setup display communication interfaces.
-	exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94);
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config, 61);
-	usleep(10000);
-
-	// Enable Backlight Reset.
-	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH);
-	usleep(60000);
-
-	// Setups DSI packet configuration and request display id.
-	DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
-	_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 3, 0);
-	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
-
-	_display_dsi_send_cmd(MIPI_DSI_DCS_READ, MIPI_DCS_GET_DISPLAY_ID, 0);
-	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
-
-	DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
-	_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
-
-	usleep(5000);
-
-	// MIPI_DCS_GET_DISPLAY_ID reply is a long read, size 3 u32.
-	for (u32 i = 0; i < 3; i++)
-		_display_id = DSI(_DSIREG(DSI_RD_DATA)); // Skip ack and msg type info and get the payload (display id).
-
-	// Save raw Display ID to Nyx storage.
-	nyx_str->info.disp_id = _display_id;
-
-	// Decode Display ID.
-	_display_id = ((_display_id >> 8) & 0xFF00) | (_display_id & 0xFF);
-
-	if ((_display_id & 0xFF) == PANEL_JDI_XXX062M)
-		_display_id = PANEL_JDI_XXX062M;
-
-	// Initialize display panel.
-	switch (_display_id)
-	{
-	case PANEL_JDI_XXX062M:
-		exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43);
-		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
-		break;
-	case PANEL_INL_P062CCA_AZ1:
-	case PANEL_AUO_A062TAN01:
-		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x439;          // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9;     // Enable extension cmd. (Pass: FF 83 94).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x739;          // MIPI_DSI_DCS_LONG_WRITE: 7 bytes.
-		if (_display_id == PANEL_INL_P062CCA_AZ1)
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
-		else
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x143209;       // (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		break;
-	case PANEL_INL_P062CCA_AZ2:
-	case PANEL_AUO_A062TAN02:
-	default: // Allow spare part displays to work.
-		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 120000);
-		break;
-	}
-
-	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000);
-
-	// Configure PLLD for DISP1.
-	plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 460.8 MHz.
-	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN.
-
-	// Finalize DSI configuration.
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 21);
-	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; // PCD1 | div3.
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10);
-	usleep(10000);
-
-	// Calibrate display communication pads.
-	exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 6);
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config, 4);
-	exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 16);
-	usleep(10000);
-
-	// Enable video display controller.
-	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113);
-}
-
-void display_backlight_pwm_init()
-{
-	clock_enable_pwm();
-
-	PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; // Enable PWM and set it to 25KHz PFM.
-
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC) | 1; // PWM clock source.
-	gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
-}
-
-void display_backlight(bool enable)
-{
-	gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO.
-}
-
-void display_backlight_brightness(u32 brightness, u32 step_delay)
-{
-	u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF;
-	if (brightness == old_value)
-		return;
-
-	if (brightness > 255)
-		brightness = 255;
-
-	if (old_value < brightness)
-	{
-		for (u32 i = old_value; i < brightness + 1; i++)
-		{
-			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
-			usleep(step_delay);
-		}
-	}
-	else
-	{
-		for (u32 i = old_value; i > brightness; i--)
-		{
-			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
-			usleep(step_delay);
-		}
-	}
-	if (!brightness)
-		PWM(PWM_CONTROLLER_PWM_CSR_0) = 0;
-}
-
-void display_end()
-{
-	display_backlight_brightness(0, 1000);
-
-	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
-	DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
-
-	DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
-	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet.
-
-	// De-initialize video controller.
-	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17);
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16);
-	usleep(10000);
-
-	// De-initialize display panel.
-	switch (_display_id)
-	{
-	case PANEL_JDI_XXX062M:
-		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22);
-		break;
-	case PANEL_AUO_A062TAN01:
-		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_auo, 37);
-		break;
-	case PANEL_INL_P062CCA_AZ2:
-	case PANEL_AUO_A062TAN02:
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x439; // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9; // Enable extension cmd. (Pass: FF 83 94).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		// Set Power.
-		DSI(_DSIREG(DSI_WR_DATA)) = 0xB39; // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
-		if (_display_id == PANEL_INL_P062CCA_AZ2)
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
-		else
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
-		// Set Power control. (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x71143209;
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x114D31; // Set Power control. (Unknown).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		break;
-	case PANEL_INL_P062CCA_AZ1:
-	default:
-		break;
-	}
-
-	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_ENTER_SLEEP_MODE, 50000);
-
-	// Disable display and backlight pins.
-	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
-	usleep(10000);
-
-	gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable.
-	usleep(10000);
-
-	gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable.
-	usleep(10000);
-
-	// Disable Display Interface specific clocks.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000;  // Set reset clock DSI, MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000;  // Clear enable clock DSI, MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1X.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000; // Clear enable DISP1, HOST1X.
-
-	// Power down pads.
-	DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
-	DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
-
-	// Switch to automatic function mode.
-	gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
-
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC)| 1;
-}
-
-void display_color_screen(u32 color)
-{
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8);
-
-	// Configure display to show single color.
-	DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
-	DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
-	DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
-	DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
-	usleep(35000);
-
-	display_backlight(true);
-}
-
-u32 *display_init_framebuffer_pitch()
-{
-	// Sanitize framebuffer area.
-	memset((u32 *)IPL_FB_ADDRESS, 0, 0x3C0000);
-
-	// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32);
-	usleep(35000);
-
-	return (u32 *)IPL_FB_ADDRESS;
-}
-
-u32 *display_init_framebuffer_pitch_inv()
-{
-	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch_inv, 34);
-
-	usleep(35000);
-
-	return (u32 *)NYX_FB_ADDRESS;
-}
-
-u32 *display_init_framebuffer_block()
-{
-	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 34);
-
-	usleep(35000);
-
-	return (u32 *)NYX_FB_ADDRESS;
-}
-
-u32 *display_init_framebuffer_log()
-{
-	// This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_log, 20);
-
-	return (u32 *)LOG_FB_ADDRESS;
-}
-
-void display_activate_console()
-{
-	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
-	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD.
-	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-
-	for (u32 i = 0xFF80; i < 0x10000; i++)
-	{
-		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-		usleep(1000);
-	}
-
-	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-}
-
-void display_deactivate_console()
-{
-	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
-
-	for (u32 i = 0xFFFF; i > 0xFF7F; i--)
-	{
-		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-		usleep(500);
-	}
-
-	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
-	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; // Disable window DD.
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-}
-
-void display_init_cursor(void *crs_fb, u32 size)
-{
-	// Setup cursor.
-	DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10);
-	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) =
-		CURSOR_BLEND_R8G8B8A8 | CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF;
-
-	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) |= CURSOR_ENABLE;
-
-	// Arm and activate changes.
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
-}
-
-void display_set_pos_cursor(u32 x, u32 y)
-{
-	DISPLAY_A(_DIREG(DC_DISP_CURSOR_POSITION)) = x | (y << 16);
-
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
-}
-
-void display_deinit_cursor()
-{
-	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = 0;
-	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) &= ~CURSOR_ENABLE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
-}

bdk/ianos/ianos.c

@@ -21,6 +21,7 @@
 #include "elfload/elfload.h"
 #include <module.h>
 #include <mem/heap.h>
+#include <power/max7762x.h>
 #include <storage/nx_sd.h>
 #include <utils/types.h>
 
@@ -43,6 +44,10 @@ static void _ianos_call_ep(moduleEntrypoint_t entrypoint, void *moduleConfig)
 	bdkParameters->memset = (memset_t)&memset;
 	bdkParameters->sharedHeap = &_heap;
 
+	// Extra functions.
+	bdkParameters->extension_magic = IANOS_EXT0;
+	bdkParameters->reg_voltage_set = (reg_voltage_set_t)&max7762x_regulator_set_voltage;
+
 	entrypoint(moduleConfig, bdkParameters);
 }
 

bdk/input/als.c

@@ -17,102 +17,140 @@
  */
 
 #include "als.h"
-#include <power/max77620.h>
 #include <power/max7762x.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/pinmux.h>
 #include <utils/util.h>
 
-#define HOS_GAIN  BH1730_GAIN_64X
+#define BH1730_DEFAULT_GAIN        BH1730_GAIN_64X
-#define HOS_ITIME 38
+#define BH1730_DEFAULT_ICYCLE       38
 
-void set_als_cfg(als_table_t *als_val, u8 gain, u8 itime)
+#define BH1730_INTERNAL_CLOCK_NS   2800
+#define BH1730_ADC_CALC_DELAY_US   2000 /* BH1730_INTERNAL_CLOCK_MS * 714 */
+#define BH1730_ITIME_CYCLE_TO_US   2700 /* BH1730_INTERNAL_CLOCK_MS * 964 */
+
+#define BH1730_DEFAULT_ITIME_MS	   100
+
+#define BH1730_LUX_MULTIPLIER      3600
+#define BH1730_LUX_MULTIPLIER_AULA 1410
+
+#define BH1730_LUX_MAX            100000
+
+typedef struct _opt_win_cal_t
 {
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), gain);
+	u32 rc;
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - itime));
+	u32 cv;
+	u32 ci;
+} opt_win_cal_t;
 
-	als_val->gain = gain;
+// Nintendo Switch Icosa/Iowa Optical Window calibration.
-	als_val->itime = itime;
+const opt_win_cal_t opt_win_cal_default[] = {
+	{  500, 5002, 7502 },
+	{  754, 2250, 2000 },
+	{ 1029, 1999, 1667 },
+	{ 1373,  884,  583 },
+	{ 1879,  309,  165 }
+};
+
+// Nintendo Switch Aula Optical Window calibration.
+const opt_win_cal_t opt_win_cal_aula[] = {
+	{  231, 9697, 30300 },
+	{  993, 3333,  2778 },
+	{ 1478, 1621,  1053 },
+	{ 7500,   81,    10 }
+};
+
+const u32 als_gain_idx_tbl[4] = { 1, 2, 64, 128 };
+
+void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle)
+{
+	if (gain > BH1730_GAIN_128X)
+		gain = BH1730_GAIN_128X;
+
+	if (!cycle)
+		cycle = 1;
+	else if (cycle > 255)
+		cycle = 255;
+
+	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), gain);
+	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - cycle));
+
+	als_ctxt->gain = gain;
+	als_ctxt->cycle = cycle;
 }
 
-void get_als_lux(als_table_t *als_val)
+void get_als_lux(als_ctxt_t *als_ctxt)
 {
 	u32 data[2];
-	float pre_gain_lux;
+	u32 visible_light;
-	float visible_light;
+	u32 ir_light;
-	float ir_light;
+	u64 lux = 0;
-	float light_ratio;
+	u32 itime_us = BH1730_ITIME_CYCLE_TO_US * als_ctxt->cycle;
 
-	u8 adc_ready = 0;
+	// Get visible and ir light raw data. Mode is continuous so waiting for new values doesn't matter.
-	u8 retries = 100;
-
-	const float als_gain_idx_tbl[4] = { 1.0, 2.0, 64.0, 128.0 };
-	const float als_norm_res = 100.0;
-	const float als_multiplier = 3.6;
-	const float als_tint = 2.7;
-
-	// Wait for ADC to prepare new data.
-	while (!(adc_ready & BH1730_CTL_ADC_VALID) && retries)
-	{
-		retries--;
-		adc_ready = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_CONTROL_REG));
-	}
-
-	// Get visible and ir light raw data.
 	data[0] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0LOW_REG)) +
 		(i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0HIGH_REG)) << 8);
 	data[1] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1LOW_REG)) +
 		(i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1HIGH_REG)) << 8);
 
-	als_val->over_limit = data[0] > 65534 || data[1] > 65534;
+	visible_light = data[0];
-	als_val->vi_light = data[0];
+	ir_light = data[1];
-	als_val->ir_light = data[1];
 
-	if (!data[0] || !retries)
+	als_ctxt->over_limit = visible_light > 65534 || ir_light > 65534;
+	als_ctxt->vi_light = visible_light;
+	als_ctxt->ir_light = ir_light;
+
+	if (!visible_light)
 	{
-		als_val->lux = 0.0;
+		als_ctxt->lux = 0;
 
 		return;
 	}
 
-	visible_light = (float)data[0];
+	// Set calibration parameters.
-	ir_light = (float)data[1];
+	u32 lux_multiplier = BH1730_LUX_MULTIPLIER;
-	light_ratio = (float)data[1] / (float)data[0];
+	u32 opt_win_cal_count = ARRAY_SIZE(opt_win_cal_default);
+	const opt_win_cal_t *opt_win_cal = opt_win_cal_default;
 
-	// The following are specific to the light filter Switch uses.
+	// Apply optical window calibration coefficients.
-	if (light_ratio < 0.5)
+	for (u32 i = 0; i < opt_win_cal_count; i++)
-		pre_gain_lux = visible_light * 5.002 - ir_light * 7.502;
+	{
-	else if (light_ratio < 0.754)
+		if (1000 * ir_light / visible_light < opt_win_cal[i].rc)
-		pre_gain_lux = visible_light * 2.250 - ir_light * 2.000;
+		{
-	else if (light_ratio < 1.029)
+			lux = ((u64)opt_win_cal[i].cv * data[0]) - (opt_win_cal[i].ci * data[1]);
-		pre_gain_lux = visible_light * 1.999 - ir_light * 1.667;
+			break;
-	else if (light_ratio < 1.373)
+		}
-		pre_gain_lux = visible_light * 0.884 - ir_light * 0.583;
-	else if (light_ratio < 1.879)
-		pre_gain_lux = visible_light * 0.309 - ir_light * 0.165;
-	else pre_gain_lux = 0.0;
-
-	als_val->lux = (pre_gain_lux / als_gain_idx_tbl[als_val->gain]) * (als_norm_res / ((float)als_val->itime * als_tint)) * als_multiplier;
 	}
 
-u8 als_init(als_table_t *als_val)
+	lux *= BH1730_DEFAULT_ITIME_MS * lux_multiplier;
+	lux /= als_gain_idx_tbl[als_ctxt->gain] * itime_us;
+	lux /= 1000;
+
+	if (lux > BH1730_LUX_MAX)
+		lux = BH1730_LUX_MAX;
+
+	als_ctxt->lux = lux;
+}
+
+u8 als_power_on(als_ctxt_t *als_ctxt)
 {
+	// Enable power to ALS IC.
+	max7762x_regulator_set_voltage(REGULATOR_LDO6, 2900000);
+	max7762x_regulator_enable(REGULATOR_LDO6, true);
+
+	// Init I2C2.
 	pinmux_config_i2c(I2C_2);
 	clock_enable_i2c(I2C_2);
 	i2c_init(I2C_2);
 
-	max77620_regulator_set_volt_and_flags(REGULATOR_LDO6, 2900000, MAX77620_POWER_MODE_NORMAL);
+	// Initialize ALS.
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2, 0xD8 | MAX77620_LDO_CFG2_ADE_MASK);
-
 	u8 id = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(0x12));
 	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_SPEC(BH1730_SPECCMD_RESET), 0);
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), HOS_GAIN);
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - HOS_ITIME));
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_CONTROL_REG), BH1730_CTL_POWER_ON | BH1730_CTL_ADC_EN);
 
-	als_val->gain = HOS_GAIN;
+	set_als_cfg(als_ctxt, BH1730_DEFAULT_GAIN, BH1730_DEFAULT_ICYCLE);
-	als_val->itime = HOS_ITIME;
+
+	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_CONTROL_REG), BH1730_CTL_POWER_ON | BH1730_CTL_ADC_EN);
 
 	return id;
 }

bdk/input/als.h

@@ -45,21 +45,21 @@
 #define BH1730_DATA1LOW_REG  0x16
 #define BH1730_DATA1HIGH_REG 0x17
 
-#define BH1730_ADDR(reg) (BH1730_CMD_MAGIC | BH1730_CMD_SETADDR | reg)
+#define BH1730_ADDR(reg) (BH1730_CMD_MAGIC | BH1730_CMD_SETADDR | (reg))
-#define BH1730_SPEC(cmd) (BH1730_CMD_MAGIC | BH1730_CMD_SPECCMD | cmd)
+#define BH1730_SPEC(cmd) (BH1730_CMD_MAGIC | BH1730_CMD_SPECCMD | (cmd))
 
-typedef struct _als_table_t
+typedef struct _als_ctxt_t
 {
-	float lux;
+	u32  lux;
 	bool over_limit;
 	u32  vi_light;
 	u32  ir_light;
 	u8   gain;
-	u8 itime;
+	u8   cycle;
-} als_table_t;
+} als_ctxt_t;
 
-void set_als_cfg(als_table_t *als_val, u8 gain, u8 itime);
+void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle);
-void get_als_lux(als_table_t *als_val);
+void get_als_lux(als_ctxt_t *als_ctxt);
-u8 als_init(als_table_t *als_val);
+u8   als_power_on(als_ctxt_t *als_ctxt);
 
 #endif /* __ALS_H_ */

bdk/input/joycon.c

@@ -1,7 +1,7 @@
 /*
  * Joy-Con UART driver for Nintendo Switch
  *
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -24,6 +24,7 @@
 #include <power/regulator_5v.h>
 #include <soc/bpmp.h>
 #include <soc/clock.h>
+#include <soc/fuse.h>
 #include <soc/gpio.h>
 #include <soc/pinmux.h>
 #include <soc/uart.h>
@@ -38,6 +39,9 @@
 #define JC_WIRED_INIT_REPLY      0x94
 #define JC_INIT_HANDSHAKE        0xA5
 
+#define JC_HORI_INPUT_RPT_CMD    0x9A
+#define JC_HORI_INPUT_RPT        0x00
+
 #define JC_WIRED_CMD_MAC         0x01
 #define JC_WIRED_CMD_10          0x10
 
@@ -58,10 +62,14 @@
 #define JC_HID_SUBCMD_SND_RUMBLE 0xFF
 
 #define JC_BTN_MASK_L 0xFF2900 // 0xFFE900: with charge status.
-#define JC_BTN_MASK_R 0x76FF
+#define JC_BTN_MASK_R 0x0056FF
 
-#define JC_ID_L 1
+#define JC_ID_L     0x01
-#define JC_ID_R 2
+#define JC_ID_R     0x02
+#define JC_ID_HORI  0x20
+
+#define JC_CRC8_INIT    0x00
+#define JC_CRC8_POLY    0x8D
 
 enum
 {
@@ -79,25 +87,31 @@ static const u8 init_jc[] = {
 static const u8 init_handshake[] = {
 	0x19, 0x01, 0x03, 0x07, 0x00,      // Uart header.
 	JC_INIT_HANDSHAKE, 0x02,           // Wired cmd and wired subcmd.
-	0x01, 0x7E, 0x00, 0x00, 0x00       // Wired subcmd data.
+	0x01, 0x7E, 0x00, 0x00, 0x00       // Wired subcmd data and crc.
 };
 
 static const u8 init_get_info[]  = {
 	0x19, 0x01, 0x03, 0x07, 0x00,      // Uart header.
 	JC_WIRED_CMD, JC_WIRED_CMD_MAC,    // Wired cmd and subcmd.
-	0x00, 0x00, 0x00, 0x00, 0x24       // Wired subcmd data.
+	0x00, 0x00, 0x00, 0x00, 0x24       // Wired subcmd data and crc.
 };
 
-static const u8 init_finilize[]  = {
+static const u8 init_finalize[]  = {
 	0x19, 0x01, 0x03, 0x07, 0x00,      // Uart header.
 	JC_WIRED_CMD, JC_WIRED_CMD_10,     // Wired cmd and subcmd.
-	0x00, 0x00, 0x00, 0x00, 0x3D       // Wired subcmd data.
+	0x00, 0x00, 0x00, 0x00, 0x3D       // Wired subcmd data and crc.
 };
 
 static const u8 nx_pad_status[]  = {
 	0x19, 0x01, 0x03, 0x08, 0x00,      // Uart header.
 	JC_WIRED_HID, 0x00,                // Wired cmd and hid cmd.
-	0x01, 0x00, 0x00, 0x69, 0x2D, 0x1F // hid data.
+	0x01, 0x00, 0x00, 0x69, 0x2D, 0x1F // hid data and crc.
+};
+
+static const u8 hori_pad_status[] = {
+	0x19, 0x01, 0x03, 0x07, 0x00,      // Uart header.
+	JC_HORI_INPUT_RPT_CMD, 0x01,       // Hori cmd and hori subcmd.
+	0x00, 0x00, 0x00, 0x00, 0x48       // Hori cmd data and crc.
 };
 
 typedef struct _jc_uart_hdr_t
@@ -184,8 +198,8 @@ typedef struct _joycon_ctxt_t
 	u8 connected;
 } joycon_ctxt_t;
 
-static joycon_ctxt_t jc_l;
+static joycon_ctxt_t jc_l = {0};
-static joycon_ctxt_t jc_r;
+static joycon_ctxt_t jc_r = {0};
 
 static bool jc_init_done = false;
 static u32 hid_pkt_inc = 0;
@@ -194,33 +208,49 @@ static jc_gamepad_rpt_t jc_gamepad;
 
 void jc_power_supply(u8 uart, bool enable);
 
+static u8 jc_crc(u8 *data, u16 len)
+{
+	u8 crc = JC_CRC8_INIT;
+	u16 i, j;
+	for (i = 0; i < len; i++) {
+		crc ^= data[i];
+		for (j = 0; j < 8; j++) {
+			if ((crc & 0x80) != 0)
+				crc = (u8)((crc << 1) ^ JC_CRC8_POLY);
+			else
+				crc <<= 1;
+		}
+	}
+	return crc;
+}
+
 void joycon_send_raw(u8 uart_port, const u8 *buf, u16 size)
 {
 	uart_send(uart_port, buf, size);
 	uart_wait_idle(uart_port, UART_TX_IDLE);
 }
 
-static u16 jc_packet_add_uart_hdr(jc_wired_hdr_t *out, u8 wired_cmd, u8 *data, u16 size)
+static u16 jc_packet_add_uart_hdr(jc_wired_hdr_t *out, u8 wired_cmd, u8 *data, u16 size, bool crc)
 {
 	out->uart_hdr.magic[0] = 0x19;
 	out->uart_hdr.magic[1] = 0x01;
 	out->uart_hdr.magic[2] = 0x3;
 
-	out->uart_hdr.total_size_lsb = 7;
+	out->uart_hdr.total_size_lsb = sizeof(jc_wired_hdr_t) - sizeof(jc_uart_hdr_t);
 	out->uart_hdr.total_size_msb = 0;
 	out->cmd = wired_cmd;
 
 	if (data)
 		memcpy(out->data, data, size);
 
-	out->crc = 0; // wired crc8ccit can be skipped.
+	out->crc = crc ? jc_crc(&out->uart_hdr.total_size_msb, sizeof(out->uart_hdr.total_size_msb) + sizeof(out->cmd) + sizeof(out->data)) : 0;
 
 	return sizeof(jc_wired_hdr_t);
 }
 
-static u16 jc_hid_output_rpt_craft(jc_wired_hdr_t *rpt, u8 *payload, u16 size)
+static u16 jc_hid_output_rpt_craft(jc_wired_hdr_t *rpt, u8 *payload, u16 size, bool crc)
 {
-	u16 pkt_size = jc_packet_add_uart_hdr(rpt, JC_WIRED_HID, NULL, 0);
+	u16 pkt_size = jc_packet_add_uart_hdr(rpt, JC_WIRED_HID, NULL, 0, crc);
 	pkt_size += size;
 
 	rpt->uart_hdr.total_size_lsb += size;
@@ -233,12 +263,12 @@ static u16 jc_hid_output_rpt_craft(jc_wired_hdr_t *rpt, u8 *payload, u16 size)
 	return pkt_size;
 }
 
-void jc_send_hid_output_rpt(u8 uart, u8 *payload, u16 size)
+void jc_send_hid_output_rpt(u8 uart, u8 *payload, u16 size, bool crc)
 {
 	u8 rpt[0x50];
 	memset(rpt, 0, sizeof(rpt));
 
-	u32 rpt_size = jc_hid_output_rpt_craft((jc_wired_hdr_t *)rpt, payload, size);
+	u32 rpt_size = jc_hid_output_rpt_craft((jc_wired_hdr_t *)rpt, payload, size, crc);
 
 	joycon_send_raw(uart, rpt, rpt_size);
 }
@@ -274,18 +304,18 @@ void jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size)
 		hid_pkt->subcmd = JC_HID_SUBCMD_RUMBLE_CTL;
 		hid_pkt->subcmd_data[0] = 1;
 		if (send_r_rumble)
-			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10);
+			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10, false);
 		if (send_l_rumble)
-			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10);
+			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10, false);
 
 		// Send rumble.
 		hid_pkt->cmd = JC_HID_RUMBLE_RPT;
 		hid_pkt->pkt_id = jc_hid_pkt_id_incr();
 		memcpy(hid_pkt->rumble, rumble_init, sizeof(rumble_init));
 		if (send_r_rumble)
-			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 10);
+			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 10, false);
 		if (send_l_rumble)
-			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 10);
+			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 10, false);
 
 		msleep(15);
 
@@ -296,21 +326,21 @@ void jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size)
 		hid_pkt->subcmd_data[0] = 0;
 		memcpy(hid_pkt->rumble, rumble_neutral, sizeof(rumble_neutral));
 		if (send_r_rumble)
-			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10);
+			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10, false);
 		if (send_l_rumble)
-			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10);
+			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10, false);
 	}
 	else
 	{
+		bool crc_needed = (jc_l.uart == uart) ? (jc_l.type & JC_ID_HORI) : (jc_r.type & JC_ID_HORI);
+
 		hid_pkt->cmd = JC_HID_OUTPUT_RPT;
 		hid_pkt->pkt_id = jc_hid_pkt_id_incr();
 		hid_pkt->subcmd = subcmd;
 		if (data)
 			memcpy(hid_pkt->subcmd_data, data, size);
 
-		u8 pkt_size = sizeof(jc_hid_out_rpt_t) + size;
+		jc_send_hid_output_rpt(uart, (u8 *)hid_pkt, sizeof(jc_hid_out_rpt_t) + size, crc_needed);
-
-		jc_send_hid_output_rpt(uart, (u8 *)hid_pkt, pkt_size);
 	}
 }
 
@@ -332,6 +362,7 @@ static void jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size)
 
 	switch (hid_pkt->cmd)
 	{
+	case JC_HORI_INPUT_RPT:
 	case JC_HID_INPUT_RPT:
 		btn_tmp = hid_pkt->btn_right | hid_pkt->btn_shared << 8 | hid_pkt->btn_left << 16;
 
@@ -411,6 +442,7 @@ static void jc_uart_pkt_parse(joycon_ctxt_t *jc, const u8* packet, size_t size)
 	jc_wired_hdr_t *pkt = (jc_wired_hdr_t *)packet;
 	switch (pkt->cmd)
 	{
+	case JC_HORI_INPUT_RPT_CMD:
 	case JC_WIRED_HID:
 		jc_parse_wired_hid(jc, pkt->payload, (pkt->data[0] << 8) | pkt->data[1]);
 		break;
@@ -431,7 +463,7 @@ static void jc_rcv_pkt(joycon_ctxt_t *jc)
 
 	// Check if device stopped sending data.
 	u32 uart_irq = uart_get_IIR(jc->uart);
-	if ((uart_irq & 0x8) != 0x8)
+	if (uart_irq != UART_IIR_REDI)
 		return;
 
 	u32 len = uart_recv(jc->uart, (u8 *)jc->buf, 0x100);
@@ -472,11 +504,16 @@ static bool jc_send_init_rumble(joycon_ctxt_t *jc)
 }
 
 static void jc_req_nx_pad_status(joycon_ctxt_t *jc)
+{
+	bool is_nxpad = !(jc->type & JC_ID_HORI);
+
+	if (is_nxpad)
 	{
 		bool sent_rumble = jc_send_init_rumble(jc);
 
 		if (sent_rumble)
 			return;
+	}
 
 	if (jc->last_status_req_time > get_tmr_ms() || !jc->connected)
 		return;
@@ -487,7 +524,10 @@ static void jc_req_nx_pad_status(joycon_ctxt_t *jc)
 	else
 		gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
 
+	if (is_nxpad)
 		joycon_send_raw(jc->uart, nx_pad_status, sizeof(nx_pad_status));
+	else
+		joycon_send_raw(jc->uart, hori_pad_status, sizeof(hori_pad_status));
 
 	// Turn Joy-Con detect on.
 	if (jc->uart == UART_B)
@@ -523,6 +563,9 @@ jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos)
 	u8 retries;
 	jc_bt_conn_t *bt_conn;
 
+	if (!jc_init_done)
+		return NULL;
+
 	bt_conn = &jc_gamepad.bt_conn_l;
 	memset(bt_conn->host_mac, 0, 6);
 	memset(bt_conn->ltk, 0, 16);
@@ -651,24 +694,31 @@ retry:
 
 void jc_deinit()
 {
+	// Disable power.
+	jc_power_supply(UART_B, false);
+	jc_power_supply(UART_C, false);
+
+	// Turn off Joy-Con detect.
 	gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
 	gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
 
+	// Send sleep command.
 	u8 data = HCI_STATE_SLEEP;
 
-	if (jc_r.connected)
+	if (jc_r.connected && !(jc_r.type & JC_ID_HORI))
 	{
 		jc_send_hid_cmd(UART_B, JC_HID_SUBCMD_HCI_STATE, &data, 1);
 		jc_rcv_pkt(&jc_r);
 	}
-	if (jc_l.connected)
+	if (jc_l.connected && !(jc_l.type & JC_ID_HORI))
 	{
 		jc_send_hid_cmd(UART_C, JC_HID_SUBCMD_HCI_STATE, &data, 1);
 		jc_rcv_pkt(&jc_l);
 	}
 
-	jc_power_supply(UART_B, false);
+	// Disable UART B and C clocks.
-	jc_power_supply(UART_C, false);
+	clock_disable_uart(UART_B);
+	clock_disable_uart(UART_C);
 }
 
 static void jc_init_conn(joycon_ctxt_t *jc)
@@ -705,9 +755,12 @@ static void jc_init_conn(joycon_ctxt_t *jc)
 		msleep(5);
 		jc_rcv_pkt(jc);
 
-		joycon_send_raw(jc->uart, init_finilize, sizeof(init_finilize));
+		if (!(jc->type & JC_ID_HORI))
+		{
+			joycon_send_raw(jc->uart, init_finalize, sizeof(init_finalize));
 			msleep(5);
 			jc_rcv_pkt(jc);
+		}
 
 		// Turn Joy-Con detect on.
 		if (jc->uart == UART_B)
@@ -762,10 +815,10 @@ void jc_power_supply(u8 uart, bool enable)
 {
 	if (enable)
 	{
-		if (regulator_get_5v_dev_enabled(1 << uart))
+		if (regulator_5v_get_dev_enabled(1 << uart))
 			return;
 
-		regulator_enable_5v(1 << uart);
+		regulator_5v_enable(1 << uart);
 
 		if (jc_init_done)
 		{
@@ -795,10 +848,10 @@ void jc_power_supply(u8 uart, bool enable)
 	}
 	else
 	{
-		if (!regulator_get_5v_dev_enabled(1 << uart))
+		if (!regulator_5v_get_dev_enabled(1 << uart))
 			return;
 
-		regulator_disable_5v(1 << uart);
+		regulator_5v_disable(1 << uart);
 
 		if (uart == UART_C)
 			gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_LOW);
@@ -812,7 +865,10 @@ void jc_init_hw()
 	jc_l.uart = UART_C;
 	jc_r.uart = UART_B;
 
-#if (LV_LOG_PRINTF != 1)
+#if !defined(DEBUG_UART_PORT) || !(DEBUG_UART_PORT)
+	if (fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG)
+		return;
+
 	jc_power_supply(UART_C, true);
 	jc_power_supply(UART_B, true);
 
@@ -829,14 +885,14 @@ void jc_init_hw()
 	pinmux_config_uart(UART_C);
 
 	// Ease the stress to APB.
-	bpmp_clk_rate_set(BPMP_CLK_NORMAL);
+	bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
 
 	// Enable UART B and C clocks.
 	clock_enable_uart(UART_B);
 	clock_enable_uart(UART_C);
 
 	// Restore OC.
-	bpmp_clk_rate_set(BPMP_CLK_DEFAULT_BOOST);
+	bpmp_clk_rate_set(prev_fid);
 
 	// Turn Joy-Con detect on.
 	gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);

bdk/input/touch.c

@@ -23,7 +23,6 @@
 #include <soc/i2c.h>
 #include <soc/pinmux.h>
 #include <power/max7762x.h>
-#include <power/max77620.h>
 #include <soc/gpio.h>
 #include <soc/t210.h>
 #include <utils/btn.h>
@@ -34,6 +33,16 @@
 #include <gfx_utils.h>
 #define DPRINTF(...) gfx_printf(__VA_ARGS__)
 
+static touch_panel_info_t _panels[] =
+{
+	{  0,  1, 1, 1,  "NISSHA NFT-K12D" },
+	{  1,  0, 1, 1,  "GiS GGM6 B2X"    },
+	{  2,  0, 0, 0,  "NISSHA NBF-K9A"  },
+	{  3,  1, 0, 0,  "GiS 5.5\""       },
+	{  4,  0, 0, 1,  "Samsung BH2109"  },
+	{ -1,  1, 0, 1,  "GiS VA 6.2\""    }
+};
+
 static int touch_command(u8 cmd, u8 *buf, u8 size)
 {
 	int res = i2c_send_buf_small(I2C_3, STMFTS_I2C_ADDR, cmd, buf, size);
@@ -53,7 +62,7 @@ static int touch_read_reg(u8 *cmd, u32 csize, u8 *buf, u32 size)
 	return 0;
 }
 
-static int touch_wait_event(u8 event, u8 status, u32 timeout)
+static int touch_wait_event(u8 event, u8 status, u32 timeout, u8 *buf)
 {
 	u32 timer = get_tmr_ms() + timeout;
 	while (true)
@@ -61,7 +70,11 @@ static int touch_wait_event(u8 event, u8 status, u32 timeout)
 		u8 tmp[8] = {0};
 		i2c_recv_buf_small(tmp, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_READ_ONE_EVENT);
 		if (tmp[1] == event && tmp[2] == status)
+		{
+			if (buf)
+				memcpy(buf, &tmp[3], 5);
 			return 0;
+		}
 
 		if (get_tmr_ms() > timer)
 			return 1;
@@ -147,10 +160,10 @@ static void _touch_parse_event(touch_event *event)
 			event->type = STMFTS_EV_MULTI_TOUCH_LEAVE;
 	}
 
-	// gfx_con_setpos(&gfx_con, 0, 300);
+	// gfx_con_setpos(0, 300);
 	// DPRINTF("x = %d    \ny = %d    \nz = %d  \n", event->x, event->y, event->z);
-	// DPRINTF("0 = %02X\n1 = %02x\n2 = %02x\n3 = %02x\n", event->raw[0], event->raw[1], event->raw[2], event->raw[3]);
+	// DPRINTF("0 = %02X\n1 = %02X\n2 = %02X\n3 = %02X\n", event->raw[0], event->raw[1], event->raw[2], event->raw[3]);
-	// DPRINTF("4 = %02X\n5 = %02x\n6 = %02x\n7 = %02x\n", event->raw[4], event->raw[5], event->raw[6], event->raw[7]);
+	// DPRINTF("4 = %02X\n5 = %02X\n6 = %02X\n7 = %02X\n", event->raw[4], event->raw[5], event->raw[6], event->raw[7]);
 }
 
 void touch_poll(touch_event *event)
@@ -183,16 +196,45 @@ touch_info touch_get_info()
 	info.config_id = buf[4];
 	info.config_ver = buf[5];
 
-	//DPRINTF("ID: %04X, FW Ver: %d.%02d\nCfg ID: %02x, Cfg Ver: %d\n",
+	//DPRINTF("ID: %04X, FW Ver: %d.%02d\nCfg ID: %02X, Cfg Ver: %d\n",
 	//	info.chip_id, info.fw_ver >> 8, info.fw_ver & 0xFF, info.config_id, info.config_ver);
 
 	return info;
 }
 
+touch_panel_info_t *touch_get_panel_vendor()
+{
+	u8 buf[5] = {0};
+	u8 cmd = STMFTS_VENDOR_GPIO_STATE;
+	static touch_panel_info_t panel_info = { -2,  0, 0, 0,  ""};
+
+	if (touch_command(STMFTS_VENDOR, &cmd, 1))
+		return NULL;
+
+	if (touch_wait_event(STMFTS_EV_VENDOR, STMFTS_VENDOR_GPIO_STATE, 2000, buf))
+		return NULL;
+
+	for (u32 i = 0; i < ARRAY_SIZE(_panels); i++)
+	{
+		touch_panel_info_t *panel = &_panels[i];
+		if (buf[0] == panel->gpio0 && buf[1] == panel->gpio1 && buf[2] == panel->gpio2)
+			return panel;
+	}
+
+	// Touch panel not found, return current gpios.
+	panel_info.gpio0 = buf[0];
+	panel_info.gpio1 = buf[1];
+	panel_info.gpio2 = buf[2];
+
+	return &panel_info;
+}
+
 int touch_get_fw_info(touch_fw_info_t *fw)
 {
 	u8 buf[8] = {0};
 
+	memset(fw, 0, sizeof(touch_fw_info_t));
+
 	// Get fw address info.
 	u8 cmd[3] = { STMFTS_RW_FRAMEBUFFER_REG, 0, 0x60 };
 	int res = touch_read_reg(cmd, 3, buf, 3);
@@ -227,7 +269,7 @@ int touch_sys_reset()
 			continue;
 		}
 		msleep(10);
-		if (touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20))
+		if (touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20, NULL))
 			continue;
 		else
 			return 0;
@@ -301,9 +343,9 @@ int touch_get_fb_info(u8 *buf)
 
 int touch_sense_enable()
 {
-	// Enable auto tuning calibration and multi-touch sensing.
+	// Switch sense mode and enable multi-touch sensing.
-	u8 cmd = 1;
+	u8 cmd = STMFTS_FINGER_MODE;
-	if (touch_command(STMFTS_AUTO_CALIBRATION, &cmd, 1))
+	if (touch_command(STMFTS_SWITCH_SENSE_MODE, &cmd, 1))
 		return 0;
 
 	if (touch_command(STMFTS_MS_MT_SENSE_ON, NULL, 0))
@@ -329,19 +371,19 @@ int touch_execute_autotune()
 	// Apply Mutual Sense Compensation tuning.
 	if (touch_command(STMFTS_MS_CX_TUNING, NULL, 0))
 		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_MS_CX_TUNING_DONE, 2000))
+	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_MS_CX_TUNING_DONE, 2000, NULL))
 		return 0;
 
 	// Apply Self Sense Compensation tuning.
 	if (touch_command(STMFTS_SS_CX_TUNING, NULL, 0))
 		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_SS_CX_TUNING_DONE, 2000))
+	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_SS_CX_TUNING_DONE, 2000, NULL))
 		return 0;
 
 	// Save Compensation data to EEPROM.
 	if (touch_command(STMFTS_SAVE_CX_TUNING, NULL, 0))
 		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_WRITE_CX_TUNE_DONE, 2000))
+	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_WRITE_CX_TUNE_DONE, 2000, NULL))
 		return 0;
 
 	return touch_sense_enable();
@@ -358,12 +400,11 @@ static int touch_init()
 
 int touch_power_on()
 {
-	// Enables LDO6 for touchscreen VDD/AVDD supply
+	// Enable LDO6 for touchscreen AVDD supply.
-	max77620_regulator_set_volt_and_flags(REGULATOR_LDO6, 2900000, MAX77620_POWER_MODE_NORMAL);
+	max7762x_regulator_set_voltage(REGULATOR_LDO6, 2900000);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2,
+	max7762x_regulator_enable(REGULATOR_LDO6, true);
-		MAX77620_LDO_CFG2_ADE_ENABLE | (3 << 3) | (MAX77620_POWER_MODE_NORMAL << MAX77620_LDO_POWER_MODE_SHIFT));
 
-	// Configure touchscreen GPIO.
+	// Configure touchscreen VDD GPIO.
 	PINMUX_AUX(PINMUX_AUX_DAP4_SCLK) = PINMUX_PULL_DOWN | 1;
 	gpio_config(GPIO_PORT_J, GPIO_PIN_7, GPIO_MODE_GPIO);
 	gpio_output_enable(GPIO_PORT_J, GPIO_PIN_7, GPIO_OUTPUT_ENABLE);
@@ -377,7 +418,7 @@ int touch_power_on()
 	// Configure Touscreen and GCAsic shared GPIO.
 	PINMUX_AUX(PINMUX_AUX_CAM_I2C_SDA) = PINMUX_LPDR | PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 2;
 	PINMUX_AUX(PINMUX_AUX_CAM_I2C_SCL) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_TRISTATE | PINMUX_PULL_DOWN | 2;
-	gpio_config(GPIO_PORT_S, GPIO_PIN_3, GPIO_MODE_GPIO);
+	gpio_config(GPIO_PORT_S, GPIO_PIN_3, GPIO_MODE_GPIO); // GC detect.
 
 	// Initialize I2C3.
 	pinmux_config_i2c(I2C_3);
@@ -385,7 +426,7 @@ int touch_power_on()
 	i2c_init(I2C_3);
 
 	// Wait for the touchscreen module to get ready.
-	touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20);
+	touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20, NULL);
 
 	// Check for forced boot time calibration.
 	if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN))
@@ -414,9 +455,7 @@ void touch_power_off()
 	gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_LOW);
 
 	// Disables LDO6 for touchscreen VDD, AVDD supply
-	max77620_regulator_enable(REGULATOR_LDO6, 0);
+	max7762x_regulator_enable(REGULATOR_LDO6, false);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2,
-		MAX77620_LDO_CFG2_ADE_ENABLE | (2 << 3) | (MAX77620_POWER_MODE_NORMAL << MAX77620_LDO_POWER_MODE_SHIFT));
 
 	clock_disable_i2c(I2C_3);
 }

bdk/input/touch.h

@@ -47,19 +47,27 @@
 #define STMFTS_ITO_CHECK               0xA7
 #define STMFTS_RELEASEINFO             0xAA
 #define STMFTS_WRITE_REG               0xB6
-#define STMFTS_AUTO_CALIBRATION        0xC3
+#define STMFTS_SWITCH_SENSE_MODE       0xC3
 #define STMFTS_NOISE_WRITE             0xC7
 #define STMFTS_NOISE_READ              0xC8
 #define STMFTS_RW_FRAMEBUFFER_REG      0xD0
 #define STMFTS_SAVE_CX_TUNING          0xFC
 
-#define STMFTS_UNK0 0xB8 //Request compensation
+#define STMFTS_DETECTION_CONFIG        0xB0
-#define STMFTS_UNK1 0xCF
+#define STMFTS_REQU_COMP_DATA          0xB8
-#define STMFTS_UNK2 0xF7
+#define STMFTS_VENDOR                  0xCF
-#define STMFTS_UNK3 0xFA
+#define STMFTS_FLASH_UNLOCK            0xF7
-#define STMFTS_UNK4 0xF9
+#define STMFTS_FLASH_WRITE_64K         0xF8
+#define STMFTS_FLASH_STATUS            0xF9
+#define STMFTS_FLASH_OP                0xFA
 #define STMFTS_UNK5 0x62
 
+/* cmd parameters */
+#define STMFTS_VENDOR_GPIO_STATE       0x01
+#define STMFTS_VENDOR_SENSE_MODE       0x02
+#define STMFTS_STYLUS_MODE             0x00
+#define STMFTS_FINGER_MODE             0x01
+#define STMFTS_HOVER_MODE              0x02
 
 /* events */
 #define STMFTS_EV_NO_EVENT             0x00
@@ -74,6 +82,7 @@
 #define STMFTS_EV_ERROR                0x0f
 #define STMFTS_EV_NOISE_READ           0x17
 #define STMFTS_EV_NOISE_WRITE          0x18
+#define STMFTS_EV_VENDOR               0x20
 
 #define STMFTS_EV_CONTROLLER_READY     0x10
 #define STMFTS_EV_STATUS               0x16
@@ -131,6 +140,15 @@ typedef struct _touch_event {
 	bool touch;
 } touch_event;
 
+typedef struct _touch_panel_info_t
+{
+	u8 idx;
+	u8 gpio0;
+	u8 gpio1;
+	u8 gpio2;
+	char *vendor;
+} touch_panel_info_t;
+
 typedef struct _touch_info {
 	u16 chip_id;
 	u16 fw_ver;
@@ -146,6 +164,7 @@ typedef struct _touch_fw_info_t {
 
 void touch_poll(touch_event *event);
 touch_event touch_poll_wait();
+touch_panel_info_t *touch_get_panel_vendor();
 int touch_get_fw_info(touch_fw_info_t *fw);
 touch_info touch_get_info();
 int touch_panel_ito_test(u8 *err);

bdk/libs/compr/lz.c

@@ -125,7 +125,7 @@ static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf )
 *  insize  - Number of input bytes.
 *************************************************************************/
 
-void LZ_Uncompress( const unsigned char *in, unsigned char *out,
+unsigned int LZ_Uncompress( const unsigned char *in, unsigned char *out,
     unsigned int insize )
 {
     unsigned char marker, symbol;
@@ -134,7 +134,7 @@ void LZ_Uncompress( const unsigned char *in, unsigned char *out,
     /* Do we have anything to uncompress? */
     if( insize < 1 )
     {
-        return;
+        return 0;
     }
 
     /* Get marker symbol from input stream */
@@ -176,4 +176,6 @@ void LZ_Uncompress( const unsigned char *in, unsigned char *out,
         }
     }
     while( inpos < insize );
+
+    return outpos;
 }

bdk/libs/compr/lz.h

@@ -41,7 +41,7 @@ extern "C" {
 * Function prototypes
 *************************************************************************/
 
-void LZ_Uncompress( const unsigned char *in, unsigned char *out,
+unsigned int LZ_Uncompress( const unsigned char *in, unsigned char *out,
                     unsigned int insize );
 
 

bdk/libs/compr/lz4.h

@@ -0,0 +1,569 @@
+/*
+ *  LZ4 - Fast LZ compression algorithm
+ *  Header File
+ *  Copyright (C) 2011-2017, Yann Collet.
+
+   BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+
+       * Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above
+   copyright notice, this list of conditions and the following disclaimer
+   in the documentation and/or other materials provided with the
+   distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+   You can contact the author at :
+    - LZ4 homepage : http://www.lz4.org
+    - LZ4 source repository : https://github.com/lz4/lz4
+*/
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+#ifndef LZ4_H_2983827168210
+#define LZ4_H_2983827168210
+
+/* --- Dependency --- */
+#include <stddef.h>   /* size_t */
+
+
+/**
+  Introduction
+
+  LZ4 is lossless compression algorithm, providing compression speed at 400 MB/s per core,
+  scalable with multi-cores CPU. It features an extremely fast decoder, with speed in
+  multiple GB/s per core, typically reaching RAM speed limits on multi-core systems.
+
+  The LZ4 compression library provides in-memory compression and decompression functions.
+  Compression can be done in:
+    - a single step (described as Simple Functions)
+    - a single step, reusing a context (described in Advanced Functions)
+    - unbounded multiple steps (described as Streaming compression)
+
+  lz4.h provides block compression functions. It gives full buffer control to user.
+  Decompressing an lz4-compressed block also requires metadata (such as compressed size).
+  Each application is free to encode such metadata in whichever way it wants.
+
+  An additional format, called LZ4 frame specification (doc/lz4_Frame_format.md),
+  take care of encoding standard metadata alongside LZ4-compressed blocks.
+  If your application requires interoperability, it's recommended to use it.
+  A library is provided to take care of it, see lz4frame.h.
+*/
+
+/*^***************************************************************
+*  Export parameters
+*****************************************************************/
+/*
+*  LZ4_DLL_EXPORT :
+*  Enable exporting of functions when building a Windows DLL
+*  LZ4LIB_VISIBILITY :
+*  Control library symbols visibility.
+*/
+#ifndef LZ4LIB_VISIBILITY
+#  if defined(__GNUC__) && (__GNUC__ >= 4)
+#    define LZ4LIB_VISIBILITY __attribute__ ((visibility ("default")))
+#  else
+#    define LZ4LIB_VISIBILITY
+#  endif
+#endif
+#if defined(LZ4_DLL_EXPORT) && (LZ4_DLL_EXPORT==1)
+#  define LZ4LIB_API __declspec(dllexport) LZ4LIB_VISIBILITY
+#elif defined(LZ4_DLL_IMPORT) && (LZ4_DLL_IMPORT==1)
+#  define LZ4LIB_API __declspec(dllimport) LZ4LIB_VISIBILITY /* It isn't required but allows to generate better code, saving a function pointer load from the IAT and an indirect jump.*/
+#else
+#  define LZ4LIB_API LZ4LIB_VISIBILITY
+#endif
+
+/*------   Version   ------*/
+#define LZ4_VERSION_MAJOR    1    /* for breaking interface changes  */
+#define LZ4_VERSION_MINOR    8    /* for new (non-breaking) interface capabilities */
+#define LZ4_VERSION_RELEASE  2    /* for tweaks, bug-fixes, or development */
+
+#define LZ4_VERSION_NUMBER (LZ4_VERSION_MAJOR *100*100 + LZ4_VERSION_MINOR *100 + LZ4_VERSION_RELEASE)
+
+#define LZ4_LIB_VERSION LZ4_VERSION_MAJOR.LZ4_VERSION_MINOR.LZ4_VERSION_RELEASE
+#define LZ4_QUOTE(str) #str
+#define LZ4_EXPAND_AND_QUOTE(str) LZ4_QUOTE(str)
+#define LZ4_VERSION_STRING LZ4_EXPAND_AND_QUOTE(LZ4_LIB_VERSION)
+
+LZ4LIB_API int LZ4_versionNumber (void);  /**< library version number; useful to check dll version */
+LZ4LIB_API const char* LZ4_versionString (void);   /**< library version string; unseful to check dll version */
+
+
+/*-************************************
+*  Tuning parameter
+**************************************/
+/*!
+ * LZ4_MEMORY_USAGE :
+ * Memory usage formula : N->2^N Bytes (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB; etc.)
+ * Increasing memory usage improves compression ratio
+ * Reduced memory usage may improve speed, thanks to cache effect
+ * Default value is 14, for 16KB, which nicely fits into Intel x86 L1 cache
+ */
+#ifndef LZ4_MEMORY_USAGE
+# define LZ4_MEMORY_USAGE 14
+#endif
+
+/*-************************************
+*  Simple Functions
+**************************************/
+/*! LZ4_compress_default() :
+    Compresses 'srcSize' bytes from buffer 'src'
+    into already allocated 'dst' buffer of size 'dstCapacity'.
+    Compression is guaranteed to succeed if 'dstCapacity' >= LZ4_compressBound(srcSize).
+    It also runs faster, so it's a recommended setting.
+    If the function cannot compress 'src' into a more limited 'dst' budget,
+    compression stops *immediately*, and the function result is zero.
+    Note : as a consequence, 'dst' content is not valid.
+    Note 2 : This function is protected against buffer overflow scenarios (never writes outside 'dst' buffer, nor read outside 'source' buffer).
+        srcSize : max supported value is LZ4_MAX_INPUT_SIZE.
+        dstCapacity : size of buffer 'dst' (which must be already allocated)
+        return  : the number of bytes written into buffer 'dst' (necessarily <= dstCapacity)
+                  or 0 if compression fails */
+LZ4LIB_API int LZ4_compress_default(const char* src, char* dst, int srcSize, int dstCapacity);
+
+/*! LZ4_decompress_safe() :
+    compressedSize : is the exact complete size of the compressed block.
+    dstCapacity : is the size of destination buffer, which must be already allocated.
+    return : the number of bytes decompressed into destination buffer (necessarily <= dstCapacity)
+             If destination buffer is not large enough, decoding will stop and output an error code (negative value).
+             If the source stream is detected malformed, the function will stop decoding and return a negative result.
+             This function is protected against malicious data packets.
+*/
+LZ4LIB_API int LZ4_decompress_safe (const char* src, char* dst, int compressedSize, int dstCapacity);
+
+
+/*-************************************
+*  Advanced Functions
+**************************************/
+#define LZ4_MAX_INPUT_SIZE        0x7E000000   /* 2 113 929 216 bytes */
+#define LZ4_COMPRESSBOUND(isize)  ((unsigned)(isize) > (unsigned)LZ4_MAX_INPUT_SIZE ? 0 : (isize) + ((isize)/255) + 16)
+
+/*!
+LZ4_compressBound() :
+    Provides the maximum size that LZ4 compression may output in a "worst case" scenario (input data not compressible)
+    This function is primarily useful for memory allocation purposes (destination buffer size).
+    Macro LZ4_COMPRESSBOUND() is also provided for compilation-time evaluation (stack memory allocation for example).
+    Note that LZ4_compress_default() compresses faster when dstCapacity is >= LZ4_compressBound(srcSize)
+        inputSize  : max supported value is LZ4_MAX_INPUT_SIZE
+        return : maximum output size in a "worst case" scenario
+              or 0, if input size is incorrect (too large or negative)
+*/
+LZ4LIB_API int LZ4_compressBound(int inputSize);
+
+/*!
+LZ4_compress_fast() :
+    Same as LZ4_compress_default(), but allows selection of "acceleration" factor.
+    The larger the acceleration value, the faster the algorithm, but also the lesser the compression.
+    It's a trade-off. It can be fine tuned, with each successive value providing roughly +~3% to speed.
+    An acceleration value of "1" is the same as regular LZ4_compress_default()
+    Values <= 0 will be replaced by ACCELERATION_DEFAULT (currently == 1, see lz4.c).
+*/
+LZ4LIB_API int LZ4_compress_fast (const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+
+/*!
+LZ4_compress_fast_extState() :
+    Same compression function, just using an externally allocated memory space to store compression state.
+    Use LZ4_sizeofState() to know how much memory must be allocated,
+    and allocate it on 8-bytes boundaries (using malloc() typically).
+    Then, provide it as 'void* state' to compression function.
+*/
+LZ4LIB_API int LZ4_sizeofState(void);
+LZ4LIB_API int LZ4_compress_fast_extState (void* state, const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+
+/*!
+LZ4_compress_destSize() :
+    Reverse the logic : compresses as much data as possible from 'src' buffer
+    into already allocated buffer 'dst' of size 'targetDestSize'.
+    This function either compresses the entire 'src' content into 'dst' if it's large enough,
+    or fill 'dst' buffer completely with as much data as possible from 'src'.
+        *srcSizePtr : will be modified to indicate how many bytes where read from 'src' to fill 'dst'.
+                      New value is necessarily <= old value.
+        return : Nb bytes written into 'dst' (necessarily <= targetDestSize)
+                 or 0 if compression fails
+*/
+LZ4LIB_API int LZ4_compress_destSize (const char* src, char* dst, int* srcSizePtr, int targetDstSize);
+
+
+/*!
+LZ4_decompress_fast() : **unsafe!**
+This function is a bit faster than LZ4_decompress_safe(),
+but doesn't provide any security guarantee.
+    originalSize : is the uncompressed size to regenerate
+                   Destination buffer must be already allocated, and its size must be >= 'originalSize' bytes.
+    return : number of bytes read from source buffer (== compressed size).
+             If the source stream is detected malformed, the function stops decoding and return a negative result.
+    note : This function respects memory boundaries for *properly formed* compressed data.
+           However, it does not provide any protection against malicious input.
+           It also doesn't know 'src' size, and implies it's >= compressed size.
+           Use this function in trusted environment **only**.
+*/
+LZ4LIB_API int LZ4_decompress_fast (const char* src, char* dst, int originalSize);
+
+/*!
+LZ4_decompress_safe_partial() :
+    This function decompress a compressed block of size 'srcSize' at position 'src'
+    into destination buffer 'dst' of size 'dstCapacity'.
+    The function will decompress a minimum of 'targetOutputSize' bytes, and stop after that.
+    However, it's not accurate, and may write more than 'targetOutputSize' (but always <= dstCapacity).
+   @return : the number of bytes decoded in the destination buffer (necessarily <= dstCapacity)
+        Note : this number can also be < targetOutputSize, if compressed block contains less data.
+            Therefore, always control how many bytes were decoded.
+            If source stream is detected malformed, function returns a negative result.
+            This function is protected against malicious data packets.
+*/
+LZ4LIB_API int LZ4_decompress_safe_partial (const char* src, char* dst, int srcSize, int targetOutputSize, int dstCapacity);
+
+
+/*-*********************************************
+*  Streaming Compression Functions
+***********************************************/
+typedef union LZ4_stream_u LZ4_stream_t;  /* incomplete type (defined later) */
+
+/*! LZ4_createStream() and LZ4_freeStream() :
+ *  LZ4_createStream() will allocate and initialize an `LZ4_stream_t` structure.
+ *  LZ4_freeStream() releases its memory.
+ */
+LZ4LIB_API LZ4_stream_t* LZ4_createStream(void);
+LZ4LIB_API int           LZ4_freeStream (LZ4_stream_t* streamPtr);
+
+/*! LZ4_resetStream() :
+ *  An LZ4_stream_t structure can be allocated once and re-used multiple times.
+ *  Use this function to start compressing a new stream.
+ */
+LZ4LIB_API void LZ4_resetStream (LZ4_stream_t* streamPtr);
+
+/*! LZ4_loadDict() :
+ *  Use this function to load a static dictionary into LZ4_stream_t.
+ *  Any previous data will be forgotten, only 'dictionary' will remain in memory.
+ *  Loading a size of 0 is allowed, and is the same as reset.
+ * @return : dictionary size, in bytes (necessarily <= 64 KB)
+ */
+LZ4LIB_API int LZ4_loadDict (LZ4_stream_t* streamPtr, const char* dictionary, int dictSize);
+
+/*! LZ4_compress_fast_continue() :
+ *  Compress 'src' content using data from previously compressed blocks, for better compression ratio.
+ *  'dst' buffer must be already allocated.
+ *  If dstCapacity >= LZ4_compressBound(srcSize), compression is guaranteed to succeed, and runs faster.
+ *
+ *  Important : The previous 64KB of compressed data is assumed to remain present and unmodified in memory!
+ *
+ *  Special 1 : When input is a double-buffer, they can have any size, including < 64 KB.
+ *              Make sure that buffers are separated by at least one byte.
+ *              This way, each block only depends on previous block.
+ *  Special 2 : If input buffer is a ring-buffer, it can have any size, including < 64 KB.
+ *
+ * @return : size of compressed block
+ *           or 0 if there is an error (typically, cannot fit into 'dst').
+ *  After an error, the stream status is invalid, it can only be reset or freed.
+ */
+LZ4LIB_API int LZ4_compress_fast_continue (LZ4_stream_t* streamPtr, const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+/*! LZ4_saveDict() :
+ *  If last 64KB data cannot be guaranteed to remain available at its current memory location,
+ *  save it into a safer place (char* safeBuffer).
+ *  This is schematically equivalent to a memcpy() followed by LZ4_loadDict(),
+ *  but is much faster, because LZ4_saveDict() doesn't need to rebuild tables.
+ * @return : saved dictionary size in bytes (necessarily <= maxDictSize), or 0 if error.
+ */
+LZ4LIB_API int LZ4_saveDict (LZ4_stream_t* streamPtr, char* safeBuffer, int maxDictSize);
+
+
+/*-**********************************************
+*  Streaming Decompression Functions
+*  Bufferless synchronous API
+************************************************/
+typedef union LZ4_streamDecode_u LZ4_streamDecode_t;   /* incomplete type (defined later) */
+
+/*! LZ4_createStreamDecode() and LZ4_freeStreamDecode() :
+ *  creation / destruction of streaming decompression tracking structure.
+ *  A tracking structure can be re-used multiple times sequentially. */
+LZ4LIB_API LZ4_streamDecode_t* LZ4_createStreamDecode(void);
+LZ4LIB_API int                 LZ4_freeStreamDecode (LZ4_streamDecode_t* LZ4_stream);
+
+/*! LZ4_setStreamDecode() :
+ *  An LZ4_streamDecode_t structure can be allocated once and re-used multiple times.
+ *  Use this function to start decompression of a new stream of blocks.
+ *  A dictionary can optionnally be set. Use NULL or size 0 for a reset order.
+ * @return : 1 if OK, 0 if error
+ */
+LZ4LIB_API int LZ4_setStreamDecode (LZ4_streamDecode_t* LZ4_streamDecode, const char* dictionary, int dictSize);
+
+/*! LZ4_decompress_*_continue() :
+ *  These decoding functions allow decompression of consecutive blocks in "streaming" mode.
+ *  A block is an unsplittable entity, it must be presented entirely to a decompression function.
+ *  Decompression functions only accept one block at a time.
+ *  The last 64KB of previously decoded data *must* remain available and unmodified at the memory position where they were decoded.
+ *  If less than 64KB of data has been decoded all the data must be present.
+ *
+ *  Special : if application sets a ring buffer for decompression, it must respect one of the following conditions :
+ *  - Exactly same size as encoding buffer, with same update rule (block boundaries at same positions)
+ *    In which case, the decoding & encoding ring buffer can have any size, including very small ones ( < 64 KB).
+ *  - Larger than encoding buffer, by a minimum of maxBlockSize more bytes.
+ *    maxBlockSize is implementation dependent. It's the maximum size of any single block.
+ *    In which case, encoding and decoding buffers do not need to be synchronized,
+ *    and encoding ring buffer can have any size, including small ones ( < 64 KB).
+ *  - _At least_ 64 KB + 8 bytes + maxBlockSize.
+ *    In which case, encoding and decoding buffers do not need to be synchronized,
+ *    and encoding ring buffer can have any size, including larger than decoding buffer.
+ *  Whenever these conditions are not possible, save the last 64KB of decoded data into a safe buffer,
+ *  and indicate where it is saved using LZ4_setStreamDecode() before decompressing next block.
+*/
+LZ4LIB_API int LZ4_decompress_safe_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* src, char* dst, int srcSize, int dstCapacity);
+LZ4LIB_API int LZ4_decompress_fast_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* src, char* dst, int originalSize);
+
+
+/*! LZ4_decompress_*_usingDict() :
+ *  These decoding functions work the same as
+ *  a combination of LZ4_setStreamDecode() followed by LZ4_decompress_*_continue()
+ *  They are stand-alone, and don't need an LZ4_streamDecode_t structure.
+ */
+LZ4LIB_API int LZ4_decompress_safe_usingDict (const char* src, char* dst, int srcSize, int dstCapcity, const char* dictStart, int dictSize);
+LZ4LIB_API int LZ4_decompress_fast_usingDict (const char* src, char* dst, int originalSize, const char* dictStart, int dictSize);
+
+
+/*^**********************************************
+ * !!!!!!   STATIC LINKING ONLY   !!!!!!
+ ***********************************************/
+
+/*-************************************
+ *  Unstable declarations
+ **************************************
+ * Declarations in this section should be considered unstable.
+ * Use at your own peril, etc., etc.
+ * They may be removed in the future.
+ * Their signatures may change.
+ **************************************/
+
+#ifdef LZ4_STATIC_LINKING_ONLY
+
+/*! LZ4_resetStream_fast() :
+ *  When an LZ4_stream_t is known to be in a internally coherent state,
+ *  it can often be prepared for a new compression with almost no work, only
+ *  sometimes falling back to the full, expensive reset that is always required
+ *  when the stream is in an indeterminate state (i.e., the reset performed by
+ *  LZ4_resetStream()).
+ *
+ *  LZ4_streams are guaranteed to be in a valid state when:
+ *  - returned from LZ4_createStream()
+ *  - reset by LZ4_resetStream()
+ *  - memset(stream, 0, sizeof(LZ4_stream_t))
+ *  - the stream was in a valid state and was reset by LZ4_resetStream_fast()
+ *  - the stream was in a valid state and was then used in any compression call
+ *    that returned success
+ *  - the stream was in an indeterminate state and was used in a compression
+ *    call that fully reset the state (LZ4_compress_fast_extState()) and that
+ *    returned success
+ */
+LZ4LIB_API void LZ4_resetStream_fast (LZ4_stream_t* streamPtr);
+
+/*! LZ4_compress_fast_extState_fastReset() :
+ *  A variant of LZ4_compress_fast_extState().
+ *
+ *  Using this variant avoids an expensive initialization step. It is only safe
+ *  to call if the state buffer is known to be correctly initialized already
+ *  (see above comment on LZ4_resetStream_fast() for a definition of "correctly
+ *  initialized"). From a high level, the difference is that this function
+ *  initializes the provided state with a call to LZ4_resetStream_fast() while
+ *  LZ4_compress_fast_extState() starts with a call to LZ4_resetStream().
+ */
+LZ4LIB_API int LZ4_compress_fast_extState_fastReset (void* state, const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+/*! LZ4_attach_dictionary() :
+ *  This is an experimental API that allows for the efficient use of a
+ *  static dictionary many times.
+ *
+ *  Rather than re-loading the dictionary buffer into a working context before
+ *  each compression, or copying a pre-loaded dictionary's LZ4_stream_t into a
+ *  working LZ4_stream_t, this function introduces a no-copy setup mechanism,
+ *  in which the working stream references the dictionary stream in-place.
+ *
+ *  Several assumptions are made about the state of the dictionary stream.
+ *  Currently, only streams which have been prepared by LZ4_loadDict() should
+ *  be expected to work.
+ *
+ *  Alternatively, the provided dictionary stream pointer may be NULL, in which
+ *  case any existing dictionary stream is unset.
+ *
+ *  If a dictionary is provided, it replaces any pre-existing stream history.
+ *  The dictionary contents are the only history that can be referenced and
+ *  logically immediately precede the data compressed in the first subsequent
+ *  compression call.
+ *
+ *  The dictionary will only remain attached to the working stream through the
+ *  first compression call, at the end of which it is cleared. The dictionary
+ *  stream (and source buffer) must remain in-place / accessible / unchanged
+ *  through the completion of the first compression call on the stream.
+ */
+LZ4LIB_API void LZ4_attach_dictionary(LZ4_stream_t *working_stream, const LZ4_stream_t *dictionary_stream);
+
+#endif
+
+/*-************************************
+ *  Private definitions
+ **************************************
+ * Do not use these definitions.
+ * They are exposed to allow static allocation of `LZ4_stream_t` and `LZ4_streamDecode_t`.
+ * Using these definitions will expose code to API and/or ABI break in future versions of the library.
+ **************************************/
+#define LZ4_HASHLOG   (LZ4_MEMORY_USAGE-2)
+#define LZ4_HASHTABLESIZE (1 << LZ4_MEMORY_USAGE)
+#define LZ4_HASH_SIZE_U32 (1 << LZ4_HASHLOG)       /* required as macro for static allocation */
+
+#if defined(__cplusplus) || (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */)
+#include <stdint.h>
+
+typedef struct LZ4_stream_t_internal LZ4_stream_t_internal;
+struct LZ4_stream_t_internal {
+    uint32_t hashTable[LZ4_HASH_SIZE_U32];
+    uint32_t currentOffset;
+    uint16_t initCheck;
+    uint16_t tableType;
+    const uint8_t* dictionary;
+    const LZ4_stream_t_internal* dictCtx;
+    uint32_t dictSize;
+};
+
+typedef struct {
+    const uint8_t* externalDict;
+    size_t extDictSize;
+    const uint8_t* prefixEnd;
+    size_t prefixSize;
+} LZ4_streamDecode_t_internal;
+
+#else
+
+typedef struct LZ4_stream_t_internal LZ4_stream_t_internal;
+struct LZ4_stream_t_internal {
+    unsigned int hashTable[LZ4_HASH_SIZE_U32];
+    unsigned int currentOffset;
+    unsigned short initCheck;
+    unsigned short tableType;
+    const unsigned char* dictionary;
+    const LZ4_stream_t_internal* dictCtx;
+    unsigned int dictSize;
+};
+
+typedef struct {
+    const unsigned char* externalDict;
+    size_t extDictSize;
+    const unsigned char* prefixEnd;
+    size_t prefixSize;
+} LZ4_streamDecode_t_internal;
+
+#endif
+
+/*!
+ * LZ4_stream_t :
+ * information structure to track an LZ4 stream.
+ * init this structure before first use.
+ * note : only use in association with static linking !
+ *        this definition is not API/ABI safe,
+ *        it may change in a future version !
+ */
+#define LZ4_STREAMSIZE_U64 ((1 << (LZ4_MEMORY_USAGE-3)) + 4)
+#define LZ4_STREAMSIZE     (LZ4_STREAMSIZE_U64 * sizeof(unsigned long long))
+union LZ4_stream_u {
+    unsigned long long table[LZ4_STREAMSIZE_U64];
+    LZ4_stream_t_internal internal_donotuse;
+} ;  /* previously typedef'd to LZ4_stream_t */
+
+
+/*!
+ * LZ4_streamDecode_t :
+ * information structure to track an LZ4 stream during decompression.
+ * init this structure  using LZ4_setStreamDecode (or memset()) before first use
+ * note : only use in association with static linking !
+ *        this definition is not API/ABI safe,
+ *        and may change in a future version !
+ */
+#define LZ4_STREAMDECODESIZE_U64  4
+#define LZ4_STREAMDECODESIZE     (LZ4_STREAMDECODESIZE_U64 * sizeof(unsigned long long))
+union LZ4_streamDecode_u {
+    unsigned long long table[LZ4_STREAMDECODESIZE_U64];
+    LZ4_streamDecode_t_internal internal_donotuse;
+} ;   /* previously typedef'd to LZ4_streamDecode_t */
+
+
+/*-************************************
+*  Obsolete Functions
+**************************************/
+
+/*! Deprecation warnings
+   Should deprecation warnings be a problem,
+   it is generally possible to disable them,
+   typically with -Wno-deprecated-declarations for gcc
+   or _CRT_SECURE_NO_WARNINGS in Visual.
+   Otherwise, it's also possible to define LZ4_DISABLE_DEPRECATE_WARNINGS */
+#ifdef LZ4_DISABLE_DEPRECATE_WARNINGS
+#  define LZ4_DEPRECATED(message)   /* disable deprecation warnings */
+#else
+#  define LZ4_GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)
+#  if defined (__cplusplus) && (__cplusplus >= 201402) /* C++14 or greater */
+#    define LZ4_DEPRECATED(message) [[deprecated(message)]]
+#  elif (LZ4_GCC_VERSION >= 405) || defined(__clang__)
+#    define LZ4_DEPRECATED(message) __attribute__((deprecated(message)))
+#  elif (LZ4_GCC_VERSION >= 301)
+#    define LZ4_DEPRECATED(message) __attribute__((deprecated))
+#  elif defined(_MSC_VER)
+#    define LZ4_DEPRECATED(message) __declspec(deprecated(message))
+#  else
+#    pragma message("WARNING: You need to implement LZ4_DEPRECATED for this compiler")
+#    define LZ4_DEPRECATED(message)
+#  endif
+#endif /* LZ4_DISABLE_DEPRECATE_WARNINGS */
+
+/* Obsolete compression functions */
+LZ4_DEPRECATED("use LZ4_compress_default() instead") LZ4LIB_API int LZ4_compress               (const char* source, char* dest, int sourceSize);
+LZ4_DEPRECATED("use LZ4_compress_default() instead") LZ4LIB_API int LZ4_compress_limitedOutput (const char* source, char* dest, int sourceSize, int maxOutputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_extState() instead") LZ4LIB_API int LZ4_compress_withState               (void* state, const char* source, char* dest, int inputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_extState() instead") LZ4LIB_API int LZ4_compress_limitedOutput_withState (void* state, const char* source, char* dest, int inputSize, int maxOutputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_continue() instead") LZ4LIB_API int LZ4_compress_continue                (LZ4_stream_t* LZ4_streamPtr, const char* source, char* dest, int inputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_continue() instead") LZ4LIB_API int LZ4_compress_limitedOutput_continue  (LZ4_stream_t* LZ4_streamPtr, const char* source, char* dest, int inputSize, int maxOutputSize);
+
+/* Obsolete decompression functions */
+LZ4_DEPRECATED("use LZ4_decompress_fast() instead") LZ4LIB_API int LZ4_uncompress (const char* source, char* dest, int outputSize);
+LZ4_DEPRECATED("use LZ4_decompress_safe() instead") LZ4LIB_API int LZ4_uncompress_unknownOutputSize (const char* source, char* dest, int isize, int maxOutputSize);
+
+/* Obsolete streaming functions; degraded functionality; do not use!
+ *
+ * In order to perform streaming compression, these functions depended on data
+ * that is no longer tracked in the state. They have been preserved as well as
+ * possible: using them will still produce a correct output. However, they don't
+ * actually retain any history between compression calls. The compression ratio
+ * achieved will therefore be no better than compressing each chunk
+ * independently.
+ */
+LZ4_DEPRECATED("Use LZ4_createStream() instead") LZ4LIB_API void* LZ4_create (char* inputBuffer);
+LZ4_DEPRECATED("Use LZ4_createStream() instead") LZ4LIB_API int   LZ4_sizeofStreamState(void);
+LZ4_DEPRECATED("Use LZ4_resetStream() instead") LZ4LIB_API  int   LZ4_resetStreamState(void* state, char* inputBuffer);
+LZ4_DEPRECATED("Use LZ4_saveDict() instead") LZ4LIB_API     char* LZ4_slideInputBuffer (void* state);
+
+/* Obsolete streaming decoding functions */
+LZ4_DEPRECATED("use LZ4_decompress_safe_usingDict() instead") LZ4LIB_API int LZ4_decompress_safe_withPrefix64k (const char* src, char* dst, int compressedSize, int maxDstSize);
+LZ4_DEPRECATED("use LZ4_decompress_fast_usingDict() instead") LZ4LIB_API int LZ4_decompress_fast_withPrefix64k (const char* src, char* dst, int originalSize);
+
+#endif /* LZ4_H_2983827168210 */
+
+
+#if defined (__cplusplus)
+}
+#endif

bdk/libs/fatfs/diskio.h

@@ -27,7 +27,8 @@ typedef enum {
 	DRIVE_SD   = 0,
 	DRIVE_RAM  = 1,
 	DRIVE_EMMC = 2,
-	DRIVE_BIS  = 3
+	DRIVE_BIS  = 3,
+	DRIVE_EMU  = 4
 } DDRIVE;
 
 
@@ -40,6 +41,7 @@ DSTATUS disk_status (BYTE pdrv);
 DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
 DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
 DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+DRESULT disk_set_info (BYTE pdrv, BYTE cmd, void *buff);
 
 
 /* Disk Status Bits (DSTATUS) */
@@ -54,9 +56,11 @@ DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
 /* Generic command (Used by FatFs) */
 #define CTRL_SYNC			0	/* Complete pending write process (needed at FF_FS_READONLY == 0) */
 #define GET_SECTOR_COUNT	1	/* Get media size (needed at FF_USE_MKFS == 1) */
+#define SET_SECTOR_COUNT	1	/* Set media size (needed at FF_USE_MKFS == 1) */
 #define GET_SECTOR_SIZE		2	/* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
 #define GET_BLOCK_SIZE		3	/* Get erase block size (needed at FF_USE_MKFS == 1) */
 #define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
+#define SET_SECTOR_OFFSET	5	/* Set media logical offset */
 
 /* Generic command (Not used by FatFs) */
 #define CTRL_POWER			5	/* Get/Set power status */

bdk/libs/fatfs/ff.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -38,8 +38,11 @@
 
 #include "ff.h"			/* Declarations of FatFs API */
 #include "diskio.h"		/* Declarations of device I/O functions */
+#include <storage/mbr_gpt.h>
+#include <gfx_utils.h>
 
-#define EFSPRINTF(text, ...) 
+#define EFSPRINTF(text, ...) print_error(); gfx_printf("%k"text"%k\n", 0xFFFFFF00, 0xFFFFFFFF);
+//#define EFSPRINTF(...)
 
 /*--------------------------------------------------------------------------
 
@@ -530,7 +533,7 @@ static WCHAR LfnBuf[FF_MAX_LFN + 1];		/* LFN working buffer */
 #define FREE_NAMBUF()	ff_memfree(lfn)
 #endif
 #define LEAVE_MKFS(res)	{ if (!work) ff_memfree(buf); return res; }
-#define MAX_MALLOC	0x4000	/* Must be >=FF_MAX_SS */
+#define MAX_MALLOC	0x8000	/* Must be >=FF_MAX_SS */
 
 #else
 #error Wrong setting of FF_USE_LFN
@@ -590,6 +593,16 @@ static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE);
 
 ---------------------------------------------------------------------------*/
 
+/*-----------------------------------------------------------------------*/
+/* Print error header                                                    */
+/*-----------------------------------------------------------------------*/
+
+void print_error()
+{
+	gfx_printf("\n\n\n%k[FatFS] Error: %k", 0xFFFFFF00, 0xFFFFFFFF);
+}
+
+
 /*-----------------------------------------------------------------------*/
 /* Load/Store multi-byte word in the FAT structure                       */
 /*-----------------------------------------------------------------------*/
@@ -3261,7 +3274,6 @@ static FRESULT find_volume (	/* FR_OK(0): successful, !=0: an error occurred */
 		stat = disk_status(fs->pdrv);
 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
 			if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
-				EFSPRINTF("WPEN1");
 				return FR_WRITE_PROTECTED;
 			}
 			return FR_OK;				/* The filesystem object is valid */
@@ -3272,14 +3284,13 @@ static FRESULT find_volume (	/* FR_OK(0): successful, !=0: an error occurred */
 	/* Following code attempts to mount the volume. (analyze BPB and initialize the filesystem object) */
 
 	fs->fs_type = 0;					/* Clear the filesystem object */
+	fs->part_type = 0;					/* Clear the Partition object */
 	fs->pdrv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
 	stat = disk_initialize(fs->pdrv);	/* Initialize the physical drive */
 	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
-		EFSPRINTF("MDNR");
 		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
 	}
 	if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
-		EFSPRINTF("WPEN2");
 		return FR_WRITE_PROTECTED;
 	}
 #if FF_MAX_SS != FF_MIN_SS				/* Get sector size (multiple sector size cfg only) */
@@ -3306,6 +3317,20 @@ static FRESULT find_volume (	/* FR_OK(0): successful, !=0: an error occurred */
 		EFSPRINTF("BRNL");
 		return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
 	}
+#if FF_SIMPLE_GPT
+	if (fmt >= 2) {
+		/* If GPT Check the first partition */
+		gpt_header_t *gpt_header = (gpt_header_t *)fs->win;
+		if (move_window(fs, 1) != FR_OK) return FR_DISK_ERR;
+		if (!mem_cmp(&gpt_header->signature, "EFI PART", 8)) {
+			if (move_window(fs, gpt_header->part_ent_lba) != FR_OK) return FR_DISK_ERR;
+			gpt_entry_t *gpt_entry = (gpt_entry_t *)fs->win;
+			fs->part_type = 1;
+			bsect = gpt_entry->lba_start;
+			fmt = bsect ? check_fs(fs, bsect) : 3;	/* Check the partition */
+		}
+	}
+#endif
 	if (fmt >= 2) {
 		EFSPRINTF("NOFAT");
 		return FR_NO_FILESYSTEM;	/* No FAT volume is found */
@@ -3894,11 +3919,11 @@ FRESULT f_read (
 
 
 
-#ifdef FF_FASTFS
+#if FF_FASTFS && FF_USE_FASTSEEK
 /*-----------------------------------------------------------------------*/
 /* Fast Read Aligned Sized File Without a Cache                         */
 /*-----------------------------------------------------------------------*/
-#if FF_USE_FASTSEEK
+
 FRESULT f_read_fast (
 	FIL* fp,			/* Pointer to the file object */
 	const void* buff,	/* Pointer to the data to be written */
@@ -3909,12 +3934,13 @@ FRESULT f_read_fast (
 	FATFS *fs;
 	UINT csize_bytes;
 	DWORD clst;
-	DWORD wbytes;
+	UINT count = 0;
-	UINT count;
 	FSIZE_t work_sector = 0;
 	FSIZE_t sector_base = 0;
 	BYTE *wbuff = (BYTE*)buff;
 
+	// TODO support sector reading inside a cluster
+
 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
 		EFSPRINTF("FOV");
@@ -3926,17 +3952,6 @@ FRESULT f_read_fast (
 	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
 
 	csize_bytes = fs->csize * SS(fs);
-	DWORD csect = (UINT)((fp->fptr / SS(fs)) & (fs->csize - 1));	/* Sector offset in the cluster */
-
-	/* If inside a cluster, read the sectors and align to cluster. */
-	if (csect) {
-		wbytes = MIN(btr, (fs->csize - csect) * SS(fs));
-		f_read(fp, wbuff, wbytes, (void *)0);
-		wbuff += wbytes;
-		btr -= wbytes;
-		if (!btr)
-			goto out;
-	}
 
 	if (!fp->fptr) {	/* On the top of the file? */
 		clst = fp->obj.sclust;	/* Follow from the origin */
@@ -3944,22 +3959,15 @@ FRESULT f_read_fast (
 		if (fp->cltbl) clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
 		else { EFSPRINTF("CLTBL"); ABORT(fs, FR_CLTBL_NO_INIT); }
 	}
-
 	if (clst < 2) { EFSPRINTF("CCHK"); ABORT(fs, FR_INT_ERR); }
 	else if (clst == 0xFFFFFFFF) { EFSPRINTF("DSKC"); ABORT(fs, FR_DISK_ERR); }
 
 	fp->clust = clst;	/* Set working cluster */
 
-	wbytes = MIN(btr, csize_bytes);
 	sector_base = clst2sect(fs, fp->clust);
-	count = wbytes / SS(fs);
+	count += fs->csize;
-	fp->fptr += wbytes;
+	btr -= csize_bytes;
-	btr -= wbytes;
+	fp->fptr += csize_bytes;
-
-	if (!btr) {	/* Final cluster/sectors read. */
-		if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
-		goto out;
-	}
 
 	while (btr) {
 		clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
@@ -3970,29 +3978,29 @@ FRESULT f_read_fast (
 		fp->clust = clst;
 
 		work_sector = clst2sect(fs, fp->clust);
-		wbytes = MIN(btr, csize_bytes);
+		if ((work_sector - sector_base) == count) count += fs->csize;
-		if ((work_sector - sector_base) == count) count += wbytes / SS(fs);
 		else {
 			if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
 			wbuff += count * SS(fs);
 
 			sector_base = work_sector;
-			count = wbytes / SS(fs);
+			count = fs->csize;
 		}
 
-		fp->fptr += wbytes;
+		fp->fptr += MIN(btr, csize_bytes);
-		btr -= wbytes;
+		btr -= MIN(btr, csize_bytes);
+
+		// TODO: what about if data is smaller than cluster?
+		// Must read-write back that cluster.
 
 		if (!btr) {	/* Final cluster/sectors read. */
 			if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
 		}
 	}
 
-out:
 	LEAVE_FF(fs, FR_OK);
 }
 #endif
-#endif
 
 
 
@@ -4136,11 +4144,11 @@ FRESULT f_write (
 
 
 
-#ifdef FF_FASTFS
+#if FF_FASTFS && FF_USE_FASTSEEK
 /*-----------------------------------------------------------------------*/
 /* Fast Write Aligned Sized File Without a Cache                         */
 /*-----------------------------------------------------------------------*/
-#if FF_USE_FASTSEEK
+
 FRESULT f_write_fast (
 	FIL* fp,			/* Pointer to the file object */
 	const void* buff,	/* Pointer to the data to be written */
@@ -4151,11 +4159,12 @@ FRESULT f_write_fast (
 	FATFS *fs;
 	UINT csize_bytes;
 	DWORD clst;
-	DWORD wbytes;
+	UINT count = 0;
-	UINT count;
 	FSIZE_t work_sector = 0;
 	FSIZE_t sector_base = 0;
-	BYTE *wbuff = (BYTE*)buff;
+	const BYTE *wbuff = (const BYTE*)buff;
+
+	// TODO support sector writing inside a cluster
 
 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
@@ -4170,19 +4179,6 @@ FRESULT f_write_fast (
 	}
 
 	csize_bytes = fs->csize * SS(fs);
-	DWORD csect = (UINT)((fp->fptr / SS(fs)) & (fs->csize - 1));	/* Sector offset in the cluster */
-
-	/* If inside a cluster, write the sectors and align to cluster. */
-	if (csect) {
-		wbytes = MIN(btw, (fs->csize - csect) * SS(fs));
-		f_write(fp, wbuff, wbytes, (void *)0);
-		/* Ensure flushing of it. FatFS is not notified for next write if raw. */
-		f_sync(fp);
-		wbuff += wbytes;
-		btw -= wbytes;
-		if (!btw)
-			goto out;
-	}
 
 	if (!fp->fptr) {	/* On the top of the file? */
 		clst = fp->obj.sclust;	/* Follow from the origin */
@@ -4192,57 +4188,49 @@ FRESULT f_write_fast (
 	}
 
 	if (clst < 2) { EFSPRINTF("CCHK"); ABORT(fs, FR_INT_ERR); }
-	else if (clst == 0xFFFFFFFF) { EFSPRINTF("DSKC"); ABORT(fs, FR_DISK_ERR); }
+	else if (clst == 0xFFFFFFFF) { EFSPRINTF("DERR"); ABORT(fs, FR_DISK_ERR); }
 
 	fp->clust = clst;	/* Set working cluster */
 
-	wbytes = MIN(btw, csize_bytes);
 	sector_base = clst2sect(fs, fp->clust);
-	count = wbytes / SS(fs);
+	count += fs->csize;
-	fp->fptr += wbytes;
+	btw -= csize_bytes;
-	btw -= wbytes;
+	fp->fptr += csize_bytes;
-
-	if (!btw) {	/* Final cluster/sectors write. */
-		if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
-		fp->flag &= (BYTE)~FA_DIRTY;
-		goto out;
-	}
 
 	while (btw) {
 		clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
 
 		if (clst < 2) { EFSPRINTF("CCHK2"); ABORT(fs, FR_INT_ERR); }
-		else if (clst == 0xFFFFFFFF) { EFSPRINTF("DSKC"); ABORT(fs, FR_DISK_ERR); }
+		else if (clst == 0xFFFFFFFF) { EFSPRINTF("DERR"); ABORT(fs, FR_DISK_ERR); }
 
 		fp->clust = clst;
 
 		work_sector = clst2sect(fs, fp->clust);
-		wbytes = MIN(btw, csize_bytes);
+		if ((work_sector - sector_base) == count) count += fs->csize;
-		if ((work_sector - sector_base) == count) count += wbytes / SS(fs);
 		else {
 			if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
 			wbuff += count * SS(fs);
 
 			sector_base = work_sector;
-			count = wbytes / SS(fs);
+			count = fs->csize;
 		}
 
-		fp->fptr += wbytes;
+		fp->fptr += MIN(btw, csize_bytes);
-		btw -= wbytes;
+		btw -= MIN(btw, csize_bytes);
 
+		// what about if data is smaller than cluster?
+		// Probably must read-write back that cluster.
 		if (!btw) {	/* Final cluster/sectors write. */
 			if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
 			fp->flag &= (BYTE)~FA_DIRTY;
 		}
 	}
 
-out:
 	fp->flag |= FA_MODIFIED;	/* Set file change flag */
 
 	LEAVE_FF(fs, FR_OK);
 }
 #endif
-#endif
 
 
 
@@ -4703,8 +4691,7 @@ FRESULT f_lseek (
 
 
 
-#ifdef FF_FASTFS
+#if FF_FASTFS && FF_USE_FASTSEEK
-#if FF_USE_FASTSEEK
 /*-----------------------------------------------------------------------*/
 /* Seek File Read/Write Pointer                                          */
 /*-----------------------------------------------------------------------*/
@@ -4712,14 +4699,16 @@ FRESULT f_lseek (
 DWORD *f_expand_cltbl (
 	FIL* fp,		/* Pointer to the file object */
 	UINT tblsz,		/* Size of table */
-	DWORD *tbl,		/* Table pointer */
 	FSIZE_t ofs		/* File pointer from top of file */
 )
 {
 	if (fp->flag & FA_WRITE) f_lseek(fp, ofs);	/* Expand file if write is enabled */
-	fp->cltbl = (DWORD *)tbl;
+	if (!fp->cltbl) {	/* Allocate memory for cluster link table */
+		fp->cltbl = (DWORD *)ff_memalloc(tblsz);
 		fp->cltbl[0] = tblsz;
+	}
 	if (f_lseek(fp, CREATE_LINKMAP)) {	/* Create cluster link table */
+		ff_memfree(fp->cltbl);
 		fp->cltbl = (void *)0;
 		EFSPRINTF("CLTBLSZ");
 		return (void *)0;
@@ -4729,7 +4718,6 @@ DWORD *f_expand_cltbl (
 	return fp->cltbl;
 }
 #endif
-#endif
 
 
 
@@ -5863,7 +5851,7 @@ FRESULT f_mkfs (
 	UINT len			/* Size of working buffer [byte] */
 )
 {
-	const UINT n_fats = 1;		/* Number of FATs for FAT/FAT32 volume (1 or 2) */
+	const UINT n_fats = 2;		/* Number of FATs for FAT/FAT32 volume (1 or 2) */
 	const UINT n_rootdir = 512;	/* Number of root directory entries for FAT volume */
 	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT volume (4Ks unit) */
 	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (128Ks unit) */
@@ -5927,7 +5915,7 @@ FRESULT f_mkfs (
 	} else {
 		/* Create a single-partition in this function */
 		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
-		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+		b_vol = (opt & FM_SFD) ? 0 : 32768;		/* Volume start sector. Align to 16MB */
 		if (sz_vol < b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);
 		sz_vol -= b_vol;						/* Volume size */
 	}
@@ -6151,6 +6139,9 @@ FRESULT f_mkfs (
 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
 				sz_rsv += n; b_fat += n;
 			} else {					/* FAT: Expand FAT size */
+				if (n % n_fats) {	/* Adjust fractional error if needed */
+					n--; sz_rsv++; b_fat++;
+				}
 				sz_fat += n / n_fats;
 			}
 
@@ -6191,7 +6182,9 @@ FRESULT f_mkfs (
 #endif
 		/* Create FAT VBR */
 		mem_set(buf, 0, ss);
-		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+		/* Boot jump code (x86), OEM name */
+		if (!(opt & FM_PRF2)) mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "NYX1.0.0", 11);
+		else mem_cpy(buf + BS_JmpBoot, "\xEB\xE9\x90\x00\x00\x00\x00\x00\x00\x00\x00", 11);
 		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
 		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
 		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
@@ -6204,23 +6197,27 @@ FRESULT f_mkfs (
 		}
 		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
 		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
-		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+		st_word(buf + BPB_NumHeads, (opt & FM_PRF2) ? 16 : 255);	/* Number of heads (for int13) */
 		st_dword(buf + BPB_HiddSec, b_vol);				/* Volume offset in the physical drive [sector] */
 		if (fmt == FS_FAT32) {
-			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+			st_dword(buf + BS_VolID32, (opt & FM_PRF2) ? 0 : GET_FATTIME());	/* VSN */
 			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
 			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
 			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
 			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
 			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
 			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
-			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+			/* Volume label, FAT signature */
+			if (!(opt & FM_PRF2)) mem_cpy(buf + BS_VolLab32, FF_MKFS_LABEL "FAT32   ", 19);
+			else mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);
 		} else {
 			st_dword(buf + BS_VolID, GET_FATTIME());	/* VSN */
 			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
 			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
 			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
-			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+			/* Volume label, FAT signature */
+			if (!(opt & FM_PRF2)) mem_cpy(buf + BS_VolLab, FF_MKFS_LABEL "FAT     ", 19);
+			else mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);
 		}
 		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
 		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Write it to the VBR sector */
@@ -6238,6 +6235,16 @@ FRESULT f_mkfs (
 			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
 		}
 
+		/* Create PRF2SAFE info */
+		if (fmt == FS_FAT32 && opt & FM_PRF2) {
+			mem_set(buf, 0, ss);
+			buf[16] = 0x64;							/* Record type */
+			st_dword(buf + 32, 0x03);				/* Unknown. SYSTEM: 0x3F00. USER: 0x03. Volatile. */
+			st_dword(buf + 36, 25);					/* Entries. SYSTEM: 22. USER: 25.Static? */
+			st_dword(buf + 508, 0x517BBFE0);		/* Custom CRC32. SYSTEM: 0x6B673904. USER: 0x517BBFE0. */
+			disk_write(pdrv, buf, b_vol + 3, 1);	/* Write PRF2SAFE info (VBR + 3) */
+		}
+
 		/* Initialize FAT area */
 		mem_set(buf, 0, (UINT)szb_buf);
 		sect = b_fat;		/* FAT start sector */
@@ -6727,6 +6734,8 @@ int f_puts (
 	putbuff pb;
 
 
+	if (str == (void *)0) return EOF; /* String is NULL */
+
 	putc_init(&pb, fp);
 	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
 	return putc_flush(&pb);
@@ -6753,6 +6762,8 @@ int f_printf (
 	TCHAR c, d, str[32], *p;
 
 
+	if (fmt == (void *)0) return EOF; /* String is NULL */
+
 	putc_init(&pb, fp);
 
 	va_start(arp, fmt);

bdk/libs/fatfs/ff.h

@@ -97,6 +97,7 @@ typedef DWORD FSIZE_t;
 typedef struct {
 	BYTE	win[FF_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
 	BYTE	fs_type;		/* Filesystem type (0:not mounted) */
+	BYTE	part_type;		/* Partition type (0:MBR, 1:GPT) */
 	BYTE	pdrv;			/* Associated physical drive */
 	BYTE	n_fats;			/* Number of FATs (1 or 2) */
 	BYTE	wflag;			/* win[] flag (b0:dirty) */
@@ -168,9 +169,6 @@ typedef struct {
 /* File object structure (FIL) */
 
 typedef struct {
-#if !FF_FS_TINY
-	BYTE	buf[FF_MAX_SS];	/* File private data read/write window */
-#endif
 	FFOBJID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
 	BYTE	flag;			/* File status flags */
 	BYTE	err;			/* Abort flag (error code) */
@@ -184,6 +182,9 @@ typedef struct {
 #if FF_USE_FASTSEEK
 	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
 #endif
+#if !FF_FS_TINY
+	BYTE	buf[FF_MAX_SS] __attribute__((aligned(8)));	/* File private data read/write window. DMA aligned. */
+#endif
 } FIL;
 
 
@@ -263,10 +264,8 @@ FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a f
 FRESULT f_close (FIL* fp);											/* Close an open file object */
 FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
 FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
-#ifdef FF_FASTFS
 FRESULT f_read_fast (FIL* fp, const void* buff, UINT btr);			/* Fast read data from the file */
 FRESULT f_write_fast (FIL* fp, const void* buff, UINT btw);         /* Fast write data to the file */
-#endif
 FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
 FRESULT f_truncate (FIL* fp);										/* Truncate the file */
 FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
@@ -288,9 +287,7 @@ FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get numbe
 FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
 FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
 FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
-#ifdef FF_FASTFS
+DWORD  *f_expand_cltbl (FIL* fp, UINT tblsz, FSIZE_t ofs);			/* Expand file and populate cluster table */
-DWORD  *f_expand_cltbl (FIL* fp, UINT tblsz, DWORD *tbl, FSIZE_t ofs);	/* Expand file and populate cluster table */
-#endif
 FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt);					/* Allocate a contiguous block to the file */
 FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
 FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
@@ -369,6 +366,7 @@ int ff_del_syncobj (FF_SYNC_t sobj);	/* Delete a sync object */
 #define FM_EXFAT	0x04
 #define FM_ANY		0x07
 #define FM_SFD		0x08
+#define FM_PRF2		0x10
 
 /* Filesystem type (FATFS.fs_type) */
 #define FS_FAT12	1

bdk/libs/lv_conf.h

@@ -155,7 +155,11 @@
 
 
 /*Log settings*/
+#ifdef DEBUG_UART_LV_LOG
+#  define USE_LV_LOG        1   /*Enable/disable the log module*/
+#else
 #  define USE_LV_LOG        0   /*Enable/disable the log module*/
+#endif
 #if USE_LV_LOG
 /* How important log should be added:
  * LV_LOG_LEVEL_TRACE       A lot of logs to give detailed information

bdk/libs/lvgl/lv_misc/lv_log.c

@@ -63,11 +63,11 @@ void lv_log_add(lv_log_level_t level, const char * file, int line, const char *
 
     if(level >= LV_LOG_LEVEL) {
 
-#if LV_LOG_PRINTF
+#if LV_LOG_PRINTF && defined(DEBUG_UART_PORT)
         static const char * lvl_prefix[] = {"Trace", "Info", "Warn", "Error"};
         char *log = (char *)malloc(0x1000);
         s_printf(log, "%s: %s \t(%s #%d)\r\n", lvl_prefix[level], dsc,  file, line);
-        uart_send(UART_B, (u8 *)log, strlen(log) + 1);
+        uart_send(DEBUG_UART_PORT, (u8 *)log, strlen(log) + 1);
         //gfx_printf("%s: %s \t(%s #%d)\n", lvl_prefix[level], dsc,  file, line);
 #else
         if(print_cb) print_cb(level, file, line, dsc);

bdk/libs/nx_savedata/allocation_table_storage.c

@@ -38,12 +38,21 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 #include <gfx_utils.h>
 
-void save_allocation_table_storage_init(allocation_table_storage_ctx_t *ctx, substorage *data, allocation_table_ctx_t *table, uint32_t block_size, uint32_t initial_block) {
+bool save_allocation_table_storage_init(allocation_table_storage_ctx_t *ctx, substorage *data, allocation_table_ctx_t *table, uint32_t block_size, uint32_t initial_block) {
     ctx->base_storage = data;
     ctx->block_size = block_size;
     ctx->fat = table;
     ctx->initial_block = initial_block;
-    ctx->_length = initial_block == 0xFFFFFFFF ? 0 : save_allocation_table_get_list_length(table, initial_block) * block_size;
+    ctx->_length = 0;
+    if (initial_block != 0xFFFFFFFF) {
+        uint32_t list_length = save_allocation_table_get_list_length(table, initial_block);
+        if (list_length == 0) {
+            EPRINTF("Allocation table storage init failed!");
+            return false;
+        };
+        ctx->_length = list_length * block_size;
+    }
+    return true;
 }
 
 uint32_t save_allocation_table_storage_read(allocation_table_storage_ctx_t *ctx, void *buffer, uint64_t offset, uint64_t count) {

bdk/libs/nx_savedata/allocation_table_storage.h

@@ -52,7 +52,7 @@ static ALWAYS_INLINE void save_allocation_table_storage_get_size(allocation_tabl
     *out_size = ctx->_length;
 }
 
-void save_allocation_table_storage_init(allocation_table_storage_ctx_t *ctx, substorage *data, allocation_table_ctx_t *table, uint32_t block_size, uint32_t initial_block);
+bool save_allocation_table_storage_init(allocation_table_storage_ctx_t *ctx, substorage *data, allocation_table_ctx_t *table, uint32_t block_size, uint32_t initial_block);
 uint32_t save_allocation_table_storage_read(allocation_table_storage_ctx_t *ctx, void *buffer, uint64_t offset, uint64_t count);
 uint32_t save_allocation_table_storage_write(allocation_table_storage_ctx_t *ctx, const void *buffer, uint64_t offset, uint64_t count);
 bool save_allocation_table_storage_set_size(allocation_table_storage_ctx_t *ctx, uint64_t size);

bdk/libs/nx_savedata/cached_storage.c

@@ -49,7 +49,7 @@ static ALWAYS_INLINE cache_block_t *cache_block_init(cached_storage_ctx_t *ctx)
 void save_cached_storage_init(cached_storage_ctx_t *ctx, substorage *base_storage, uint32_t block_size, uint32_t cache_size) {
     memcpy(&ctx->base_storage, base_storage, sizeof(substorage));
     ctx->block_size = block_size;
-    substorage_get_size(base_storage, &ctx->length);
+    ctx->length = base_storage->length;
     ctx->cache_size = cache_size;
 
     list_init(&ctx->blocks);
@@ -69,6 +69,8 @@ static void cache_block_finalize(cache_block_t **block) {
 }
 
 void save_cached_storage_finalize(cached_storage_ctx_t *ctx) {
+    if (!ctx->blocks.next)
+        return;
     LIST_FOREACH_SAFE(curr_block, &ctx->blocks) {
         cache_block_t *block = CONTAINER_OF(curr_block, cache_block_t, link) ;
         cache_block_finalize(&block);
@@ -76,6 +78,8 @@ void save_cached_storage_finalize(cached_storage_ctx_t *ctx) {
 }
 
 static bool try_get_block_by_value(cached_storage_ctx_t *ctx, uint64_t index, cache_block_t **out_block) {
+    if (!ctx->blocks.next)
+        return false;
     LIST_FOREACH_ENTRY(cache_block_t, block, &ctx->blocks, link) {
         if (block->index == index) {
             *out_block = block;

bdk/libs/nx_savedata/header.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020 shchmue
+ * Copyright (c) 2019-2022 shchmue
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -61,7 +61,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 #define VERSION_RMAP         0x10000
 #define VERSION_IVFC         0x20000
 
-#define SAVE_BLOCK_SIZE_DEFAULT 0x4000
+#define SAVE_BLOCK_SIZE_DEFAULT SZ_16K
 
 #define SAVE_NUM_HEADERS 2
 
@@ -232,6 +232,6 @@ typedef struct {
     };
 } save_header_t;
 
-static_assert(sizeof(save_header_t) == 0x4000, "Save header size is wrong!");
+static_assert(sizeof(save_header_t) == SZ_16K, "Save header size is wrong!");
 
 #endif

bdk/libs/nx_savedata/hierarchical_integrity_verification_storage.c

@@ -135,7 +135,7 @@ validity_t save_hierarchical_integrity_verification_storage_validate(hierarchica
     validity_t result = VALIDITY_VALID;
     integrity_verification_storage_ctx_t *storage = &ctx->integrity_storages[3];
 
-    uint64_t block_size = storage->base_storage.sector_size;
+    uint32_t block_size = storage->base_storage.sector_size;
     uint32_t block_count = (uint32_t)(DIV_ROUND_UP(ctx->length, block_size));
 
     uint8_t *buffer = malloc(block_size);
@@ -143,7 +143,7 @@ validity_t save_hierarchical_integrity_verification_storage_validate(hierarchica
     for (unsigned int i = 0; i < block_count; i++) {
         if (ctx->level_validities[3][i] == VALIDITY_UNCHECKED) {
             uint64_t storage_size = storage->base_storage.length;
-            uint32_t to_read = MIN((uint32_t)(storage_size - block_size * i), (uint32_t)block_size);
+            uint32_t to_read = MIN((uint32_t)(storage_size - block_size * i), block_size);
             substorage_read(&ctx->data_level->base_storage, buffer, block_size * i, to_read);
         }
         if (ctx->level_validities[3][i] == VALIDITY_INVALID) {

bdk/libs/nx_savedata/hierarchical_save_file_table.c

@@ -207,7 +207,7 @@ void save_hierarchical_file_table_unlink_file_from_parent(hierarchical_save_file
             return;
         }
         prev_index = cur_index;
-        memcpy(&prev_entry, &cur_entry, sizeof(prev_entry));
+        memcpy(&prev_entry, &cur_entry, sizeof(save_table_entry_t));
         cur_index = prev_entry.next_sibling;
     }
 }
@@ -236,7 +236,7 @@ void save_hierarchical_file_table_unlink_directory_from_parent(hierarchical_save
             return;
         }
         prev_index = cur_index;
-        memcpy(&prev_entry, &cur_entry, sizeof(prev_entry));
+        memcpy(&prev_entry, &cur_entry, sizeof(save_table_entry_t));
         cur_index = prev_entry.next_sibling;
     }
 }

bdk/libs/nx_savedata/integrity_verification_storage.c

@@ -52,7 +52,7 @@ void save_ivfc_storage_init(integrity_verification_storage_ctx_t *ctx, integrity
 /* buffer must have size count + 0x20 for salt to by copied in at offset 0. */
 static ALWAYS_INLINE void save_ivfc_storage_do_hash(integrity_verification_storage_ctx_t *ctx, uint8_t *out_hash, void *buffer, uint64_t count) {
     memcpy(buffer, ctx->salt, sizeof(ctx->salt));
-    se_calc_sha256(out_hash, buffer, count + sizeof(ctx->salt));
+    se_calc_sha256_oneshot(out_hash, buffer, count + sizeof(ctx->salt));
     out_hash[0x1F] |= 0x80;
 }
 
@@ -81,7 +81,7 @@ bool save_ivfc_storage_read(integrity_verification_storage_ctx_t *ctx, void *buf
         return false;
     }
 
-    uint8_t hash_buffer[0x20] = {0};
+    uint8_t hash_buffer[0x20] __attribute__((aligned(4))) = {0};
     uint64_t hash_pos = block_index * sizeof(hash_buffer);
 
     if (substorage_read(&ctx->hash_storage, hash_buffer, hash_pos, sizeof(hash_buffer)) != sizeof(hash_buffer))
@@ -99,17 +99,16 @@ bool save_ivfc_storage_read(integrity_verification_storage_ctx_t *ctx, void *buf
         return false;
     }
 
-    if (ctx->integrity_check_level && ctx->block_validities[block_index] != VALIDITY_UNCHECKED) {
     memcpy(buffer, data_buffer + 0x20 + (offset % ctx->base_storage.sector_size), count);
+
+    if (ctx->integrity_check_level && ctx->block_validities[block_index] != VALIDITY_UNCHECKED) {
         free(data_buffer);
         return true;
     }
 
-    uint8_t hash[0x20] = {0};
+    uint8_t hash[0x20] __attribute__((aligned(4))) = {0};
     save_ivfc_storage_do_hash(ctx, hash, data_buffer, ctx->base_storage.sector_size);
-    memcpy(buffer, data_buffer + 0x20 + (offset % ctx->base_storage.sector_size), count);
     free(data_buffer);
-
     if (memcmp(hash_buffer, hash, sizeof(hash_buffer)) == 0) {
         ctx->block_validities[block_index] = VALIDITY_VALID;
     } else {
@@ -127,7 +126,7 @@ bool save_ivfc_storage_write(integrity_verification_storage_ctx_t *ctx, const vo
     uint64_t block_index = offset / ctx->base_storage.sector_size;
     uint64_t hash_pos = block_index * 0x20;
 
-    uint8_t hash[0x20] = {0};
+    uint8_t hash[0x20] __attribute__((aligned(4))) = {0};
     uint8_t *data_buffer = calloc(1, ctx->base_storage.sector_size + 0x20);
     if (count < ctx->base_storage.sector_size) {
         if (substorage_read(&ctx->base_storage.base_storage, data_buffer + 0x20, offset - (offset % ctx->base_storage.sector_size), ctx->base_storage.sector_size) != ctx->base_storage.sector_size) {

bdk/libs/nx_savedata/remap_storage.c

@@ -102,7 +102,7 @@ uint32_t save_remap_storage_read(remap_storage_ctx_t *ctx, void *buffer, uint64_
     }
     uint64_t in_pos = offset;
     uint32_t out_pos = 0;
-    uint32_t remaining = count;
+    uint32_t remaining = (u32)count;
 
     while (remaining) {
         uint64_t entry_pos = in_pos - entry->entry.virtual_offset;
@@ -135,7 +135,7 @@ uint32_t save_remap_storage_write(remap_storage_ctx_t *ctx, const void *buffer,
     }
     uint64_t in_pos = offset;
     uint32_t out_pos = 0;
-    uint32_t remaining = count;
+    uint32_t remaining = (u32)count;
 
     while (remaining) {
         uint64_t entry_pos = in_pos - entry->entry.virtual_offset;

bdk/libs/nx_savedata/remap_storage.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020 shchmue
+ * Copyright (c) 2019-2022 shchmue
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -41,7 +41,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 #include <stdint.h>
 
 #define RMAP_ALIGN_SMALL 0x200
-#define RMAP_ALIGN_LARGE 0x4000
+#define RMAP_ALIGN_LARGE SZ_16K
 
 typedef struct {
     uint32_t magic; /* RMAP */

bdk/libs/nx_savedata/save.c

@@ -98,13 +98,13 @@ static bool save_process_header(save_ctx_t *ctx) {
     ctx->data_ivfc_master = (uint8_t *)&ctx->header + ctx->header.layout.ivfc_master_hash_offset_a;
     ctx->fat_ivfc_master = (uint8_t *)&ctx->header + ctx->header.layout.fat_ivfc_master_hash_a;
 
-    uint8_t hash[0x20];
+    uint8_t hash[0x20] __attribute__((aligned(4)));
     uint32_t hashed_data_offset = sizeof(ctx->header.layout) + sizeof(ctx->header.cmac) + sizeof(ctx->header._0x10);
     uint32_t hashed_data_size = sizeof(ctx->header) - hashed_data_offset;
-    se_calc_sha256(hash, (uint8_t *)&ctx->header + hashed_data_offset, hashed_data_size);
+    se_calc_sha256_oneshot(hash, (uint8_t *)&ctx->header + hashed_data_offset, hashed_data_size);
-    ctx->header_hash_validity = memcmp(hash, ctx->header.layout.hash, 0x20) == 0 ? VALIDITY_VALID : VALIDITY_INVALID;
+    ctx->header_hash_validity = memcmp(hash, ctx->header.layout.hash, sizeof(hash)) == 0 ? VALIDITY_VALID : VALIDITY_INVALID;
 
-    unsigned char cmac[0x10] = {};
+    uint8_t cmac[0x10] __attribute__((aligned(4)));
     se_aes_key_set(10, ctx->save_mac_key, 0x10);
     se_aes_cmac(10, cmac, 0x10, &ctx->header.layout, sizeof(ctx->header.layout));
     if (memcmp(cmac, &ctx->header.cmac, 0x10) == 0) {
@@ -126,14 +126,14 @@ bool save_process(save_ctx_t *ctx) {
     substorage_init(&ctx->base_storage, &file_storage_vt, ctx->file, 0, f_size(ctx->file));
     /* Try to parse Header A. */
     if (substorage_read(&ctx->base_storage, &ctx->header, 0, sizeof(ctx->header)) != sizeof(ctx->header)) {
-        EPRINTF("Failed to read save header!\n");
+        EPRINTF("Failed to read save header A!\n");
         return false;
     }
 
     if (!save_process_header(ctx) || (ctx->header_hash_validity == VALIDITY_INVALID)) {
         /* Try to parse Header B. */
         if (substorage_read(&ctx->base_storage, &ctx->header, sizeof(ctx->header), sizeof(ctx->header)) != sizeof(ctx->header)) {
-            EPRINTF("Failed to read save header!\n");
+            EPRINTF("Failed to read save header B!\n");
             return false;
         }
 
@@ -143,14 +143,22 @@ bool save_process(save_ctx_t *ctx) {
         }
     }
 
+    if (ctx->header.layout.version > VERSION_DISF_5) {
+        EPRINTF("Unsupported save version.\nLibrary must be updated.");
+        return false;
+    }
+
     /* Initialize remap storages. */
     ctx->data_remap_storage.header = &ctx->header.main_remap_header;
     ctx->meta_remap_storage.header = &ctx->header.meta_remap_header;
 
+    u32 data_remap_entry_size = sizeof(remap_entry_t) * ctx->data_remap_storage.header->map_entry_count;
+    u32 meta_remap_entry_size = sizeof(remap_entry_t) * ctx->meta_remap_storage.header->map_entry_count;
+
     substorage_init(&ctx->data_remap_storage.base_storage, &file_storage_vt, ctx->file, ctx->header.layout.file_map_data_offset, ctx->header.layout.file_map_data_size);
     ctx->data_remap_storage.map_entries = calloc(1, sizeof(remap_entry_ctx_t) * ctx->data_remap_storage.header->map_entry_count);
-    uint8_t *remap_buffer = malloc(MAX(ctx->data_remap_storage.header->map_entry_count, ctx->meta_remap_storage.header->map_entry_count) * sizeof(remap_entry_t));
+    uint8_t *remap_buffer = malloc(MAX(data_remap_entry_size, meta_remap_entry_size));
-    if (substorage_read(&ctx->base_storage, remap_buffer, ctx->header.layout.file_map_entry_offset, sizeof(remap_entry_t) * ctx->data_remap_storage.header->map_entry_count) != sizeof(remap_entry_t) * ctx->data_remap_storage.header->map_entry_count) {
+    if (substorage_read(&ctx->base_storage, remap_buffer, ctx->header.layout.file_map_entry_offset, data_remap_entry_size) != data_remap_entry_size) {
         EPRINTF("Failed to read data remap table!");
         free(remap_buffer);
         return false;
@@ -177,7 +185,7 @@ bool save_process(save_ctx_t *ctx) {
     /* Initialize meta remap storage. */
     substorage_init(&ctx->meta_remap_storage.base_storage, &hierarchical_duplex_storage_vt, &ctx->duplex_storage, 0, ctx->duplex_storage.data_layer->_length);
     ctx->meta_remap_storage.map_entries = calloc(1, sizeof(remap_entry_ctx_t) * ctx->meta_remap_storage.header->map_entry_count);
-    if (substorage_read(&ctx->base_storage, remap_buffer, ctx->header.layout.meta_map_entry_offset, sizeof(remap_entry_t) * ctx->meta_remap_storage.header->map_entry_count) != sizeof(remap_entry_t) * ctx->meta_remap_storage.header->map_entry_count) {
+    if (substorage_read(&ctx->base_storage, remap_buffer, ctx->header.layout.meta_map_entry_offset, meta_remap_entry_size) != meta_remap_entry_size) {
         EPRINTF("Failed to read meta remap table!");
         free(remap_buffer);
         return false;
@@ -225,42 +233,68 @@ bool save_process(save_ctx_t *ctx) {
     }
 
     /* Initialize core save filesystem. */
-    save_data_file_system_core_init(&ctx->save_filesystem_core, &ctx->core_data_ivfc_storage.base_storage, ctx->fat_storage, &ctx->header.save_header);
+    return save_data_file_system_core_init(&ctx->save_filesystem_core, &ctx->core_data_ivfc_storage.base_storage, ctx->fat_storage, &ctx->header.save_header);
-
-    return true;
 }
 
 void save_free_contexts(save_ctx_t *ctx) {
+    if (ctx->data_remap_storage.header) {
         for (unsigned int i = 0; i < ctx->data_remap_storage.header->map_segment_count; i++) {
+            if (ctx->data_remap_storage.segments && ctx->data_remap_storage.segments[i].entries)
                 free(ctx->data_remap_storage.segments[i].entries);
         }
+    }
+    if (ctx->data_remap_storage.segments)
         free(ctx->data_remap_storage.segments);
+
+    if (ctx->meta_remap_storage.header) {
         for (unsigned int i = 0; i < ctx->meta_remap_storage.header->map_segment_count; i++) {
+            if (ctx->meta_remap_storage.segments && ctx->meta_remap_storage.segments[i].entries)
                 free(ctx->meta_remap_storage.segments[i].entries);
         }
+    }
+    if (ctx->meta_remap_storage.segments)
         free(ctx->meta_remap_storage.segments);
+
+    if (ctx->data_remap_storage.map_entries)
         free(ctx->data_remap_storage.map_entries);
+    if (ctx->meta_remap_storage.map_entries)
         free(ctx->meta_remap_storage.map_entries);
+
     for (unsigned int i = 0; i < 2; i++) {
+        if (ctx->duplex_storage.layers[i].bitmap.bitmap)
             free(ctx->duplex_storage.layers[i].bitmap.bitmap);
+        if (ctx->duplex_storage.layers[i].data_a.base_storage.ctx)
             free(ctx->duplex_storage.layers[i].data_a.base_storage.ctx);
+        if (ctx->duplex_storage.layers[i].data_b.base_storage.ctx)
             free(ctx->duplex_storage.layers[i].data_b.base_storage.ctx);
     }
+    if (ctx->duplex_storage.layers[1].bitmap_storage.base_storage.ctx)
         free(ctx->duplex_storage.layers[1].bitmap_storage.base_storage.ctx);
+
+    if (ctx->journal_storage.map.map_storage)
         free(ctx->journal_storage.map.map_storage);
+    if (ctx->journal_storage.map.entries)
         free(ctx->journal_storage.map.entries);
+
     for (unsigned int i = 0; i < 4; i++) {
+        if (ctx->core_data_ivfc_storage.integrity_storages[i].block_validities)
             free(ctx->core_data_ivfc_storage.integrity_storages[i].block_validities);
         save_cached_storage_finalize(&ctx->core_data_ivfc_storage.levels[i + 1]);
     }
+    if (ctx->core_data_ivfc_storage.level_validities)
         free(ctx->core_data_ivfc_storage.level_validities);
+
     if (ctx->header.layout.version >= VERSION_DISF_5) {
         for (unsigned int i = 0; i < 3; i++) {
+            if (ctx->fat_ivfc_storage.integrity_storages[i].block_validities)
                 free(ctx->fat_ivfc_storage.integrity_storages[i].block_validities);
             save_cached_storage_finalize(&ctx->fat_ivfc_storage.levels[i + 1]);
         }
     }
+    if (ctx->fat_ivfc_storage.level_validities)
         free(ctx->fat_ivfc_storage.level_validities);
+
+    if (ctx->fat_storage)
         free(ctx->fat_storage);
 }
 
@@ -292,7 +326,7 @@ bool save_commit(save_ctx_t *ctx) {
     uint32_t hashed_data_offset = sizeof(ctx->header.layout) + sizeof(ctx->header.cmac) + sizeof(ctx->header._0x10);
     uint32_t hashed_data_size = sizeof(ctx->header) - hashed_data_offset;
     uint8_t *header = (uint8_t *)&ctx->header;
-    se_calc_sha256(ctx->header.layout.hash, header + hashed_data_offset, hashed_data_size);
+    se_calc_sha256_oneshot(ctx->header.layout.hash, header + hashed_data_offset, hashed_data_size);
 
     se_aes_key_set(10, ctx->save_mac_key, 0x10);
     se_aes_cmac(10, ctx->header.cmac, 0x10, &ctx->header.layout, sizeof(ctx->header.layout));

bdk/libs/nx_savedata/save_data_file.c

@@ -38,7 +38,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 void save_data_file_init(save_data_file_ctx_t *ctx, allocation_table_storage_ctx_t *base_storage, const char *path, hierarchical_save_file_table_ctx_t *file_table, uint64_t size, open_mode_t mode) {
     ctx->mode = mode;
-    memcpy(&ctx->base_storage, base_storage, sizeof(ctx->base_storage));
+    memcpy(&ctx->base_storage, base_storage, sizeof(allocation_table_storage_ctx_t));
     ctx->path = path;
     ctx->file_table = file_table;
     ctx->size = size;

bdk/libs/nx_savedata/save_data_file_system_core.c

@@ -41,21 +41,29 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 #include <gfx_utils.h>
 #include <mem/heap.h>
 
-static ALWAYS_INLINE void save_data_file_system_core_open_fat_storage(save_data_file_system_core_ctx_t *ctx, allocation_table_storage_ctx_t *storage_ctx, uint32_t block_index) {
+static ALWAYS_INLINE bool save_data_file_system_core_open_fat_storage(save_data_file_system_core_ctx_t *ctx, allocation_table_storage_ctx_t *storage_ctx, uint32_t block_index) {
-    save_allocation_table_storage_init(storage_ctx, ctx->base_storage, &ctx->allocation_table, (uint32_t)ctx->header->block_size, block_index);
+    return save_allocation_table_storage_init(storage_ctx, ctx->base_storage, &ctx->allocation_table, (uint32_t)ctx->header->block_size, block_index);
 }
 
-void save_data_file_system_core_init(save_data_file_system_core_ctx_t *ctx, substorage *storage, void *allocation_table, save_fs_header_t *save_fs_header) {
+bool save_data_file_system_core_init(save_data_file_system_core_ctx_t *ctx, substorage *storage, void *allocation_table, save_fs_header_t *save_fs_header) {
     save_allocation_table_init(&ctx->allocation_table, allocation_table, &save_fs_header->fat_header);
     ctx->header = save_fs_header;
     ctx->base_storage = storage;
 
     save_filesystem_list_ctx_t *dir_table = &ctx->file_table.directory_table;
     save_filesystem_list_ctx_t *file_table = &ctx->file_table.file_table;
-    save_data_file_system_core_open_fat_storage(ctx, &dir_table->storage, save_fs_header->fat_header.directory_table_block);
+    if (!save_data_file_system_core_open_fat_storage(ctx, &dir_table->storage, save_fs_header->fat_header.directory_table_block)) {
-    save_data_file_system_core_open_fat_storage(ctx, &file_table->storage, save_fs_header->fat_header.file_table_block);
+        EPRINTF("Failed to init dir table for fs core!");
+        return false;
+    }
+    if (!save_data_file_system_core_open_fat_storage(ctx, &file_table->storage, save_fs_header->fat_header.file_table_block)) {
+        EPRINTF("Failed to init file table for fs core!");
+        return false;
+    }
     save_fs_list_init(dir_table);
     save_fs_list_init(file_table);
+
+    return true;
 }
 
 bool save_data_file_system_core_create_directory(save_data_file_system_core_ctx_t *ctx, const char *path) {

bdk/libs/nx_savedata/save_data_file_system_core.h

@@ -66,7 +66,7 @@ static ALWAYS_INLINE void save_data_file_system_core_get_total_space_size(save_d
     *out_total_space = ctx->header->block_size * ctx->header->block_count;
 }
 
-void save_data_file_system_core_init(save_data_file_system_core_ctx_t *ctx, substorage *storage, void *allocation_table, save_fs_header_t *save_fs_header);
+bool save_data_file_system_core_init(save_data_file_system_core_ctx_t *ctx, substorage *storage, void *allocation_table, save_fs_header_t *save_fs_header);
 
 bool save_data_file_system_core_create_directory(save_data_file_system_core_ctx_t *ctx, const char *path);
 bool save_data_file_system_core_create_file(save_data_file_system_core_ctx_t *ctx, const char *path, uint64_t size);

bdk/libs/nx_savedata/save_fs_list.c

@@ -250,7 +250,7 @@ uint32_t save_fs_list_allocate_entry(save_filesystem_list_ctx_t *ctx) {
     if (capacity == 0 || length >= capacity) {
         uint64_t current_size, new_size;
         save_allocation_table_storage_get_size(&ctx->storage, &current_size);
-        if (!save_allocation_table_storage_set_size(&ctx->storage, current_size + 0x4000))
+        if (!save_allocation_table_storage_set_size(&ctx->storage, current_size + SZ_16K))
             return 0;
         save_allocation_table_storage_get_size(&ctx->storage, &new_size);
         if (!save_fs_list_set_capacity(ctx, (uint32_t)(new_size / sizeof(save_fs_list_entry_t))))

bdk/libs/nx_savedata/save_fs_list.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020 shchmue
+ * Copyright (c) 2019-2022 shchmue
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,

bdk/libs/nx_savedata/storage.c

@@ -45,11 +45,6 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 #include <string.h>
 
-void storage_init(storage *this, const storage_vt *vt, void *ctx) {
-    this->vt = vt;
-    this->ctx = ctx;
-}
-
 void substorage_init(substorage *this, const storage_vt *vt, void *ctx, uint64_t offset, uint64_t length) {
     storage_init(&this->base_storage, vt, ctx);
     this->offset = offset;

bdk/libs/nx_savedata/storage.h

@@ -51,7 +51,10 @@ typedef struct {
     void *ctx;
 } storage;
 
-void storage_init(storage *this, const storage_vt *vt, void *ctx);
+static void ALWAYS_INLINE storage_init(storage *this, const storage_vt *vt, void *ctx) {
+    this->vt = vt;
+    this->ctx = ctx;
+}
 
 typedef struct {
     uint64_t offset;

bdk/mem/emc.h

@@ -72,6 +72,7 @@
 #define EMC_PDEX2MRR                              0xb4
 #define EMC_ODT_WRITE                             0xb0
 #define EMC_WEXT                                  0xb8
+#define EMC_CTT                                   0xBC
 #define EMC_RFC_SLR                               0xc0
 #define EMC_MRS_WAIT_CNT2                         0xc4
 #define EMC_MRS_WAIT_CNT                          0xc8
@@ -86,8 +87,13 @@
 #define EMC_MRR                                   0xec
 #define EMC_CMDQ                                  0xf0
 #define EMC_MC2EMCQ                               0xf4
+#define EMC_FBIO_TWTM                             0xF8
+#define EMC_FBIO_TRATM                            0xFC
+#define EMC_FBIO_TWATM                            0x108
+#define EMC_FBIO_TR2REF                           0x10C
 #define EMC_FBIO_SPARE                            0x100
 #define EMC_FBIO_CFG5                             0x104
+#define EMC_FBIO_CFG6                             0x114
 #define EMC_CFG_RSV                               0x120
 #define EMC_ACPD_CONTROL                          0x124
 #define EMC_MPC                                   0x128
@@ -211,6 +217,7 @@
 #define EMC_AUTO_CAL_CONFIG6                      0x5cc
 #define EMC_AUTO_CAL_CONFIG7                      0x574
 #define EMC_AUTO_CAL_CONFIG8                      0x2dc
+#define EMC_AUTO_CAL_CONFIG9                      0x42C
 #define EMC_AUTO_CAL_VREF_SEL_0                   0x2f8
 #define EMC_AUTO_CAL_VREF_SEL_1                   0x300
 #define EMC_AUTO_CAL_INTERVAL                     0x2a8
@@ -232,7 +239,7 @@
 #define EMC_COMP_PAD_SW_CTRL                      0x57c
 #define EMC_REQ_CTRL                              0x2b0
 #define EMC_EMC_STATUS                            0x2b4
-#define  EMC_STATUS_MRR_DIVLD (1 << 20)
+#define  EMC_STATUS_MRR_DIVLD BIT(20)
 #define EMC_CFG_2                                 0x2b8
 #define EMC_CFG_DIG_DLL                           0x2bc
 #define EMC_CFG_DIG_DLL_PERIOD                    0x2c0
@@ -386,6 +393,8 @@
 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0        0xed4
 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1        0xed8
 #define EMC_TRAINING_DRAMC_TIMING                 0xedc
+#define EMC_PMACRO_DATA_PI_CTRL                   0x110
+#define EMC_PMACRO_CMD_PI_CTRL                    0x114
 #define EMC_PMACRO_QUSE_DDLL_RANK0_0              0x600
 #define EMC_PMACRO_QUSE_DDLL_RANK0_1              0x604
 #define EMC_PMACRO_QUSE_DDLL_RANK0_2              0x608
@@ -650,6 +659,7 @@
 #define EMC_PMACRO_CMD_PAD_TX_CTRL                0xc60
 #define EMC_PMACRO_DATA_PAD_TX_CTRL               0xc64
 #define EMC_PMACRO_COMMON_PAD_TX_CTRL             0xc68
+#define EMC_PMACRO_DSR_VTTGEN_CTRL0               0xC6C
 #define EMC_PMACRO_BRICK_MAPPING_0                0xc80
 #define EMC_PMACRO_BRICK_MAPPING_1                0xc84
 #define EMC_PMACRO_BRICK_MAPPING_2                0xc88
@@ -662,6 +672,24 @@
 #define EMC_PMACRO_DATA_BRICK_CTRL_FDPD           0x31c
 #define EMC_PMACRO_TRAINING_CTRL_0                0xcf8
 #define EMC_PMACRO_TRAINING_CTRL_1                0xcfc
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_0             0xD40
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_1             0xD44
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_2             0xD48
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_3             0xD4C
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_4             0xD50
+#define EMC_PMACRO_PERBIT_FGCG_CTRL_5             0xD54
+#define EMC_PMACRO_PERBIT_RFU_CTRL_0              0xD60
+#define EMC_PMACRO_PERBIT_RFU_CTRL_1              0xD64
+#define EMC_PMACRO_PERBIT_RFU_CTRL_2              0xD68
+#define EMC_PMACRO_PERBIT_RFU_CTRL_3              0xD6C
+#define EMC_PMACRO_PERBIT_RFU_CTRL_4              0xD70
+#define EMC_PMACRO_PERBIT_RFU_CTRL_5              0xD74
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_0             0xD80
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_1             0xD84
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_2             0xD88
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_3             0xD8C
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_4             0xD90
+#define EMC_PMACRO_PERBIT_RFU1_CTRL_5             0xD94
 #define EMC_PMC_SCRATCH1                          0x440
 #define EMC_PMC_SCRATCH2                          0x444
 #define EMC_PMC_SCRATCH3                          0x448
@@ -684,10 +712,13 @@ enum
 
 typedef struct _emc_mr_data_t
 {
-	u8 dev0_ch0;
+	// Device 0.
-	u8 dev0_ch1;
+	u8 rank0_ch0;
-	u8 dev1_ch0;
+	u8 rank0_ch1;
-	u8 dev1_ch1;
+
+	// Device 1.
+	u8 rank1_ch0;
+	u8 rank1_ch1;
 } emc_mr_data_t;
 
 #endif

bdk/mem/mc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -15,11 +15,14 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <memory_map.h>
 #include <mem/mc.h>
 #include <soc/t210.h>
 #include <soc/clock.h>
 #include <utils/util.h>
 
+//#define CONFIG_ENABLE_AHB_REDIRECT
+
 void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)
 {
 	MC(MC_SEC_CARVEOUT_BOM) = bom;
@@ -122,13 +125,13 @@ void mc_config_carveout()
 	MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
 }
 
-void mc_enable_ahb_redirect()
+void mc_enable_ahb_redirect(bool full_aperture)
 {
 	// Enable ARC_CLK_OVR_ON.
 	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000;
 	//MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE;
 	MC(MC_IRAM_BOM) = 0x40000000;
-	MC(MC_IRAM_TOM) = 0x4003F000;
+	MC(MC_IRAM_TOM) = full_aperture ? DRAM_START : 0x4003F000;
 }
 
 void mc_disable_ahb_redirect()
@@ -143,18 +146,19 @@ void mc_disable_ahb_redirect()
 
 void mc_enable()
 {
+	// Reset EMC source to PLLP.
 	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000;
-	// Enable EMC clock.
+	// Enable memory clocks.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF) | 0x2000000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC);
-	// Enable MC clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MEM);
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE) | 1;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL);
-	// Enable EMC DLL clock.
+	// Clear clock resets for memory.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001; //Clear EMC and MC reset.
 	usleep(5);
 
-	//#ifdef CONFIG_ENABLE_AHB_REDIRECT
+#ifdef CONFIG_ENABLE_AHB_REDIRECT
+	mc_enable_ahb_redirect();
+#else
 	mc_disable_ahb_redirect();
-	//mc_enable_ahb_redirect();
+#endif
-	//#endif
 }

bdk/mem/mc.h

@@ -23,7 +23,7 @@
 void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock);
 void mc_config_carveout();
 void mc_config_carveout_finalize();
-void mc_enable_ahb_redirect();
+void mc_enable_ahb_redirect(bool full_aperture);
 void mc_disable_ahb_redirect();
 void mc_enable();
 

bdk/mem/mc_t210.h

@@ -461,6 +461,7 @@
 #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1                    0xc6c
 #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0                    0xd08
 #define MC_ERR_APB_ASID_UPDATE_STATUS                           0x9d0
+#define MC_UNTRANSLATED_REGION_CHECK                            0x948
 #define MC_DA_CONFIG0                                           0x9dc
 
 // MC_SECURITY_CARVEOUTX_CFG0
@@ -503,14 +504,14 @@
 #define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L2 (4 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
 #define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L3 (8 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
 
-#define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU (1 << 22)
+#define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU BIT(22)
 
-#define SEC_CARVEOUT_CFG_TZ_GLOBAL_WR_EN_BYPASS_CHECK (1 << 23)
+#define SEC_CARVEOUT_CFG_TZ_GLOBAL_WR_EN_BYPASS_CHECK BIT(23)
-#define SEC_CARVEOUT_CFG_TZ_GLOBAL_RD_EN_BYPASS_CHECK (1 << 24)
+#define SEC_CARVEOUT_CFG_TZ_GLOBAL_RD_EN_BYPASS_CHECK BIT(24)
 
-#define SEC_CARVEOUT_CFG_ALLOW_APERTURE_ID_MISMATCH (1 << 25)
+#define SEC_CARVEOUT_CFG_ALLOW_APERTURE_ID_MISMATCH BIT(25)
-#define SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH    (1 << 26)
+#define SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH    BIT(26)
 
-#define SEC_CARVEOUT_CFG_IS_WPR (1 << 27)
+#define SEC_CARVEOUT_CFG_IS_WPR BIT(27)
 
 #endif

bdk/mem/minerva.c

@@ -23,6 +23,7 @@
 #include <ianos/ianos.h>
 #include <soc/clock.h>
 #include <soc/fuse.h>
+#include <soc/hw_init.h>
 #include <soc/t210.h>
 #include <utils/util.h>
 
@@ -37,6 +38,10 @@ u32 minerva_init()
 	minerva_cfg = NULL;
 	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
 
+	//!TODO: Not supported on T210B01 yet.
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
+		return 0;
+
 #ifdef NYX
 	// Set table to nyx storage.
 	mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
@@ -48,14 +53,14 @@ u32 minerva_init()
 		u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
 		minerva_cfg = (void *)ep_addr;
 
-		return 0;
+		return !minerva_cfg ? 1 : 0;
 	}
 	else
 	{
 		mtc_config_t mtc_tmp;
 
 		mtc_tmp.mtc_table = mtc_cfg->mtc_table;
-		mtc_tmp.sdram_id = (fuse_read_odm(4) >> 3) & 0x1F;
+		mtc_tmp.sdram_id  = fuse_read_dramid(false);
 		mtc_tmp.init_done = MTC_NEW_MAGIC;
 
 		u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)&mtc_tmp);
@@ -76,7 +81,7 @@ u32 minerva_init()
 	// Set table to nyx storage.
 	mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
 
-	mtc_cfg->sdram_id = (fuse_read_odm(4) >> 3) & 0x1F;
+	mtc_cfg->sdram_id  = fuse_read_dramid(false);
 	mtc_cfg->init_done = MTC_NEW_MAGIC; // Initialize mtc table.
 
 	u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
@@ -99,21 +104,21 @@ u32 minerva_init()
 	}
 
 	mtc_cfg->rate_from = mtc_cfg->mtc_table[curr_ram_idx].rate_khz;
-	mtc_cfg->rate_to = 204000;
+	mtc_cfg->rate_to = FREQ_204;
 	mtc_cfg->train_mode = OP_TRAIN;
 	minerva_cfg(mtc_cfg, NULL);
-	mtc_cfg->rate_to = 800000;
+	mtc_cfg->rate_to = FREQ_800;
 	minerva_cfg(mtc_cfg, NULL);
-	mtc_cfg->rate_to = 1600000;
+	mtc_cfg->rate_to = FREQ_1600;
 	minerva_cfg(mtc_cfg, NULL);
 
 	// FSP WAR.
 	mtc_cfg->train_mode = OP_SWITCH;
-	mtc_cfg->rate_to = 800000;
+	mtc_cfg->rate_to = FREQ_800;
 	minerva_cfg(mtc_cfg, NULL);
 
 	// Switch to max.
-	mtc_cfg->rate_to = 1600000;
+	mtc_cfg->rate_to = FREQ_1600;
 	minerva_cfg(mtc_cfg, NULL);
 
 	return 0;
@@ -124,6 +129,7 @@ void minerva_change_freq(minerva_freq_t freq)
 	if (!minerva_cfg)
 		return;
 
+	// Check if requested frequency is different. Do not allow otherwise because it will hang.
 	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
 	if (mtc_cfg->rate_from != freq)
 	{
@@ -133,6 +139,23 @@ void minerva_change_freq(minerva_freq_t freq)
 	}
 }
 
+void minerva_prep_boot_freq()
+{
+	if (!minerva_cfg)
+		return;
+
+	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
+
+	// Check if there's RAM OC. If not exit.
+	if (mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600)
+		return;
+
+	// FSP WAR.
+	minerva_change_freq(FREQ_204);
+	// Scale down to 800 MHz boot freq.
+	minerva_change_freq(FREQ_800);
+}
+
 void minerva_periodic_training()
 {
 	if (!minerva_cfg)

bdk/mem/minerva.h

@@ -27,8 +27,8 @@
 
 typedef struct
 {
-	s32 rate_to;
+	u32 rate_to;
-	s32 rate_from;
+	u32 rate_from;
 	emc_table_t *mtc_table;
 	u32 table_entries;
 	emc_table_t *current_emc_table;
@@ -60,6 +60,7 @@ typedef enum
 extern void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
 u32  minerva_init();
 void minerva_change_freq(minerva_freq_t freq);
+void minerva_prep_boot_freq();
 void minerva_periodic_training();
 
 #endif

bdk/mem/sdram.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 balika011
- * Copyright (c) 2019-2020 CTCaer
+ * Copyright (c) 2019-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -20,12 +20,15 @@
 
 #include <mem/mc.h>
 #include <mem/emc.h>
+#include <mem/sdram.h>
 #include <mem/sdram_param_t210.h>
+#include <mem/sdram_param_t210b01.h>
 #include <memory_map.h>
 #include <power/max77620.h>
 #include <power/max7762x.h>
 #include <soc/clock.h>
 #include <soc/fuse.h>
+#include <soc/hw_init.h>
 #include <soc/i2c.h>
 #include <soc/pmc.h>
 #include <soc/t210.h>
@@ -33,17 +36,47 @@
 
 #define CONFIG_SDRAM_KEEP_ALIVE
 
-#ifdef CONFIG_SDRAM_COMPRESS_CFG
+typedef struct _sdram_vendor_patch_t
-#include <libs/compr/lz.h>
-#include "sdram_config_lz.inl"
-#else
-#include "sdram_config.inl"
-#endif
-
-static u32 _get_sdram_id()
 {
-	return ((fuse_read_odm(4) & 0xF8) >> 3);
+	u32 val;
-}
+	u32 offset:16;
+	u32 dramcf:16;
+} sdram_vendor_patch_t;
+
+static const u8 dram_encoding_t210b01[] = {
+	LPDDR4X_UNUSED,
+	LPDDR4X_UNUSED,
+	LPDDR4X_UNUSED,
+	LPDDR4X_4GB_HYNIX_1Y_A,
+	LPDDR4X_UNUSED,
+	LPDDR4X_4GB_HYNIX_1Y_A,
+	LPDDR4X_4GB_HYNIX_1Y_A,
+	LPDDR4X_4GB_SAMSUNG_X1X2,
+	LPDDR4X_NO_PATCH,
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ,
+	LPDDR4X_NO_PATCH,
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE,
+	LPDDR4X_NO_PATCH,
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ,
+	LPDDR4X_NO_PATCH,
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE,
+	LPDDR4X_4GB_SAMSUNG_Y,
+	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
+	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
+	LPDDR4X_4GB_SAMSUNG_1Y_Y,
+	LPDDR4X_8GB_SAMSUNG_1Y_Y,
+	LPDDR4X_UNUSED, // Removed.
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
+	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
+};
+
+#include "sdram_config.inl"
+#include "sdram_config_t210b01.inl"
 
 static bool _sdram_wait_emc_status(u32 reg_offset, u32 bit_mask, bool updated_state, s32 emc_channel)
 {
@@ -85,17 +118,26 @@ static void _sdram_req_mrr_data(u32 data, bool dual_channel)
 emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
 {
 	emc_mr_data_t data;
-	_sdram_req_mrr_data((1 << 31) | (mrx << 16), EMC_CHAN0);
+
-	data.dev0_ch0 = EMC(EMC_MRR) & 0xFF;
+	/*
-	data.dev0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
+	 * When a dram chip has only one rank, then the info from the 2 ranks differs.
-	_sdram_req_mrr_data((1 << 30) | (mrx << 16), EMC_CHAN1);
+	 * Info not matching is only allowed on different channels.
-	data.dev1_ch0 = EMC(EMC_MRR) & 0xFF;
+	 */
-	data.dev1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
+
+	// Get Device 0 (Rank 0) info from both dram chips (channels).
+	_sdram_req_mrr_data(BIT(31) | (mrx << 16), EMC_CHAN0);
+	data.rank0_ch0 = EMC(EMC_MRR) & 0xFF;
+	data.rank0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
+
+	// Get Device 1 (Rank 1) info from both dram chips (channels).
+	_sdram_req_mrr_data(BIT(30) | (mrx << 16), EMC_CHAN1);
+	data.rank1_ch0 = EMC(EMC_MRR) & 0xFF;
+	data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
 
 	return data;
 }
 
-static void _sdram_config(const sdram_params_t *params)
+static void _sdram_config_t210(const sdram_params_t210_t *params)
 {
 	// Program DPD3/DPD4 regs (coldboot path).
 	// Enable sel_dpd on unused pins.
@@ -143,9 +185,10 @@ break_nosleep:
 	if (params->clear_clock2_mc1)
 		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000; // Clear Reset to MC1.
 
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x2000001; // Enable EMC and MEM clocks.
+	// Enable and clear reset for memory clocks.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x4000;    // Enable EMC_DLL clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001; // Clear EMC and MEM resets.
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
 
 	// Set pad macros.
 	EMC(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0;
@@ -540,7 +583,7 @@ break_nosleep:
 	EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000;
 
 	// Patch BootROM.
-	if (params->boot_rom_patch_control & (1 << 31))
+	if (params->boot_rom_patch_control & BIT(31))
 	{
 		*(vu32 *)(APB_MISC_BASE + params->boot_rom_patch_control * 4) = params->boot_rom_patch_data;
 		MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update.
@@ -695,47 +738,678 @@ break_nosleep:
 	MC(MC_EMEM_CFG_ACCESS_CTRL) = 1;
 }
 
-#ifndef CONFIG_SDRAM_COMPRESS_CFG
+static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
-static void _sdram_patch_model_params(u32 dramid, u32 *params)
 {
-	for (u32 i = 0; i < sizeof(sdram_cfg_vendor_patches) / sizeof(sdram_vendor_patch_t); i++)
+	u32 pmc_scratch1 = ~params->emc_pmc_scratch1;
-		if (sdram_cfg_vendor_patches[i].dramid & DRAM_ID(dramid))
+	u32 pmc_scratch2 = ~params->emc_pmc_scratch2;
-			params[sdram_cfg_vendor_patches[i].addr] = sdram_cfg_vendor_patches[i].val;
-}
-#endif
 
-sdram_params_t *sdram_get_params()
+	// Override HW FSM if needed.
+	if (params->clk_rst_pllm_misc20_override_enable)
+		CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = params->clk_rst_pllm_misc20_override;
+
+	// Program DPD3/DPD4 regs (coldboot path).
+	// Enable sel_dpd on unused pins.
+	PMC(APBDEV_PMC_WEAK_BIAS) = (pmc_scratch1 & 0x1000) << 19 | (pmc_scratch1 & 0xFFF) << 18 | (pmc_scratch1 & 0x8000) << 15;
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) + 0x80000000;
+	usleep(params->pmc_io_dpd3_req_wait);
+
+	// Disable e_dpd_vttgen.
+	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x3FFF0000) | 0x80000000;
+	usleep(params->pmc_io_dpd4_req_wait);
+
+	// Disable e_dpd_bg.
+	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x1FFF) | 0x80000000;
+	usleep(1);
+
+	// Program CMD mapping. Required before brick mapping, else
+	// we can't guarantee CK will be differential at all times.
+	EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7;
+	EMC(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0;
+	EMC(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1;
+	EMC(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2;
+	EMC(EMC_CMD_MAPPING_CMD1_0) = params->emc_cmd_mapping_cmd1_0;
+	EMC(EMC_CMD_MAPPING_CMD1_1) = params->emc_cmd_mapping_cmd1_1;
+	EMC(EMC_CMD_MAPPING_CMD1_2) = params->emc_cmd_mapping_cmd1_2;
+	EMC(EMC_CMD_MAPPING_CMD2_0) = params->emc_cmd_mapping_cmd2_0;
+	EMC(EMC_CMD_MAPPING_CMD2_1) = params->emc_cmd_mapping_cmd2_1;
+	EMC(EMC_CMD_MAPPING_CMD2_2) = params->emc_cmd_mapping_cmd2_2;
+	EMC(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0;
+	EMC(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1;
+	EMC(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2;
+	EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte;
+
+	// Program brick mapping.
+	EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0;
+	EMC(EMC_PMACRO_BRICK_MAPPING_1) = params->emc_pmacro_brick_mapping1;
+	EMC(EMC_PMACRO_BRICK_MAPPING_2) = params->emc_pmacro_brick_mapping2;
+
+	// Set pad macros.
+	EMC(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0;
+	EMC(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1;
+	EMC(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2;
+
+	// Set pad macros bias.
+	EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0;
+
+	// Patch 1 to 3 using BCT spare secure variables.
+	if (params->emc_bct_spare_secure0)
+		*(vu32 *)params->emc_bct_spare_secure0 = params->emc_bct_spare_secure1;
+	if (params->emc_bct_spare_secure2)
+		*(vu32 *)params->emc_bct_spare_secure2 = params->emc_bct_spare_secure3;
+	if (params->emc_bct_spare_secure4)
+		*(vu32 *)params->emc_bct_spare_secure4 = params->emc_bct_spare_secure5;
+
+	EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place.
+	usleep(params->pmc_vddp_sel_wait + 2); // Ensure the regulators settle.
+
+	// Set clock sources.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = params->emc_clock_source;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll;
+
+	// Select EMC write mux.
+	EMC(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg;
+
+	// Patch 2 using BCT spare variables.
+	if (params->emc_bct_spare2)
+		*(vu32 *)params->emc_bct_spare2 = params->emc_bct_spare3;
+
+	// This is required to do any reads from the pad macros.
+	EMC(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay;
+
+	EMC(EMC_FBIO_CFG8) = params->emc_fbio_cfg8;
+
+	// Set swizzle for Rank 0.
+	EMC(EMC_SWIZZLE_RANK0_BYTE0) = params->emc_swizzle_rank0_byte0;
+	EMC(EMC_SWIZZLE_RANK0_BYTE1) = params->emc_swizzle_rank0_byte1;
+	EMC(EMC_SWIZZLE_RANK0_BYTE2) = params->emc_swizzle_rank0_byte2;
+	EMC(EMC_SWIZZLE_RANK0_BYTE3) = params->emc_swizzle_rank0_byte3;
+	// Set swizzle for Rank 1.
+	EMC(EMC_SWIZZLE_RANK1_BYTE0) = params->emc_swizzle_rank1_byte0;
+	EMC(EMC_SWIZZLE_RANK1_BYTE1) = params->emc_swizzle_rank1_byte1;
+	EMC(EMC_SWIZZLE_RANK1_BYTE2) = params->emc_swizzle_rank1_byte2;
+	EMC(EMC_SWIZZLE_RANK1_BYTE3) = params->emc_swizzle_rank1_byte3;
+
+	// Patch 3 using BCT spare variables.
+	if (params->emc_bct_spare6)
+		*(vu32 *)params->emc_bct_spare6 = params->emc_bct_spare7;
+
+	// Set pad controls.
+	EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl;
+	EMC(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2;
+	EMC(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3;
+
+	// Program Autocal controls with shadowed register fields.
+	EMC(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2;
+	EMC(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3;
+	EMC(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4;
+	EMC(EMC_AUTO_CAL_CONFIG5) = params->emc_auto_cal_config5;
+	EMC(EMC_AUTO_CAL_CONFIG6) = params->emc_auto_cal_config6;
+	EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7;
+	EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8;
+
+	EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term;
+	EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive;
+	EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive;
+	EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive;
+	EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common;
+	EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel;
+	EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl;
+
+	EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0;
+	EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1;
+	EMC(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1;
+
+	EMC(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0;
+	EMC(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1;
+	EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0;
+	EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1;
+	EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0;
+	EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1;
+	EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2;
+	EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3;
+	EMC(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0;
+	EMC(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1;
+	EMC(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2;
+	EMC(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3;
+
+	EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1;
+	EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl;
+
+	EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd;
+	EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2;
+	EMC(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd;
+	EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl;
+	EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl;
+	EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl;
+	EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode;
+	EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode;
+	EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl & 0xEFFFFFFF;
+
+	EMC(EMC_CFG_3) = params->emc_cfg3;
+	EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0;
+	EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1;
+	EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2;
+	EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3;
+	EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4;
+	EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5;
+	EMC(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0;
+	EMC(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1;
+	EMC(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2;
+	EMC(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3;
+	EMC(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4;
+	EMC(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5;
+
+	// Program per bit pad macros.
+	EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_0) = params->emc_pmacro_perbit_fgcg_ctrl0;
+	EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_1) = params->emc_pmacro_perbit_fgcg_ctrl1;
+	EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_2) = params->emc_pmacro_perbit_fgcg_ctrl2;
+	EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_3) = params->emc_pmacro_perbit_fgcg_ctrl3;
+	EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_4) = params->emc_pmacro_perbit_fgcg_ctrl4;
+	EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_5) = params->emc_pmacro_perbit_fgcg_ctrl5;
+	EMC(EMC_PMACRO_PERBIT_RFU_CTRL_0) = params->emc_pmacro_perbit_rfu_ctrl0;
+	EMC(EMC_PMACRO_PERBIT_RFU_CTRL_1) = params->emc_pmacro_perbit_rfu_ctrl1;
+	EMC(EMC_PMACRO_PERBIT_RFU_CTRL_2) = params->emc_pmacro_perbit_rfu_ctrl2;
+	EMC(EMC_PMACRO_PERBIT_RFU_CTRL_3) = params->emc_pmacro_perbit_rfu_ctrl3;
+	EMC(EMC_PMACRO_PERBIT_RFU_CTRL_4) = params->emc_pmacro_perbit_rfu_ctrl4;
+	EMC(EMC_PMACRO_PERBIT_RFU_CTRL_5) = params->emc_pmacro_perbit_rfu_ctrl5;
+	EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_0) = params->emc_pmacro_perbit_rfu1_ctrl0;
+	EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_1) = params->emc_pmacro_perbit_rfu1_ctrl1;
+	EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_2) = params->emc_pmacro_perbit_rfu1_ctrl2;
+	EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_3) = params->emc_pmacro_perbit_rfu1_ctrl3;
+	EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_4) = params->emc_pmacro_perbit_rfu1_ctrl4;
+	EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_5) = params->emc_pmacro_perbit_rfu1_ctrl5;
+	EMC(EMC_PMACRO_DATA_PI_CTRL) = params->emc_pmacro_data_pi_ctrl;
+	EMC(EMC_PMACRO_CMD_PI_CTRL) = params->emc_pmacro_cmd_pi_ctrl;
+
+	EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass;
+	EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0;
+	EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1;
+	EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2;
+	EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0;
+	EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1;
+	EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2;
+	EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0;
+	EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1;
+	EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0;
+	EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1;
+	EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt;
+
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->emc_pmacro_quse_ddll_rank0_3;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->emc_pmacro_quse_ddll_rank0_4;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->emc_pmacro_quse_ddll_rank0_5;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->emc_pmacro_quse_ddll_rank1_0;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->emc_pmacro_quse_ddll_rank1_1;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->emc_pmacro_quse_ddll_rank1_2;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4;
+	EMC(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5;
+
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->emc_pmacro_ob_ddll_long_dq_rank0_3;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->emc_pmacro_ob_ddll_long_dq_rank0_4;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->emc_pmacro_ob_ddll_long_dq_rank0_5;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->emc_pmacro_ob_ddll_long_dq_rank1_0;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->emc_pmacro_ob_ddll_long_dq_rank1_1;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->emc_pmacro_ob_ddll_long_dq_rank1_2;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->emc_pmacro_ob_ddll_long_dq_rank1_3;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->emc_pmacro_ob_ddll_long_dq_rank1_4;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->emc_pmacro_ob_ddll_long_dq_rank1_5;
+
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ob_ddll_long_dqs_rank0_0;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ob_ddll_long_dqs_rank0_1;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ob_ddll_long_dqs_rank0_2;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ob_ddll_long_dqs_rank0_3;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->emc_pmacro_ob_ddll_long_dqs_rank0_4;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->emc_pmacro_ob_ddll_long_dqs_rank0_5;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ob_ddll_long_dqs_rank1_0;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ob_ddll_long_dqs_rank1_1;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ob_ddll_long_dqs_rank1_2;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ob_ddll_long_dqs_rank1_3;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->emc_pmacro_ob_ddll_long_dqs_rank1_4;
+	EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->emc_pmacro_ob_ddll_long_dqs_rank1_5;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ib_ddll_long_dqs_rank0_0;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ib_ddll_long_dqs_rank0_1;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ib_ddll_long_dqs_rank0_2;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ib_ddll_long_dqs_rank0_3;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ib_ddll_long_dqs_rank1_0;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ib_ddll_long_dqs_rank1_1;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2;
+	EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3;
+
+	EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0;
+	EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1;
+	EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2;
+	EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3;
+	EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4;
+	EMC(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0;
+	EMC(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1;
+	EMC(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2;
+
+	// Set DLL periodic offset.
+	EMC(EMC_PMACRO_DDLL_PERIODIC_OFFSET) = params->emc_pmacro_ddll_periodic_offset;
+
+	// Patch 4 using BCT spare variables.
+	if (params->emc_bct_spare4)
+		*(vu32 *)params->emc_bct_spare4 = params->emc_bct_spare5;
+
+	// Patch 4 to 6 using BCT spare secure variables.
+	if (params->emc_bct_spare_secure6)
+		*(vu32 *)params->emc_bct_spare_secure6 = params->emc_bct_spare_secure7;
+	if (params->emc_bct_spare_secure8)
+		*(vu32 *)params->emc_bct_spare_secure8 = params->emc_bct_spare_secure9;
+	if (params->emc_bct_spare_secure10)
+		*(vu32 *)params->emc_bct_spare_secure10 = params->emc_bct_spare_secure11;
+
+	EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place.
+
+	// Initialize MC VPR settings.
+	MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom;
+	MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi;
+	MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb;
+	MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override;
+	MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1;
+	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0;
+	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1;
+
+	// Program SDRAM geometry parameters.
+	MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg;
+	MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0;
+	MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1;
+	MC(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask;
+
+	// Program bank swizzling.
+	MC(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->mc_emem_adr_cfg_bank_mask0;
+	MC(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->mc_emem_adr_cfg_bank_mask1;
+	MC(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->mc_emem_adr_cfg_bank_mask2;
+
+	// Program external memory aperture (base and size).
+	MC(MC_EMEM_CFG) = params->mc_emem_cfg;
+
+	// Program SEC carveout (base and size).
+	MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom;
+	MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi;
+	MC(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb;
+
+	// Program MTS carveout (base and size).
+	MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom;
+	MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi;
+	MC(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb;
+
+	// Program the memory arbiter.
+	MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg;
+	MC(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req;
+	MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl;
+	MC(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl;
+	MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd;
+	MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp;
+	MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc;
+	MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras;
+	MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw;
+	MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd;
+	MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre;
+	MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre;
+	MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r;
+	MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w;
+	MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw;
+	MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w;
+	MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r;
+	MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb;
+	MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns;
+	MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers;
+	MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0;
+	MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1;
+	MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2;
+	MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle;
+	MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override;
+	MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1;
+	MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv;
+	MC(MC_DA_CONFIG0) = params->mc_da_cfg0;
+
+	MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update.
+
+	// Program second-level clock enable overrides.
+	MC(MC_CLKEN_OVERRIDE) = params->mc_clken_override;
+
+	// Program statistics gathering.
+	MC(MC_STAT_CONTROL) = params->mc_stat_control;
+
+	// Program SDRAM geometry parameters.
+	EMC(EMC_ADR_CFG) = params->emc_adr_cfg;
+
+	// Program second-level clock enable overrides.
+	EMC(EMC_CLKEN_OVERRIDE) = params->emc_clken_override;
+
+	// Program EMC pad auto calibration.
+	EMC(EMC_PMACRO_AUTOCAL_CFG_0) = params->emc_pmacro_auto_cal_cfg0;
+	EMC(EMC_PMACRO_AUTOCAL_CFG_1) = params->emc_pmacro_auto_cal_cfg1;
+	EMC(EMC_PMACRO_AUTOCAL_CFG_2) = params->emc_pmacro_auto_cal_cfg2;
+
+	EMC(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0;
+	EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1;
+
+	EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval;
+	EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config;
+	usleep(params->emc_auto_cal_wait);
+
+	// Patch 5 using BCT spare variables.
+	if (params->emc_bct_spare8)
+		*(vu32 *)params->emc_bct_spare8 = params->emc_bct_spare9;
+
+	EMC(EMC_AUTO_CAL_CONFIG9) = params->emc_auto_cal_config9;
+
+	// Program EMC timing configuration.
+	EMC(EMC_CFG_2) = params->emc_cfg2;
+	EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe;
+	EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1;
+	EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2;
+	EMC(EMC_CMDQ) = params->emc_cmd_q;
+	EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q;
+	EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt;
+	EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2;
+	EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5;
+	EMC(EMC_RC) = params->emc_rc;
+	EMC(EMC_RFC) = params->emc_rfc;
+	EMC(EMC_RFCPB) = params->emc_rfc_pb;
+	EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2;
+	EMC(EMC_RFC_SLR) = params->emc_rfc_slr;
+	EMC(EMC_RAS) = params->emc_ras;
+	EMC(EMC_RP) = params->emc_rp;
+	EMC(EMC_TPPD) = params->emc_tppd;
+	EMC(EMC_CTT) = params->emc_trtm;
+	EMC(EMC_FBIO_TWTM) = params->emc_twtm;
+	EMC(EMC_FBIO_TRATM) = params->emc_tratm;
+	EMC(EMC_FBIO_TWATM) = params->emc_twatm;
+	EMC(EMC_FBIO_TR2REF) = params->emc_tr2ref;
+	EMC(EMC_R2R) = params->emc_r2r;
+	EMC(EMC_W2W) = params->emc_w2w;
+	EMC(EMC_R2W) = params->emc_r2w;
+	EMC(EMC_W2R) = params->emc_w2r;
+	EMC(EMC_R2P) = params->emc_r2p;
+	EMC(EMC_W2P) = params->emc_w2p;
+	EMC(EMC_CCDMW) = params->emc_ccdmw;
+	EMC(EMC_RD_RCD) = params->emc_rd_rcd;
+	EMC(EMC_WR_RCD) = params->emc_wr_rcd;
+	EMC(EMC_RRD) = params->emc_rrd;
+	EMC(EMC_REXT) = params->emc_rext;
+	EMC(EMC_WEXT) = params->emc_wext;
+	EMC(EMC_WDV) = params->emc_wdv;
+	EMC(EMC_WDV_CHK) = params->emc_wdv_chk;
+	EMC(EMC_WSV) = params->emc_wsv;
+	EMC(EMC_WEV) = params->emc_wev;
+	EMC(EMC_WDV_MASK) = params->emc_wdv_mask;
+	EMC(EMC_WS_DURATION) = params->emc_ws_duration;
+	EMC(EMC_WE_DURATION) = params->emc_we_duration;
+	EMC(EMC_QUSE) = params->emc_quse;
+	EMC(EMC_QUSE_WIDTH) = params->emc_quse_width;
+	EMC(EMC_IBDLY) = params->emc_ibdly;
+	EMC(EMC_OBDLY) = params->emc_obdly;
+	EMC(EMC_EINPUT) = params->emc_einput;
+	EMC(EMC_EINPUT_DURATION) = params->emc_einput_duration;
+	EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra;
+	EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width;
+	EMC(EMC_DBG) = params->emc_dbg;
+	EMC(EMC_QRST) = params->emc_qrst;
+	EMC(EMC_ISSUE_QRST) = 1;
+	EMC(EMC_ISSUE_QRST) = 0;
+	EMC(EMC_QSAFE) = params->emc_qsafe;
+	EMC(EMC_RDV) = params->emc_rdv;
+	EMC(EMC_RDV_MASK) = params->emc_rdv_mask;
+	EMC(EMC_RDV_EARLY) = params->emc_rdv_early;
+	EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask;
+	EMC(EMC_QPOP) = params->emc_qpop;
+	EMC(EMC_REFRESH) = params->emc_refresh;
+	EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num;
+	EMC(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt;
+	EMC(EMC_PDEX2WR) = params->emc_pdex2wr;
+	EMC(EMC_PDEX2RD) = params->emc_pdex2rd;
+	EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden;
+	EMC(EMC_ACT2PDEN) = params->emc_act2pden;
+	EMC(EMC_AR2PDEN) = params->emc_ar2pden;
+	EMC(EMC_RW2PDEN) = params->emc_rw2pden;
+	EMC(EMC_CKE2PDEN) = params->emc_cke2pden;
+	EMC(EMC_PDEX2CKE) = params->emc_pdex2che;
+	EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr;
+	EMC(EMC_TXSR) = params->emc_txsr;
+	EMC(EMC_TXSRDLL) = params->emc_txsr_dll;
+	EMC(EMC_TCKE) = params->emc_tcke;
+	EMC(EMC_TCKESR) = params->emc_tckesr;
+	EMC(EMC_TPD) = params->emc_tpd;
+	EMC(EMC_TFAW) = params->emc_tfaw;
+	EMC(EMC_TRPAB) = params->emc_trpab;
+	EMC(EMC_TCLKSTABLE) = params->emc_tclkstable;
+	EMC(EMC_TCLKSTOP) = params->emc_tclkstop;
+	EMC(EMC_TREFBW) = params->emc_trefbw;
+	EMC(EMC_ODT_WRITE) = params->emc_odt_write;
+	EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll;
+	EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period;
+
+	// Don't write CFG_ADR_EN (bit 1) here - lock bit written later.
+	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD;
+	EMC(EMC_CFG_RSV) = params->emc_cfg_rsv;
+	EMC(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1;
+	EMC(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2;
+	EMC(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3;
+	EMC(EMC_ACPD_CONTROL) = params->emc_acpd_control;
+	EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen;
+	EMC(EMC_PMACRO_DSR_VTTGEN_CTRL0) = params->emc_pmacro_dsr_vttgen_ctrl0;
+
+	// Set pipe bypass enable bits before sending any DRAM commands.
+	EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000;
+
+	// BootROM patching is used as a generic patch here.
+	if (params->boot_rom_patch_control)
+	{
+		*(vu32 *)params->boot_rom_patch_control = params->boot_rom_patch_data;
+		MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update.
+	}
+
+	// Patch 7 to 9 using BCT spare secure variables.
+	if (params->emc_bct_spare_secure12)
+		*(vu32 *)params->emc_bct_spare_secure12 = params->emc_bct_spare_secure13;
+	if (params->emc_bct_spare_secure14)
+		*(vu32 *)params->emc_bct_spare_secure14 = params->emc_bct_spare_secure15;
+	if (params->emc_bct_spare_secure16)
+		*(vu32 *)params->emc_bct_spare_secure16 = params->emc_bct_spare_secure17;
+
+	// Release SEL_DPD_CMD.
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = ((params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000;
+	usleep(params->pmc_io_dpd3_req_wait);
+
+	// Set transmission pad control parameters.
+	EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl;
+
+	// ZQ CAL setup (not actually issuing ZQ CAL now).
+	if (params->emc_zcal_warm_cold_boot_enables & 1)
+	{
+		if (params->memory_type == MEMORY_TYPE_DDR3L)
+			EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt << 3;
+		if (params->memory_type == MEMORY_TYPE_LPDDR4)
+		{
+			EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
+			EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd;
+		}
+	}
+
+	EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place.
+	usleep(params->emc_timing_control_wait);
+
+	// Deassert HOLD_CKE_LOW.
+	PMC(APBDEV_PMC_DDR_CNTRL) &= 0xFF78007F;
+	usleep(params->pmc_ddr_ctrl_wait);
+
+	// Set clock enable signal.
+	u32 pin_gpio_cfg = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12);
+	if (params->memory_type == MEMORY_TYPE_DDR3L || params->memory_type == MEMORY_TYPE_LPDDR4)
+	{
+		EMC(EMC_PIN) = pin_gpio_cfg;
+		(void)EMC(EMC_PIN);
+		usleep(params->emc_pin_extra_wait + 200);
+		EMC(EMC_PIN) = pin_gpio_cfg | 0x100;
+		(void)EMC(EMC_PIN);
+	}
+
+	if (params->memory_type == MEMORY_TYPE_LPDDR4)
+		usleep(params->emc_pin_extra_wait + 2000);
+	else if (params->memory_type == MEMORY_TYPE_DDR3L)
+		usleep(params->emc_pin_extra_wait + 500);
+
+	// Enable clock enable signal.
+	EMC(EMC_PIN) = pin_gpio_cfg | 0x101;
+	(void)EMC(EMC_PIN);
+	usleep(params->emc_pin_program_wait);
+
+	// Send NOP (trigger just needs to be non-zero).
+	if (params->memory_type != MEMORY_TYPE_LPDDR4)
+		EMC(EMC_NOP) = (params->emc_dev_select << 30) + 1;
+
+	// On coldboot w/LPDDR2/3, wait 200 uSec after asserting CKE high.
+	if (params->memory_type == MEMORY_TYPE_LPDDR2)
+		usleep(params->emc_pin_extra_wait + 200);
+
+	// Init zq calibration,
+	if (params->memory_type == MEMORY_TYPE_LPDDR4)
+	{
+		// Patch 6 using BCT spare variables.
+		if (params->emc_bct_spare10)
+			*(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11;
+
+		// Write mode registers.
+		EMC(EMC_MRW2) = params->emc_mrw2;
+		EMC(EMC_MRW) = params->emc_mrw1;
+		EMC(EMC_MRW3) = params->emc_mrw3;
+		EMC(EMC_MRW4) = params->emc_mrw4;
+		EMC(EMC_MRW6) = params->emc_mrw6;
+		EMC(EMC_MRW14) = params->emc_mrw14;
+
+		EMC(EMC_MRW8) = params->emc_mrw8;
+		EMC(EMC_MRW12) = params->emc_mrw12;
+		EMC(EMC_MRW9) = params->emc_mrw9;
+		EMC(EMC_MRW13) = params->emc_mrw13;
+
+		if (params->emc_zcal_warm_cold_boot_enables & 1)
+		{
+			// Issue ZQCAL start, device 0.
+			EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0;
+			usleep(params->emc_zcal_init_wait);
+
+			// Issue ZQCAL latch.
+			EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3;
+			// Same for device 1.
+			if (!(params->emc_dev_select & 2))
+			{
+				EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1;
+				usleep(params->emc_zcal_init_wait);
+				EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3;
+			}
+		}
+	}
+
+	// Patch 10 to 12 using BCT spare secure variables.
+	if (params->emc_bct_spare_secure18)
+		*(vu32 *)params->emc_bct_spare_secure18 = params->emc_bct_spare_secure19;
+	if (params->emc_bct_spare_secure20)
+		*(vu32 *)params->emc_bct_spare_secure20 = params->emc_bct_spare_secure21;
+	if (params->emc_bct_spare_secure22)
+		*(vu32 *)params->emc_bct_spare_secure22 = params->emc_bct_spare_secure23;
+
+	// Set package and DPD pad control.
+	PMC(APBDEV_PMC_DDR_CFG) = params->pmc_ddr_cfg;
+
+	// Start periodic ZQ calibration (LPDDRx only).
+	if (params->memory_type == MEMORY_TYPE_LPDDR2 || params->memory_type == MEMORY_TYPE_DDR3L || params->memory_type == MEMORY_TYPE_LPDDR4)
+	{
+		EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval;
+		EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
+		EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd;
+	}
+
+	// Patch 7 using BCT spare variables.
+	if (params->emc_bct_spare12)
+		*(vu32 *)params->emc_bct_spare12 = params->emc_bct_spare13;
+
+	EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place.
+
+	if (params->emc_extra_refresh_num)
+		EMC(EMC_REF) = ((1 << params->emc_extra_refresh_num << 8) - 253) | (params->emc_dev_select << 30);
+
+	// Enable refresh.
+	EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000;
+
+	EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control;
+	EMC(EMC_CFG) = params->emc_cfg;
+	EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq;
+	EMC(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd;
+	EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl;
+
+	// Write addr swizzle lock bit.
+	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2;
+
+	EMC(EMC_TIMING_CONTROL) = 1; // Re-trigger timing to latch power saving functions.
+
+	EMC(EMC_CFG_UPDATE) = params->emc_cfg_update;
+
+	// Enable EMC pipe clock gating.
+	EMC(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk;
+
+	// Depending on freqency, enable CMD/CLK fdpd.
+	EMC(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->emc_fdpd_ctrl_cmd_no_ramp;
+
+	// Set untranslated region requirements.
+	MC(MC_UNTRANSLATED_REGION_CHECK) = params->mc_untranslated_region_check;
+
+	// Lock carveouts per BCT cfg.
+	MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access;
+	MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access;
+	MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl;
+
+	// Disable write access to a bunch of EMC registers.
+	MC(MC_EMEM_CFG_ACCESS_CTRL) = 1;
+
+	// Enable arbiter.
+	SYSREG(AHB_ARBITRATION_XBAR_CTRL) = (SYSREG(AHB_ARBITRATION_XBAR_CTRL) & 0xFFFEFFFF) | (params->ahb_arbitration_xbar_ctrl_meminit_done << 16);
+}
+
+static void *_sdram_get_params_t210()
 {
 	// Check if id is proper.
-	u32 dramid = _get_sdram_id();
+	u32 dramid = fuse_read_dramid(false);
-	if (dramid > 6)
-		dramid = 0;
 
-#ifdef CONFIG_SDRAM_COMPRESS_CFG
+	// Copy base parameters.
-	u8 *buf = (u8 *)SDRAM_PARAMS_ADDR;
+	u32 *params = (u32 *)SDRAM_PARAMS_ADDR;
-	LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz));
+	memcpy(params, &_dram_cfg_0_samsung_4gb, sizeof(sdram_params_t210_t));
-	return (sdram_params_t *)&buf[sizeof(sdram_params_t) * dramid];
-#else
-	sdram_params_t *buf = (sdram_params_t *)SDRAM_PARAMS_ADDR;
-	memcpy(buf, &_dram_cfg_0_samsung_4gb, sizeof(sdram_params_t));
-	switch (dramid)
-	{
-	case DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH:
-	case DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT:
-		break;
 
-	case DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN:
+	// Patch parameters if needed.
-	case DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH:
+	for (u32 i = 0; i < ARRAY_SIZE(sdram_cfg_vendor_patches_t210); i++)
-#ifdef CONFIG_SDRAM_COPPER_SUPPORT
+		if (sdram_cfg_vendor_patches_t210[i].dramcf & DRAM_ID(dramid))
-	case DRAM_4GB_COPPER_SAMSUNG:
+			params[sdram_cfg_vendor_patches_t210[i].offset] = sdram_cfg_vendor_patches_t210[i].val;
-	case DRAM_4GB_COPPER_HYNIX:
+
-	case DRAM_4GB_COPPER_MICRON:
+	return (void *)params;
-#endif
-		_sdram_patch_model_params(dramid, (u32 *)buf);
-		break;
 }
-	return buf;
+
-#endif
+void *sdram_get_params_t210b01()
+{
+	// Check if id is proper.
+	u32 dramid = fuse_read_dramid(false);
+
+	// Copy base parameters.
+	u32 *params = (u32 *)SDRAM_PARAMS_ADDR;
+	memcpy(params, &_dram_cfg_08_10_12_14_samsung_hynix_4gb, sizeof(sdram_params_t210b01_t));
+
+	// Patch parameters if needed.
+	u8 dram_code = dram_encoding_t210b01[dramid];
+	if (!dram_code)
+		return (void *)params;
+
+	for (u32 i = 0; i < ARRAY_SIZE(sdram_cfg_vendor_patches_t210b01); i++)
+		if (sdram_cfg_vendor_patches_t210b01[i].dramcf == dram_code)
+			params[sdram_cfg_vendor_patches_t210b01[i].offset] = sdram_cfg_vendor_patches_t210b01[i].val;
+
+	return (void *)params;
 }
 
 /*
@@ -754,13 +1428,13 @@ sdram_params_t *sdram_get_params()
  * Note: The modulus in the header must match and validated.
  */
 
-sdram_params_t *sdram_get_params_patched()
+void *sdram_get_params_patched()
 {
-	#define IPATCH_CONFIG(addr, data) (((addr - 0x100000) / 2) << 16 | (data & 0xffff))
+	#define IPATCH_CONFIG(addr, data) ((((addr) - 0x100000) / 2) << 16 | ((data) & 0xffff))
-	sdram_params_t *sdram_params = sdram_get_params();
+	sdram_params_t210_t *sdram_params = _sdram_get_params_t210();
 
 	// Disable Warmboot signature check.
-	sdram_params->boot_rom_patch_control = (1 << 31) | (((IPATCH_BASE + 4) - APB_MISC_BASE) / 4);
+	sdram_params->boot_rom_patch_control = BIT(31) | (((IPATCH_BASE + 4) - APB_MISC_BASE) / 4);
 	sdram_params->boot_rom_patch_data = IPATCH_CONFIG(0x10459E, 0x2000);
 /*
 	// Disable SBK lock.
@@ -773,16 +1447,15 @@ sdram_params_t *sdram_get_params_patched()
 	sdram_params->emc_bct_spare12 = (IPATCH_BASE + 11 * 4);
 	sdram_params->emc_bct_spare13 = IPATCH_CONFIG(0x100FDE, 0xE320);
 */
-	return sdram_params;
+	return (void *)sdram_params;
 }
 
-void sdram_init()
+static void _sdram_init_t210()
 {
-	const sdram_params_t *params = (const sdram_params_t *)sdram_get_params();
+	const sdram_params_t210_t *params = (const sdram_params_t210_t *)_sdram_get_params_t210();
 
 	// Set DRAM voltage.
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 0x05);
+	max7762x_regulator_set_voltage(REGULATOR_SD1, 1100000); // HOS uses 1.125V
-	max77620_regulator_set_voltage(REGULATOR_SD1, 1100000);
 
 	// VDDP Select.
 	PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
@@ -801,5 +1474,37 @@ void sdram_init()
 	if (params->emc_bct_spare0)
 		*(vu32 *)params->emc_bct_spare0 = params->emc_bct_spare1;
 
-	_sdram_config(params);
+	_sdram_config_t210(params);
+}
+
+static void _sdram_init_t210b01()
+{
+	const sdram_params_t210b01_t *params = (const sdram_params_t210b01_t *)sdram_get_params_t210b01();
+
+	// VDDP Select.
+	PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
+	usleep(params->pmc_vddp_sel_wait);
+
+	// Turn on MEM IO Power.
+	PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power;
+	PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short;
+
+	PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl;
+
+	// Patch 1 using BCT spare variables
+	if (params->emc_bct_spare0)
+		*(vu32 *)params->emc_bct_spare0 = params->emc_bct_spare1;
+
+	_sdram_config_t210b01(params);
+}
+
+void sdram_init()
+{
+	// Disable remote sense for SD1.
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, MAX77620_SD_CNF2_ROVS_EN_SD0 | MAX77620_SD_CNF2_RSVD);
+
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
+		_sdram_init_t210();
+	else
+		_sdram_init_t210b01();
 }

bdk/mem/sdram.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2020-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,11 +19,110 @@
 #define _SDRAM_H_
 
 #include <mem/emc.h>
-#include <mem/sdram_param_t210.h>
+
+/*
+ * Tegra X1/X1+ EMC/DRAM Bandwidth Chart:
+ *
+ * Note: BWbits T210    = Hz x ddr x bus width x channels = Hz x 2 x 32 x 2.
+ *       BWbits T210B01 = Hz x ddr x bus width x channels = Hz x 2 x 64 x 2.
+ *       Both assume that both sub-partitions are used and thus reaching max
+ *       bandwidth per channel. (T210: 2x16-bit, T210B01: 2x32-bit).
+ *       Retail Mariko use one sub-partition, in order to meet Erista perf.
+ *
+ *              T210   T210B01
+ *   40.8 MHz:  0.61   1.22 GiB/s
+ *   68.0 MHz:  1.01   2.02 GiB/s
+ *  102.0 MHz:  1.52   3.04 GiB/s
+ *  204.0 MHz:  3.04   6.08 GiB/s <-- Tegra X1/X1+ Init/SC7 Frequency
+ *  408.0 MHz:  6.08  12.16 GiB/s
+ *  665.6 MHz:  9.92  19.84 GiB/s
+ *  800.0 MHz: 11.92  23.84 GiB/s <-- Tegra X1/X1+ Nvidia OS Boot Frequency
+ * 1065.6 MHz: 15.89  31.78 GiB/s
+ * 1331.2 MHz: 19.84  39.68 GiB/s
+ * 1600.0 MHz: 23.84  47.68 GiB/s <-- Tegra X1/X1+ HOS Max Frequency
+ * 1862.4 MHz: 27.75  55.50 GiB/s <-- Tegra X1  Official Max Frequency
+ * 2131.2 MHz: 31.76  63.52 GiB/s <-- Tegra X1+ Official Max Frequency
+ *
+ */
+
+enum sdram_ids_erista
+{
+	// LPDDR4 3200Mbps.
+	LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH        = 0,
+	LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE       = 1,
+	LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT  = 2, // WT:C.
+	LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH       = 3, // Changed to Iowa Hynix 4GB 1Y-A.
+	LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH        = 4,
+	LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE      = 5, // Changed to Hoag Hynix 4GB 1Y-A.
+	LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT = 6, // Changed to Aula Hynix 4GB 1Y-A.
+};
+
+enum sdram_ids_mariko
+{
+	// LPDDR4X 4266Mbps.
+	LPDDR4X_IOWA_4GB_HYNIX_1Y_A                     = 3, // Replaced from Copper.
+	LPDDR4X_HOAG_4GB_HYNIX_1Y_A                     = 5, // Replaced from Copper.
+	LPDDR4X_AULA_4GB_HYNIX_1Y_A                     = 6, // Replaced from Copper.
+
+	// LPDDR4X 3733Mbps.
+	LPDDR4X_IOWA_4GB_SAMSUNG_X1X2                   = 7,
+
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 8,  // Die-M.
+	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 9,  // Die-M.
+	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 10, // Die-M.
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // 4266Mbps. Die-E.
+
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 12, // Die-M.
+	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 13, // Die-M.
+	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 14, // Die-M.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // 4266Mbps. Die-E.
+
+	// LPDDR4X 4266Mbps.
+	LPDDR4X_IOWA_4GB_SAMSUNG_Y                      = 16,
+
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 17, // Die-A.
+	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 18, // Die-A.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 19, // Die-A.
+
+	LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y                   = 20,
+	LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y                   = 21,
+
+	// LPDDR4X_AULA_8GB_SAMSUNG_1Y_A                   = 22, // Unused.
+
+	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 23, // Die-A.
+	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 24, // Die-A.
+
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // 4266Mbps. Die-F.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // 4266Mbps. Die-F.
+	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // 4266Mbps. Die-F.
+
+	LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 28, // Die-A.
+};
+
+enum sdram_codes_mariko
+{
+	LPDDR4X_NO_PATCH                       = 0,
+	LPDDR4X_UNUSED                         = 0,
+
+	// LPDDR4X_4GB_SAMSUNG_K4U6E3S4AM_MGCJ          DRAM IDs: 08, 12.
+	// LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLHR_NME         DRAM IDs: 10, 14.
+
+	LPDDR4X_4GB_SAMSUNG_X1X2                   = 1,  // DRAM IDs: 07.
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 2,  // DRAM IDs: 09, 13.
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 3,  // DRAM IDs: 11, 15.
+	LPDDR4X_4GB_SAMSUNG_Y                      = 4,  // DRAM IDs: 16.
+	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 5,  // DRAM IDs: 17, 19, 24.
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 6,  // DRAM IDs: 18, 23, 28.
+	LPDDR4X_4GB_SAMSUNG_1Y_Y                   = 7,  // DRAM IDs: 20.
+	LPDDR4X_8GB_SAMSUNG_1Y_Y                   = 8,  // DRAM IDs: 21.
+	//LPDDR4X_8GB_SAMSUNG_1Y_A                   = 9,  // DRAM IDs: 22. Unused.
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 10, // DRAM IDs: 25, 26, 27.
+	LPDDR4X_4GB_HYNIX_1Y_A                     = 11, // DRAM IDs: 03, 05, 06.
+};
 
 void sdram_init();
-sdram_params_t *sdram_get_params();
+void *sdram_get_params_patched();
-sdram_params_t *sdram_get_params_patched();
+void *sdram_get_params_t210b01();
 void sdram_lp0_save_params(const void *params);
 emc_mr_data_t sdram_read_mrx(emc_mr_t mrx);
 

bdk/mem/sdram_config.inl

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020 CTCaer
+ * Copyright (c) 2020-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -15,26 +15,11 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#define DRAM_CFG_SIZE 1896
+#define DRAM_CFG_T210_SIZE 1896
 
-#define DRAM_ID(x) (1 << (x))
+#define DRAM_ID(x) BIT(x)
 
-#define DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH       0
+static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
-#define DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN      1
-#define DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT 2
-#define DRAM_4GB_COPPER_SAMSUNG                3
-#define DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH       4
-#define DRAM_4GB_COPPER_HYNIX                  5
-#define DRAM_4GB_COPPER_MICRON                 6
-
-typedef struct _sdram_vendor_patch_t
-{
-	u32 val;
-	u16 addr:9;
-	u16 dramid:7;
-} sdram_vendor_patch_t;
-
-static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	/* Specifies the type of memory device */
 	.memory_type                                     = MEMORY_TYPE_LPDDR4,
 
@@ -112,7 +97,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	 * DRAM size information
 	 * Specifies the value for EMC_ADR_CFG
 	 */
-	.emc_adr_cfg                                     = 0x00000001,
+	.emc_adr_cfg                                     = 0x00000001, // 2 Ranks.
 
 	/*
 	 * Specifies the time to wait after asserting pin
@@ -258,7 +243,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.emc_cfg_dig_dll                                 = 0x002C00A0,
 	.emc_cfg_dig_dll_1                               = 0x00003701,
 	.emc_cfg_dig_dll_period                          = 0x00008000,
-	.emc_dev_select                                  = 0x00000000,
+	.emc_dev_select                                  = 0x00000000, // Both Ranks.
 	.emc_sel_dpd_ctrl                                = 0x00040008,
 
 	/* Pads trimmer delays */
@@ -421,7 +406,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.pmc_ddr_ctrl                                    = 0x0007FF8B,
 	.emc_acpd_control                                = 0x00000000,
 
-	.emc_swizzle_rank0_byte0                         = 0x76543201,
+	.emc_swizzle_rank0_byte0                         = 0x76543201, // Overridden to 0x76543201 by spare6/7.
 	.emc_swizzle_rank0_byte1                         = 0x65324710,
 	.emc_swizzle_rank0_byte2                         = 0x25763410,
 	.emc_swizzle_rank0_byte3                         = 0x25673401,
@@ -469,7 +454,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.emc_pmacro_data_rx_term_mode                    = 0x00000010,
 	.emc_pmacro_cmd_rx_term_mode                     = 0x00003000,
 	.emc_pmacro_data_pad_tx_ctrl                     = 0x02000111,
-	.emc_pmacro_common_pad_tx_ctrl                   = 0x00000008,
+	.emc_pmacro_common_pad_tx_ctrl                   = 0x00000008, // Overridden to 0x0000000A by spare4/5.
 	.emc_pmacro_cmd_pad_tx_ctrl                      = 0x0A000000,
 
 	.emc_cfg3                                        = 0x00000040,
@@ -505,9 +490,9 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.emc_pmacro_cmd_ctrl2                            = 0x0A0A0A0A,
 
 	/* DRAM size information */
-	.mc_emem_adr_cfg                                 = 0x00000001,
+	.mc_emem_adr_cfg                                 = 0x00000001, // 2 Ranks.
-	.mc_emem_adr_cfg_dev0                            = 0x00070302,
+	.mc_emem_adr_cfg_dev0                            = 0x00070302, // Rank 0 Density 512MB.
-	.mc_emem_adr_cfg_dev1                            = 0x00070302,
+	.mc_emem_adr_cfg_dev1                            = 0x00070302, // Rank 1 Density 512MB.
 	.mc_emem_adr_cfg_channel_mask                    = 0xFFFF2400,
 	.mc_emem_adr_cfg_bank_mask0                      = 0x6E574400,
 	.mc_emem_adr_cfg_bank_mask1                      = 0x39722800,
@@ -516,7 +501,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
 	 * size (in KBytes)
 	 */
-	.mc_emem_cfg                                     = 0x00001000,
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density.
 
 	/* MC arbitration configuration */
 	.mc_emem_arb_cfg                                 = 0x08000001,
@@ -659,48 +644,53 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.mc_mts_carveout_reg_ctrl                        = 0x00000000
 };
 
-static const sdram_vendor_patch_t sdram_cfg_vendor_patches[] = {
+static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210[] = {
 	// Hynix timing config.
-	{ 0x0000000D,  67, DRAM_ID(1) | DRAM_ID(5) }, // emc_r2w.
+	{ 0x0000000D, 0x10C / 4, DRAM_ID(1) }, // emc_r2w.
-	{ 0x00000001,  91, DRAM_ID(1) | DRAM_ID(5) }, // emc_puterm_extra.
+	{ 0x00000001, 0x16C / 4, DRAM_ID(1) }, // emc_puterm_extra.
-	{ 0x80000000,  92, DRAM_ID(1) | DRAM_ID(5) }, // emc_puterm_width.
+	{ 0x80000000, 0x170 / 4, DRAM_ID(1) }, // emc_puterm_width.
-	{ 0x00000210, 317, DRAM_ID(1) | DRAM_ID(5) }, // emc_pmacro_data_rx_term_mode.
+	{ 0x00000210, 0x4F4 / 4, DRAM_ID(1) }, // emc_pmacro_data_rx_term_mode.
-	{ 0x00000005, 368, DRAM_ID(1) | DRAM_ID(5) }, // mc_emem_arb_timing_r2w.
+	{ 0x00000005, 0x5C0 / 4, DRAM_ID(1) }, // mc_emem_arb_timing_r2w.
 
 	// Samsung 6GB density config.
-	{ 0x000C0302, 347, DRAM_ID(4) },              // mc_emem_adr_cfg_dev0. 768MB sub-partition density.
+	{ 0x000C0302, 0x56C / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev0. 768MB Rank 0 density.
-	{ 0x000C0302, 348, DRAM_ID(4) },              // mc_emem_adr_cfg_dev1. 768MB sub-partition density.
+	{ 0x000C0302, 0x570 / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev1. 768MB Rank 1 density.
-	{ 0x00001800, 353, DRAM_ID(4) },              // mc_emem_cfg. 6GB total density.
+	{ 0x00001800, 0x584 / 4, DRAM_ID(4) }, // mc_emem_cfg. 6GB total density.
 
 #ifdef CONFIG_SDRAM_COPPER_SUPPORT
 	// Copper prototype Samsung/Hynix/Micron timing configs.
-	{ 0x0000003A,  59, DRAM_ID(6) },              // emc_rfc. Auto refresh.
+	{ 0x0000003A,  0xEC / 4, DRAM_ID(6) },              // emc_rfc. Auto refresh.
-	{ 0x0000001D,  60, DRAM_ID(6) },              // emc_rfc_pb. Bank Auto refresh.
+	{ 0x0000001D,  0xF0 / 4, DRAM_ID(6) },              // emc_rfc_pb. Bank Auto refresh.
-	{ 0x00000012, 108, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_rw2pden.
+	{ 0x0000000D, 0x10C / 4, DRAM_ID(5) },              // emc_r2w.
-	{ 0x0000003B, 112, DRAM_ID(6) },              // emc_txsr.
+	{ 0x00000001, 0x16C / 4, DRAM_ID(5) },              // emc_puterm_extra.
-	{ 0x0000003B, 113, DRAM_ID(6) },              // emc_txsr_dll.
+	{ 0x80000000, 0x170 / 4, DRAM_ID(5) },              // emc_puterm_width.
-	{ 0x00000003, 119, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_tclkstable.
+	{ 0x00000012, 0x1B0 / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_rw2pden.
-	{ 0x00120015, 205, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
+	{ 0x0000003B, 0x1C0 / 4, DRAM_ID(6) },              // emc_txsr.
-	{ 0x00160012, 206, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_5.
+	{ 0x0000003B, 0x1C4 / 4, DRAM_ID(6) },              // emc_txsr_dll.
-	{ 0x00120015, 211, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
+	{ 0x00000003, 0x1DC / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_tclkstable.
-	{ 0x00160012, 212, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_5.
+	{ 0x00120015, 0x334 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
-	{ 0x002F0032, 213, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
+	{ 0x00160012, 0x338 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_5.
-	{ 0x00310032, 214, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
+	{ 0x00120015, 0x34C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
-	{ 0x00360034, 215, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
+	{ 0x00160012, 0x350 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_5.
-	{ 0x0033002F, 216, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_3.
+	{ 0x002F0032, 0x354 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
-	{ 0x00000006, 217, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
+	{ 0x00310032, 0x358 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
-	{ 0x002F0032, 219, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
+	{ 0x00360034, 0x35C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
-	{ 0x00310032, 220, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
+	{ 0x0033002F, 0x360 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_3.
-	{ 0x00360034, 221, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
+	{ 0x00000006, 0x364 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
-	{ 0x0033002F, 222, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_3.
+	{ 0x002F0032, 0x36C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
-	{ 0x00000006, 223, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
+	{ 0x00310032, 0x370 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
-	{ 0x00150015, 233, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_0.
+	{ 0x00360034, 0x374 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
-	{ 0x00120012, 235, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_2.
+	{ 0x0033002F, 0x378 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_3.
-	{ 0x00160016, 236, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_3.
+	{ 0x00000006, 0x37C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
-	{ 0x00000015, 237, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_4.
+	{ 0x00150015, 0x3A4 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_0.
-	{ 0x00000012, 295, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft2.
+	{ 0x00120012, 0x3AC / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_2.
-	{ 0x00000012, 296, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft3.
+	{ 0x00160016, 0x3B0 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_3.
-	{ 0x00000007, 370, DRAM_ID(6) },              // mc_emem_arb_timing_rfcpb. Bank refresh.
+	{ 0x00000015, 0x3B4 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_4.
-	{ 0x72A30504, 373, DRAM_ID(6) },              // mc_emem_arb_misc0.
+	{ 0x00000012, 0x49C / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft2.
+	{ 0x00000012, 0x4A0 / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft3.
+	{ 0x00000210, 0x4F4 / 4, DRAM_ID(5) },              // emc_pmacro_data_rx_term_mode.
+	{ 0x00000005, 0x5C0 / 4, DRAM_ID(5) },              // mc_emem_arb_timing_r2w.
+	{ 0x00000007, 0x5C8 / 4, DRAM_ID(6) },              // mc_emem_arb_timing_rfcpb. Bank refresh.
+	{ 0x72A30504, 0x5D4 / 4, DRAM_ID(6) },              // mc_emem_arb_misc0.
 #endif
 };

bdk/mem/sdram_config_lz.inl

@@ -1,124 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-static const u8 _dram_cfg_lz[1262] = {
-	0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
-	0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08,
-	0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00,
-	0x00, 0x04, 0xB4, 0x01, 0x70, 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00,
-	0x70, 0x17, 0x10, 0x24, 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40,
-	0x00, 0x00, 0x00, 0x17, 0x04, 0x04, 0x17, 0x09, 0x18, 0xFF, 0xFF, 0x1F,
-	0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, 0x77,
-	0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x08, 0x08, 0xA6, 0xA6,
-	0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, 0x04, 0x04,
-	0x04, 0x04, 0x17, 0x04, 0x04, 0x17, 0x04, 0x3C, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x17, 0x04, 0x04, 0x17, 0x06, 0x06, 0x00, 0x00, 0x04, 0x08, 0x17, 0x06,
-	0x46, 0xA1, 0x01, 0x00, 0x00, 0x32, 0x17, 0x0B, 0x64, 0x01, 0x17, 0x04,
-	0x7C, 0x17, 0x07, 0x0C, 0x03, 0x17, 0x04, 0x04, 0x00, 0x00, 0x00, 0x1E,
-	0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x13,
-	0x17, 0x0B, 0x2C, 0x09, 0x00, 0x00, 0x00, 0x17, 0x05, 0x5D, 0x17, 0x07,
-	0x10, 0x0B, 0x17, 0x07, 0x28, 0x08, 0x17, 0x07, 0x0C, 0x17, 0x04, 0x1C,
-	0x20, 0x00, 0x00, 0x00, 0x06, 0x17, 0x04, 0x04, 0x17, 0x07, 0x08, 0x17,
-	0x04, 0x50, 0x17, 0x04, 0x2C, 0x17, 0x04, 0x1C, 0x17, 0x04, 0x10, 0x17,
-	0x08, 0x6C, 0x17, 0x04, 0x10, 0x17, 0x04, 0x38, 0x17, 0x04, 0x40, 0x05,
-	0x17, 0x07, 0x1C, 0x17, 0x08, 0x58, 0x17, 0x04, 0x24, 0x17, 0x04, 0x18,
-	0x17, 0x08, 0x64, 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14,
-	0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x17, 0x09, 0x0C, 0x17, 0x05, 0x82,
-	0x58, 0x17, 0x07, 0x61, 0xC1, 0x17, 0x07, 0x50, 0x17, 0x04, 0x04, 0x17,
-	0x08, 0x81, 0x48, 0x17, 0x04, 0x04, 0x17, 0x04, 0x28, 0x17, 0x04, 0x60,
-	0x17, 0x08, 0x54, 0x27, 0x17, 0x04, 0x04, 0x17, 0x07, 0x14, 0x17, 0x04,
-	0x04, 0x04, 0x17, 0x07, 0x81, 0x58, 0x17, 0x0C, 0x0C, 0x1C, 0x03, 0x00,
-	0x00, 0x0D, 0xA0, 0x60, 0x91, 0xBF, 0x3B, 0x17, 0x04, 0x5A, 0xF3, 0x0C,
-	0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05,
-	0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03,
-	0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02,
-	0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08,
-	0x24, 0x06, 0x07, 0x9A, 0x12, 0x17, 0x05, 0x83, 0x41, 0x00, 0xFF, 0x17,
-	0x10, 0x83, 0x6C, 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00,
-	0x00, 0x0D, 0x08, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00,
-	0x00, 0x0B, 0x08, 0x72, 0x72, 0x0E, 0x0C, 0x17, 0x04, 0x20, 0x08, 0x08,
-	0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x17, 0x06,
-	0x2C, 0x11, 0x08, 0x17, 0x10, 0x84, 0x67, 0x15, 0x00, 0xCC, 0x00, 0x0A,
-	0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, 0xFF,
-	0x0F, 0xFF, 0x0F, 0x17, 0x08, 0x83, 0x4C, 0x01, 0x03, 0x00, 0x70, 0x00,
-	0x0C, 0x00, 0x01, 0x17, 0x04, 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04,
-	0x00, 0x06, 0x13, 0x07, 0x00, 0x80, 0x17, 0x04, 0x10, 0xA0, 0x00, 0x2C,
-	0x00, 0x01, 0x37, 0x00, 0x00, 0x00, 0x80, 0x17, 0x06, 0x48, 0x08, 0x00,
-	0x04, 0x00, 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28,
-	0x28, 0x28, 0x17, 0x04, 0x04, 0x11, 0x11, 0x11, 0x11, 0x17, 0x04, 0x04,
-	0xBE, 0x00, 0x00, 0x17, 0x05, 0x58, 0x17, 0x08, 0x5C, 0x17, 0x22, 0x85,
-	0x6A, 0x17, 0x1A, 0x1A, 0x14, 0x00, 0x12, 0x00, 0x10, 0x17, 0x05, 0x83,
-	0x0A, 0x17, 0x16, 0x18, 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00,
-	0x33, 0x00, 0x35, 0x00, 0x30, 0x00, 0x32, 0x17, 0x05, 0x83, 0x0C, 0x17,
-	0x04, 0x20, 0x17, 0x18, 0x18, 0x28, 0x00, 0x28, 0x17, 0x04, 0x04, 0x17,
-	0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x14, 0x17, 0x05, 0x5A, 0x17, 0x04,
-	0x5C, 0x17, 0x04, 0x5E, 0x17, 0x04, 0x0E, 0x17, 0x0E, 0x78, 0x17, 0x09,
-	0x82, 0x50, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51,
-	0x17, 0x08, 0x18, 0x80, 0x01, 0x00, 0x00, 0x40, 0x17, 0x04, 0x20, 0x03,
-	0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x17, 0x08, 0x82, 0x58,
-	0x17, 0x0C, 0x38, 0x17, 0x1B, 0x81, 0x6C, 0x17, 0x08, 0x85, 0x60, 0x17,
-	0x08, 0x86, 0x50, 0x17, 0x08, 0x86, 0x60, 0x17, 0x06, 0x83, 0x21, 0x22,
-	0x04, 0xFF, 0xFF, 0xAF, 0x4F, 0x17, 0x0C, 0x86, 0x74, 0x17, 0x08, 0x2C,
-	0x8B, 0xFF, 0x07, 0x17, 0x06, 0x81, 0x04, 0x32, 0x54, 0x76, 0x10, 0x47,
-	0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75,
-	0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45,
-	0x32, 0x67, 0x17, 0x04, 0x24, 0x49, 0x92, 0x24, 0x17, 0x04, 0x04, 0x17,
-	0x11, 0x7C, 0x1B, 0x17, 0x04, 0x04, 0x17, 0x13, 0x81, 0x14, 0x2F, 0x41,
-	0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x17, 0x04, 0x7C, 0xFF, 0xFF, 0xFF,
-	0x7F, 0x0B, 0xD7, 0x06, 0x40, 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03,
-	0x00, 0x00, 0x5C, 0x01, 0x00, 0x10, 0x10, 0x10, 0x17, 0x06, 0x86, 0x59,
-	0x17, 0x0F, 0x89, 0x14, 0x37, 0x17, 0x07, 0x82, 0x72, 0x10, 0x17, 0x06,
-	0x83, 0x0D, 0x00, 0x11, 0x01, 0x17, 0x05, 0x85, 0x39, 0x17, 0x04, 0x0E,
-	0x0A, 0x17, 0x07, 0x89, 0x29, 0x17, 0x04, 0x1B, 0x17, 0x08, 0x86, 0x77,
-	0x17, 0x09, 0x12, 0x20, 0x00, 0x00, 0x00, 0x81, 0x10, 0x09, 0x28, 0x93,
-	0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76, 0x17, 0x18, 0x82, 0x2C, 0xFF,
-	0xEF, 0xFF, 0xEF, 0xC0, 0xC0, 0xC0, 0xC0, 0x17, 0x04, 0x04, 0xDC, 0xDC,
-	0xDC, 0xDC, 0x0A, 0x0A, 0x0A, 0x0A, 0x17, 0x04, 0x04, 0x17, 0x04, 0x04,
-	0x17, 0x05, 0x82, 0x24, 0x03, 0x07, 0x17, 0x04, 0x04, 0x00, 0x00, 0x24,
-	0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, 0x10,
-	0x9C, 0x4B, 0x17, 0x04, 0x64, 0x01, 0x00, 0x00, 0x08, 0x4C, 0x00, 0x00,
-	0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x17, 0x06, 0x85, 0x60, 0x17,
-	0x10, 0x82, 0x74, 0x17, 0x08, 0x08, 0x17, 0x08, 0x88, 0x00, 0x17, 0x04,
-	0x10, 0x04, 0x17, 0x0B, 0x87, 0x6C, 0x01, 0x00, 0x02, 0x02, 0x01, 0x02,
-	0x03, 0x00, 0x04, 0x05, 0xC3, 0x71, 0x0F, 0x0F, 0x17, 0x08, 0x8B, 0x18,
-	0x1F, 0x17, 0x09, 0x81, 0x73, 0x00, 0xFF, 0x00, 0xFF, 0x17, 0x05, 0x86,
-	0x48, 0x17, 0x04, 0x0C, 0x17, 0x07, 0x86, 0x34, 0x00, 0x00, 0xF0, 0x17,
-	0x09, 0x87, 0x54, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x17, 0x0C, 0x81,
-	0x52, 0x17, 0x0A, 0x1C, 0x17, 0x10, 0x81, 0x6C, 0x17, 0x0A, 0x82, 0x21,
-	0x17, 0x07, 0x82, 0x4D, 0x17, 0x0A, 0x8A, 0x1B, 0x17, 0x11, 0x2C, 0x76,
-	0x0C, 0x17, 0x0A, 0x8A, 0x67, 0x17, 0x0F, 0x84, 0x28, 0x17, 0x06, 0x34,
-	0x17, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x17, 0x0C, 0x8B, 0x1F, 0x17, 0x2A,
-	0x38, 0x1E, 0x17, 0x0A, 0x38, 0x17, 0x13, 0x81, 0x28, 0x00, 0xC0, 0x17,
-	0x17, 0x55, 0x46, 0x24, 0x17, 0x0A, 0x81, 0x28, 0x17, 0x14, 0x38, 0x17,
-	0x18, 0x81, 0x60, 0x46, 0x2C, 0x17, 0x06, 0x38, 0xEC, 0x17, 0x0D, 0x16,
-	0x17, 0x0E, 0x82, 0x3C, 0x17, 0x82, 0x0C, 0x8E, 0x68, 0x17, 0x04, 0x24,
-	0x17, 0x5C, 0x8E, 0x68, 0x17, 0x07, 0x82, 0x5F, 0x80, 0x17, 0x87, 0x01,
-	0x8E, 0x68, 0x02, 0x17, 0x81, 0x4A, 0x8E, 0x68, 0x17, 0x0C, 0x87, 0x78,
-	0x17, 0x85, 0x28, 0x8E, 0x68, 0x17, 0x8E, 0x68, 0x9D, 0x50, 0x17, 0x81,
-	0x24, 0x8E, 0x68, 0x17, 0x04, 0x2C, 0x17, 0x28, 0x8E, 0x68, 0x17, 0x04,
-	0x30, 0x17, 0x85, 0x3C, 0x8E, 0x68, 0x12, 0x17, 0x07, 0x85, 0x70, 0x17,
-	0x88, 0x74, 0x8E, 0x68, 0x17, 0x87, 0x3E, 0x9D, 0x50, 0x0C, 0x17, 0x04,
-	0x04, 0x17, 0x12, 0x8E, 0x68, 0x18, 0x17, 0x87, 0x12, 0xBB, 0x20, 0x17,
-	0x83, 0x04, 0x9D, 0x50, 0x15, 0x17, 0x05, 0x8D, 0x76, 0x17, 0x0F, 0x8B,
-	0x49, 0x17, 0x0B, 0x18, 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00,
-	0x34, 0x00, 0x36, 0x00, 0x2F, 0x00, 0x33, 0x17, 0x09, 0x84, 0x0C, 0x17,
-	0x18, 0x18, 0x17, 0x20, 0x8E, 0x68, 0x15, 0x17, 0x07, 0x5A, 0x17, 0x06,
-	0x5E, 0x16, 0x00, 0x15, 0x17, 0x82, 0x40, 0x9D, 0x50, 0x17, 0x86, 0x5F,
-	0xBB, 0x20, 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x17, 0x81, 0x4F, 0xAC, 0x38,
-	0x3B, 0x17, 0x04, 0x04, 0x17, 0x86, 0x30, 0x8E, 0x68, 0x17, 0x81, 0x53,
-	0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10,
-	0x8E, 0x68
-};

bdk/mem/sdram_config_t210b01.inl

@@ -0,0 +1,992 @@
+/*
+ * Copyright (c) 2020-2021 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define DRAM_CFG_T210B01_SIZE 2104
+
+static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
+	/* Specifies the type of memory device */
+	.memory_type                                     = MEMORY_TYPE_LPDDR4,
+
+	/* MC/EMC clock source configuration */
+	.pllm_input_divider                              = 0x00000001, // M div.
+	.pllm_feedback_divider                           = 0x00000022, // N div.
+	.pllm_stable_time                                = 0x0000012C,
+	.pllm_setup_control                              = 0x00000000,
+	.pllm_post_divider                               = 0x00000000, // P div.
+	.pllm_kcp                                        = 0x00000000,
+	.pllm_kvco                                       = 0x00000000,
+
+	/* Spare BCT params */
+	.emc_bct_spare0                                  = 0x00000000,
+	.emc_bct_spare1                                  = 0x00000000,
+	.emc_bct_spare2                                  = 0x00000000,
+	.emc_bct_spare3                                  = 0x00000000,
+	.emc_bct_spare4                                  = 0x00000000,
+	.emc_bct_spare5                                  = 0x00000000,
+	.emc_bct_spare6                                  = 0x00000000,
+	.emc_bct_spare7                                  = 0x00000000,
+	.emc_bct_spare8                                  = 0x00000000,
+	.emc_bct_spare9                                  = 0x00000000,
+	.emc_bct_spare10                                 = 0x00000000,
+	.emc_bct_spare11                                 = 0x00000000,
+	.emc_bct_spare12                                 = 0x00000000,
+	.emc_bct_spare13                                 = 0x00000000,
+
+	.emc_bct_spare_secure0                           = 0x00000000,
+	.emc_bct_spare_secure1                           = 0x00000000,
+	.emc_bct_spare_secure2                           = 0x00000000,
+	.emc_bct_spare_secure3                           = 0x00000000,
+	.emc_bct_spare_secure4                           = 0x00000000,
+	.emc_bct_spare_secure5                           = 0x00000000,
+	.emc_bct_spare_secure6                           = 0x00000000,
+	.emc_bct_spare_secure7                           = 0x00000000,
+	.emc_bct_spare_secure8                           = 0x00000000,
+	.emc_bct_spare_secure9                           = 0x00000000,
+	.emc_bct_spare_secure10                          = 0x00000000,
+	.emc_bct_spare_secure11                          = 0x00000000,
+	.emc_bct_spare_secure12                          = 0x00000000,
+	.emc_bct_spare_secure13                          = 0x00000000,
+	.emc_bct_spare_secure14                          = 0x00000000,
+	.emc_bct_spare_secure15                          = 0x00000000,
+	.emc_bct_spare_secure16                          = 0x00000000,
+	.emc_bct_spare_secure17                          = 0x00000000,
+	.emc_bct_spare_secure18                          = 0x00000000,
+	.emc_bct_spare_secure19                          = 0x00000000,
+	.emc_bct_spare_secure20                          = 0x00000000,
+	.emc_bct_spare_secure21                          = 0x00000000,
+	.emc_bct_spare_secure22                          = 0x00000000,
+	.emc_bct_spare_secure23                          = 0x00000000,
+
+	/* EMC clock configuration */
+	.emc_clock_source                                = 0x40188002,
+	.emc_clock_source_dll                            = 0x40000000,
+
+	.clk_rst_pllm_misc20_override                    = 0x00000000,
+	.clk_rst_pllm_misc20_override_enable             = 0x00000000,
+
+	.clear_clock2_mc1                                = 0x00000000,
+
+	/* Auto-calibration of EMC pads */
+	.emc_auto_cal_interval                           = 0x001FFFFF,
+
+	.emc_auto_cal_config                             = 0xA01A51D8,
+	.emc_auto_cal_config2                            = 0x00000000,
+	.emc_auto_cal_config3                            = 0x00880000,
+
+	.emc_auto_cal_config4                            = 0x00880000,
+	.emc_auto_cal_config5                            = 0x00001220,
+	.emc_auto_cal_config6                            = 0x00880000,
+	.emc_auto_cal_config7                            = 0x00880000,
+	.emc_auto_cal_config8                            = 0x00880000,
+	.emc_auto_cal_config9                            = 0x00000000,
+
+	.emc_auto_cal_vref_sel0                          = 0xB3C5BCBC,
+	.emc_auto_cal_vref_sel1                          = 0x00009E3C,
+
+	.emc_auto_cal_channel                            = 0xC1E00302,
+
+	.emc_pmacro_auto_cal_cfg0                        = 0x04040404,
+	.emc_pmacro_auto_cal_cfg1                        = 0x04040404,
+	.emc_pmacro_auto_cal_cfg2                        = 0x04040404,
+
+	.emc_pmacro_rx_term                              = 0x3F3F3F3F,
+	.emc_pmacro_dq_tx_drive                          = 0x3F3F3F3F,
+	.emc_pmacro_ca_tx_drive                          = 0x3F3F3F3F,
+	.emc_pmacro_cmd_tx_drive                         = 0x00001220,
+	.emc_pmacro_auto_cal_common                      = 0x00000804,
+	.emc_pmacro_zcrtl                                = 0x00505050,
+
+	/* Specifies the time for the calibration to stabilize (in microseconds) */
+	.emc_auto_cal_wait                               = 0x000001A1,
+
+	.emc_xm2_comp_pad_ctrl                           = 0x00000030,
+	.emc_xm2_comp_pad_ctrl2                          = 0x16001000,
+	.emc_xm2_comp_pad_ctrl3                          = 0x00901000,
+
+	/*
+	 * DRAM size information
+	 * Specifies the value for EMC_ADR_CFG
+	 */
+	.emc_adr_cfg                                     = 0x00000000, // 1 Rank.
+
+	/*
+	 * Specifies the time to wait after asserting pin
+	 * CKE (in microseconds)
+	 */
+	.emc_pin_program_wait                            = 0x00000002,
+	/* Specifies the extra delay before/after pin RESET/CKE command */
+	.emc_pin_extra_wait                              = 0x00000000,
+
+	.emc_pin_gpio_enable                             = 0x00000003,
+	.emc_pin_gpio                                    = 0x00000003,
+
+	/* Specifies the extra delay after the first writing of EMC_TIMING_CONTROL */
+	.emc_timing_control_wait                         = 0x0000001E,
+
+	/* Timing parameters required for the SDRAM */
+	.emc_rc                                          = 0x0000000D,
+	.emc_rfc                                         = 0x0000003A,
+	.emc_rfc_pb                                      = 0x0000001D,
+	.emc_ref_ctrl2                                   = 0x00000000,
+	.emc_rfc_slr                                     = 0x00000000,
+	.emc_ras                                         = 0x00000009,
+	.emc_rp                                          = 0x00000004,
+	.emc_r2r                                         = 0x00000000,
+	.emc_w2w                                         = 0x00000000,
+	.emc_r2w                                         = 0x0000000B,
+	.emc_w2r                                         = 0x0000000D,
+	.emc_r2p                                         = 0x00000008,
+	.emc_w2p                                         = 0x0000000B,
+	.emc_tppd                                        = 0x00000004,
+	.emc_trtm                                        = 0x00000017,
+	.emc_twtm                                        = 0x00000015,
+	.emc_tratm                                       = 0x00000017,
+	.emc_twatm                                       = 0x0000001B,
+	.emc_tr2ref                                      = 0x00000000,
+	.emc_ccdmw                                       = 0x00000020,
+	.emc_rd_rcd                                      = 0x00000006,
+	.emc_wr_rcd                                      = 0x00000006,
+	.emc_rrd                                         = 0x00000006,
+	.emc_rext                                        = 0x00000003,
+	.emc_wext                                        = 0x00000000,
+	.emc_wdv                                         = 0x00000004,
+	.emc_wdv_chk                                     = 0x00000006,
+	.emc_wsv                                         = 0x00000002,
+	.emc_wev                                         = 0x00000000,
+	.emc_wdv_mask                                    = 0x00000004,
+	.emc_ws_duration                                 = 0x00000008,
+	.emc_we_duration                                 = 0x0000000E,
+	.emc_quse                                        = 0x00000005,
+	.emc_quse_width                                  = 0x00000006,
+	.emc_ibdly                                       = 0x00000000,
+	.emc_obdly                                       = 0x00000000,
+	.emc_einput                                      = 0x00000002,
+	.emc_einput_duration                             = 0x0000000D,
+	.emc_puterm_extra                                = 0x00000001,
+	.emc_puterm_width                                = 0x80000000,
+	.emc_qrst                                        = 0x00010000,
+	.emc_qsafe                                       = 0x00000012,
+	.emc_rdv                                         = 0x00000018,
+	.emc_rdv_mask                                    = 0x0000001A,
+	.emc_rdv_early                                   = 0x00000016,
+	.emc_rdv_early_mask                              = 0x00000018,
+	.emc_qpop                                        = 0x0000000A,
+	.emc_refresh                                     = 0x00000304,
+	.emc_burst_refresh_num                           = 0x00000000,
+	.emc_prerefresh_req_cnt                          = 0x000000C1,
+	.emc_pdex2wr                                     = 0x00000008,
+	.emc_pdex2rd                                     = 0x00000008,
+	.emc_pchg2pden                                   = 0x00000003,
+	.emc_act2pden                                    = 0x0000000A,
+	.emc_ar2pden                                     = 0x00000003,
+	.emc_rw2pden                                     = 0x00000014,
+	.emc_cke2pden                                    = 0x00000005,
+	.emc_pdex2che                                    = 0x00000002,
+	.emc_pdex2mrr                                    = 0x0000000D,
+	.emc_txsr                                        = 0x0000003B,
+	.emc_txsr_dll                                    = 0x0000003B,
+	.emc_tcke                                        = 0x00000005,
+	.emc_tckesr                                      = 0x00000005,
+	.emc_tpd                                         = 0x00000004,
+	.emc_tfaw                                        = 0x00000009,
+	.emc_trpab                                       = 0x00000005,
+	.emc_tclkstable                                  = 0x00000004,
+	.emc_tclkstop                                    = 0x00000009,
+	.emc_trefbw                                      = 0x0000031C,
+
+	/* FBIO configuration values */
+	.emc_fbio_cfg5                                   = 0x9160A00D,
+	.emc_fbio_cfg7                                   = 0x00003A3F,
+	.emc_fbio_cfg8                                   = 0x0CF30000,
+
+	/* Command mapping for CMD brick 0 */
+	.emc_cmd_mapping_cmd0_0                          = 0x061B0504,
+	.emc_cmd_mapping_cmd0_1                          = 0x1C070302,
+	.emc_cmd_mapping_cmd0_2                          = 0x05252523,
+	.emc_cmd_mapping_cmd1_0                          = 0x0A091D08,
+	.emc_cmd_mapping_cmd1_1                          = 0x0D1E0B24,
+	.emc_cmd_mapping_cmd1_2                          = 0x0326260C,
+	.emc_cmd_mapping_cmd2_0                          = 0x231C1B02,
+	.emc_cmd_mapping_cmd2_1                          = 0x05070403,
+	.emc_cmd_mapping_cmd2_2                          = 0x02252506,
+	.emc_cmd_mapping_cmd3_0                          = 0x0D1D0B0A,
+	.emc_cmd_mapping_cmd3_1                          = 0x1E090C08,
+	.emc_cmd_mapping_cmd3_2                          = 0x08262624,
+	.emc_cmd_mapping_byte                            = 0x9A070624,
+
+	.emc_fbio_spare                                  = 0x00000012,
+	.emc_cfg_rsv                                     = 0xFF00FF00,
+
+	/* MRS command values */
+	.emc_mrs                                         = 0x00000000,
+	.emc_emrs                                        = 0x00000000,
+	.emc_emrs2                                       = 0x00000000,
+	.emc_emrs3                                       = 0x00000000,
+	.emc_mrw1                                        = 0x88010004,
+	.emc_mrw2                                        = 0x88020000,
+	.emc_mrw3                                        = 0x880D0000,
+	.emc_mrw4                                        = 0xC0000000,
+	.emc_mrw6                                        = 0x88033131,
+	.emc_mrw8                                        = 0x880B0000,
+	.emc_mrw9                                        = 0x8C0E5D5D,
+	.emc_mrw10                                       = 0x880C5D5D,
+	.emc_mrw12                                       = 0x8C0D0808,
+	.emc_mrw13                                       = 0x8C0D0000,
+	.emc_mrw14                                       = 0x88161616,
+	.emc_mrw_extra                                   = 0x88010004,
+	.emc_warm_boot_mrw_extra                         = 0x08110000,
+	.emc_warm_boot_extramode_reg_write_enable        = 0x00000001,
+	.emc_extramode_reg_write_enable                  = 0x00000000,
+	.emc_mrw_reset_command                           = 0x00000000,
+	.emc_mrw_reset_ninit_wait                        = 0x00000000,
+	.emc_mrs_wait_cnt                                = 0x00CC0010,
+	.emc_mrs_wait_cnt2                               = 0x0033000A,
+
+	/* EMC miscellaneous configurations */
+	.emc_cfg                                         = 0xF3200000,
+	.emc_cfg2                                        = 0x00110825,
+	.emc_cfg_pipe                                    = 0x0FFF0000,
+	.emc_cfg_pipe_clk                                = 0x00000000,
+	.emc_fdpd_ctrl_cmd_no_ramp                       = 0x00000001,
+	.emc_cfg_update                                  = 0x70000301,
+	.emc_dbg                                         = 0x01000C00,
+	.emc_dbg_write_mux                               = 0x00000001,
+	.emc_cmd_q                                       = 0x10004408,
+	.emc_mc2emc_q                                    = 0x06000404,
+	.emc_dyn_self_ref_control                        = 0x00000713,
+	.ahb_arbitration_xbar_ctrl_meminit_done          = 0x00000001,
+	.emc_cfg_dig_dll                                 = 0x002C00A0,
+	.emc_cfg_dig_dll_1                               = 0x000F3701,
+	.emc_cfg_dig_dll_period                          = 0x00008000,
+	.emc_dev_select                                  = 0x00000002, // Rank 0 only.
+	.emc_sel_dpd_ctrl                                = 0x0004000C,
+
+	/* Pads trimmer delays */
+	.emc_fdpd_ctrl_dq                                = 0x8020221F,
+	.emc_fdpd_ctrl_cmd                               = 0x0220F40F,
+	.emc_pmacro_ib_vref_dq_0                         = 0x29292929,
+	.emc_pmacro_ib_vref_dq_1                         = 0x29292929,
+	.emc_pmacro_ib_vref_dqs_0                        = 0x29292929,
+	.emc_pmacro_ib_vref_dqs_1                        = 0x29292929,
+	.emc_pmacro_ib_rxrt                              = 0x00000078,
+	.emc_cfg_pipe1                                   = 0x0FFF0000,
+	.emc_cfg_pipe2                                   = 0x00000000,
+
+	.emc_pmacro_quse_ddll_rank0_0                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_1                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_2                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_3                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_4                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_5                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_0                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_1                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_2                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_3                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_4                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_5                    = 0x00000000,
+
+	.emc_pmacro_ob_ddll_long_dq_rank0_0              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_1              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_2              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_3              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_4              = 0x000D0016,
+	.emc_pmacro_ob_ddll_long_dq_rank0_5              = 0x0017000B,
+	.emc_pmacro_ob_ddll_long_dq_rank1_0              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_1              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_2              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_3              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_4              = 0x000D0016,
+	.emc_pmacro_ob_ddll_long_dq_rank1_5              = 0x0017000B,
+
+	.emc_pmacro_ob_ddll_long_dqs_rank0_0             = 0x00450043,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_1             = 0x00430045,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_2             = 0x00470046,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_3             = 0x00460041,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_4             = 0x0003000C,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_5             = 0x000D0000,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_0             = 0x00450043,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_1             = 0x00430045,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_2             = 0x00470046,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_3             = 0x00460041,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_4             = 0x0003000C,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_5             = 0x000D0000,
+
+	.emc_pmacro_ib_ddll_long_dqs_rank0_0             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank0_1             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank0_2             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank0_3             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_0             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_1             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_2             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_3             = 0x00280028,
+
+	.emc_pmacro_ddll_long_cmd_0                      = 0x00160016,
+	.emc_pmacro_ddll_long_cmd_1                      = 0x000D000D,
+	.emc_pmacro_ddll_long_cmd_2                      = 0x000B000B,
+	.emc_pmacro_ddll_long_cmd_3                      = 0x00170017,
+	.emc_pmacro_ddll_long_cmd_4                      = 0x00000016,
+	.emc_pmacro_ddll_short_cmd_0                     = 0x00000000,
+	.emc_pmacro_ddll_short_cmd_1                     = 0x00000000,
+	.emc_pmacro_ddll_short_cmd_2                     = 0x00000000,
+
+	.emc_pmacro_ddll_periodic_offset                 = 0x00000000,
+
+	/*
+	 * Specifies the delay after asserting CKE pin during a WarmBoot0
+	 * sequence (in microseconds)
+	 */
+	.warm_boot_wait                                  = 0x00000001,
+
+	.emc_odt_write                                   = 0x00000000,
+
+	/* Periodic ZQ calibration */
+
+	/*
+	 * Specifies the value for EMC_ZCAL_INTERVAL
+	 * Value 0 disables ZQ calibration
+	 */
+	.emc_zcal_interval                               = 0x00064000,
+	.emc_zcal_wait_cnt                               = 0x000900CC,
+	.emc_zcal_mrw_cmd                                = 0x8051004F,
+
+	/* DRAM initialization sequence flow control */
+	.emc_mrs_reset_dll                               = 0x00000000,
+	.emc_zcal_init_dev0                              = 0x80000001,
+	.emc_zcal_init_dev1                              = 0x00000000,
+	/*
+	 * Specifies the wait time after programming a ZQ initialization
+	 * command (in microseconds)
+	 */
+	.emc_zcal_init_wait                              = 0x00000001,
+	/*
+	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
+	 * and warm boot [bit 1]
+	 */
+	.emc_zcal_warm_cold_boot_enables                 = 0x00000003,
+
+	/*
+	 * Specifies the MRW command to LPDDR2 for ZQ calibration
+	 * on warmboot
+	 */
+	/* Is issued to both devices separately */
+	.emc_mrw_lpddr2zcal_warm_boot                    = 0x040A00AB,
+	/*
+	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
+	 * Is issued to both devices separately
+	 */
+	.emc_zqcal_ddr3_warm_boot                        = 0x00000011,
+	.emc_zqcal_lpddr4_warm_boot                      = 0x00000001,
+
+	/*
+	 * Specifies the wait time for ZQ calibration on warmboot
+	 * (in microseconds)
+	 */
+	.emc_zcal_warm_boot_wait                         = 0x00000001,
+	/*
+	 * Specifies the enable for DRAM Mode Register programming
+	 * at warm boot
+	 */
+	.emc_mrs_warm_boot_enable                        = 0x00000001,
+	.emc_mrs_reset_dll_wait                          = 0x00000000,
+	.emc_mrs_extra                                   = 0x00000000,
+	.emc_warm_boot_mrs_extra                         = 0x00000000,
+	.emc_emrs_ddr2_dll_enable                        = 0x00000000,
+	.emc_mrs_ddr2_dll_reset                          = 0x00000000,
+	.emc_emrs_ddr2_ocd_calib                         = 0x00000000,
+	/*
+	 * Specifies the wait between initializing DDR and setting OCD
+	 * calibration (in microseconds)
+	 */
+	.emc_ddr2_wait                                   = 0x00000000,
+	.emc_clken_override                              = 0x00000000,
+	/*
+	 * Specifies LOG2 of the extra refresh numbers after booting
+	 * Program 0 to disable
+	 */
+	.emc_extra_refresh_num                           = 0x00000002,
+	.emc_clken_override_allwarm_boot                 = 0x00000000,
+	.mc_clken_override_allwarm_boot                  = 0x00000000,
+	/* Specifies digital dll period, choosing between 4 to 64 ms */
+	.emc_cfg_dig_dll_period_warm_boot                = 0x00000003,
+
+	/* Pad controls */
+	.pmc_vddp_sel                                    = 0x00000001,
+	.pmc_vddp_sel_wait                               = 0x00000002,
+	.pmc_ddr_cfg                                     = 0x04220100,
+	.pmc_io_dpd3_req                                 = 0x4FAF9FFF,
+	.pmc_io_dpd3_req_wait                            = 0x00000001,
+	.pmc_io_dpd4_req_wait                            = 0x00000002,
+	.pmc_reg_short                                   = 0x00000000,
+	.pmc_no_io_power                                 = 0x00000000,
+	.pmc_ddr_ctrl_wait                               = 0x00000000,
+	.pmc_ddr_ctrl                                    = 0x0037FF9F,
+	.emc_acpd_control                                = 0x00000000,
+
+	.emc_swizzle_rank0_byte0                         = 0x76543201,
+	.emc_swizzle_rank0_byte1                         = 0x65324710,
+	.emc_swizzle_rank0_byte2                         = 0x25763410,
+	.emc_swizzle_rank0_byte3                         = 0x25673401,
+	.emc_swizzle_rank1_byte0                         = 0x32647501,
+	.emc_swizzle_rank1_byte1                         = 0x34567201,
+	.emc_swizzle_rank1_byte2                         = 0x56742310,
+	.emc_swizzle_rank1_byte3                         = 0x67324501,
+
+	.emc_txdsrvttgen                                 = 0x00000000,
+
+	.emc_data_brlshft0                               = 0x00249249,
+	.emc_data_brlshft1                               = 0x00249249,
+
+	.emc_dqs_brlshft0                                = 0x00000000,
+	.emc_dqs_brlshft1                                = 0x00000000,
+
+	.emc_cmd_brlshft0                                = 0x00000000,
+	.emc_cmd_brlshft1                                = 0x00000000,
+	.emc_cmd_brlshft2                                = 0x00000012,
+	.emc_cmd_brlshft3                                = 0x00000012,
+
+	.emc_quse_brlshft0                               = 0x00000000,
+	.emc_quse_brlshft1                               = 0x00000000,
+	.emc_quse_brlshft2                               = 0x00000000,
+	.emc_quse_brlshft3                               = 0x00000000,
+
+	.emc_dll_cfg0                                    = 0x1F134120,
+	.emc_dll_cfg1                                    = 0x00010014,
+
+	.emc_pmc_scratch1                                = 0x4FAF9FFF,
+	.emc_pmc_scratch2                                = 0x7FFFFFFF,
+	.emc_pmc_scratch3                                = 0x4036D71F,
+
+	.emc_pmacro_pad_cfg_ctrl                         = 0x00000000,
+	.emc_pmacro_vttgen_ctrl0                         = 0x00090000,
+	.emc_pmacro_vttgen_ctrl1                         = 0x00103400,
+	.emc_pmacro_vttgen_ctrl2                         = 0x00000000,
+	.emc_pmacro_dsr_vttgen_ctrl0                     = 0x00000009,
+	.emc_pmacro_brick_ctrl_rfu1                      = 0x00000000,
+	.emc_pmacro_cmd_brick_ctrl_fdpd                  = 0x00000000,
+	.emc_pmacro_brick_ctrl_rfu2                      = 0x00000000,
+	.emc_pmacro_data_brick_ctrl_fdpd                 = 0x00000000,
+	.emc_pmacro_bg_bias_ctrl0                        = 0x00000000,
+	.emc_pmacro_data_pad_rx_ctrl                     = 0x05050003,
+	.emc_pmacro_cmd_pad_rx_ctrl                      = 0x05000000,
+	.emc_pmacro_data_rx_term_mode                    = 0x00000210,
+	.emc_pmacro_cmd_rx_term_mode                     = 0x00002000,
+	.emc_pmacro_data_pad_tx_ctrl                     = 0x00000421,
+	.emc_pmacro_cmd_pad_tx_ctrl                      = 0x00000000,
+
+	.emc_cfg3                                        = 0x00000040,
+
+	.emc_pmacro_tx_pwrd0                             = 0x10000000,
+	.emc_pmacro_tx_pwrd1                             = 0x00000000,
+	.emc_pmacro_tx_pwrd2                             = 0x00000000,
+	.emc_pmacro_tx_pwrd3                             = 0x00000000,
+	.emc_pmacro_tx_pwrd4                             = 0x00400080,
+	.emc_pmacro_tx_pwrd5                             = 0x00801004,
+
+	.emc_config_sample_delay                         = 0x00000020,
+
+	.emc_pmacro_brick_mapping0                       = 0x28091081,
+	.emc_pmacro_brick_mapping1                       = 0x44A53293,
+	.emc_pmacro_brick_mapping2                       = 0x76678A5B,
+
+	.emc_pmacro_tx_sel_clk_src0                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src1                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src2                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src3                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src4                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src5                      = 0x00000000,
+
+	.emc_pmacro_perbit_fgcg_ctrl0                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl1                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl2                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl3                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl4                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl5                    = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl0                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl1                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl2                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl3                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl4                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl5                     = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl0                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl1                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl2                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl3                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl4                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl5                    = 0x00000000,
+
+	.emc_pmacro_data_pi_ctrl                         = 0x00001010,
+	.emc_pmacro_cmd_pi_ctrl                          = 0x00001010,
+
+	.emc_pmacro_ddll_bypass                          = 0xEF00EF00,
+
+	.emc_pmacro_ddll_pwrd0                           = 0x00000000,
+	.emc_pmacro_ddll_pwrd1                           = 0x00000000,
+	.emc_pmacro_ddll_pwrd2                           = 0x1C1C1C1C,
+
+	.emc_pmacro_cmd_ctrl0                            = 0x00000000,
+	.emc_pmacro_cmd_ctrl1                            = 0x00000000,
+	.emc_pmacro_cmd_ctrl2                            = 0x00000000,
+
+	/* DRAM size information */
+	.mc_emem_adr_cfg                                 = 0x00000000, // 1 Rank.
+	.mc_emem_adr_cfg_dev0                            = 0x00080302, // Rank 0 Density 1024MB.
+	.mc_emem_adr_cfg_dev1                            = 0x00080302, // Rank 1 Density 1024MB.
+	.mc_emem_adr_cfg_channel_mask                    = 0xFFFF2400,
+	.mc_emem_adr_cfg_bank_mask0                      = 0x6E574400,
+	.mc_emem_adr_cfg_bank_mask1                      = 0x39722800,
+	.mc_emem_adr_cfg_bank_mask2                      = 0x4B9C1000,
+	/*
+	 * Specifies the value for MC_EMEM_CFG which holds the external memory
+	 * size (in KBytes)
+	 */
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density.
+
+	/* MC arbitration configuration */
+	.mc_emem_arb_cfg                                 = 0x08000001,
+	.mc_emem_arb_outstanding_req                     = 0x8000004C,
+	.emc_emem_arb_refpb_hp_ctrl                      = 0x000A1020,
+	.emc_emem_arb_refpb_bank_ctrl                    = 0x80001028,
+
+	.mc_emem_arb_timing_rcd                          = 0x00000001,
+	.mc_emem_arb_timing_rp                           = 0x00000000,
+	.mc_emem_arb_timing_rc                           = 0x00000003,
+	.mc_emem_arb_timing_ras                          = 0x00000001,
+	.mc_emem_arb_timing_faw                          = 0x00000002,
+	.mc_emem_arb_timing_rrd                          = 0x00000001,
+	.mc_emem_arb_timing_rap2pre                      = 0x00000002,
+	.mc_emem_arb_timing_wap2pre                      = 0x00000005,
+	.mc_emem_arb_timing_r2r                          = 0x00000001,
+	.mc_emem_arb_timing_w2w                          = 0x00000001,
+	.mc_emem_arb_timing_r2w                          = 0x00000004,
+	.mc_emem_arb_timing_w2r                          = 0x00000005,
+	.mc_emem_arb_timing_rfcpb                        = 0x00000007,
+
+	.mc_emem_arb_da_turns                            = 0x02020000,
+	.mc_emem_arb_da_covers                           = 0x00030201,
+	.mc_emem_arb_misc0                               = 0x72A30504,
+	.mc_emem_arb_misc1                               = 0x70000F0F,
+	.mc_emem_arb_misc2                               = 0x00000000,
+
+	.mc_emem_arb_ring1_throttle                      = 0x001F0000,
+	.mc_emem_arb_override                            = 0x10000000,
+	.mc_emem_arb_override1                           = 0x00000000,
+	.mc_emem_arb_rsv                                 = 0xFF00FF00,
+
+	.mc_da_cfg0                                      = 0x00000001,
+	.mc_emem_arb_timing_ccdmw                        = 0x00000008,
+
+	.mc_clken_override                               = 0x00008000,
+
+	.mc_stat_control                                 = 0x00000000,
+	.mc_video_protect_bom                            = 0xFFF00000,
+	.mc_video_protect_bom_adr_hi                     = 0x00000000,
+	.mc_video_protect_size_mb                        = 0x00000000,
+	.mc_video_protect_vpr_override                   = 0xE4BAC343,
+	.mc_video_protect_vpr_override1                  = 0x06001ED3, // Add SE2, SE2B.
+	.mc_video_protect_gpu_override0                  = 0x00000000,
+	.mc_video_protect_gpu_override1                  = 0x00000000,
+	.mc_sec_carveout_bom                             = 0xFFF00000,
+	.mc_sec_carveout_adr_hi                          = 0x00000000,
+	.mc_sec_carveout_size_mb                         = 0x00000000,
+	.mc_video_protect_write_access                   = 0x00000000,
+	.mc_sec_carveout_protect_write_access            = 0x00000000,
+
+	.mc_generalized_carveout1_bom                    = 0x00000000,
+	.mc_generalized_carveout1_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout1_size_128kb             = 0x00000008,
+	.mc_generalized_carveout1_access0                = 0x00000000,
+	.mc_generalized_carveout1_access1                = 0x00000000,
+	.mc_generalized_carveout1_access2                = 0x00300000,
+	.mc_generalized_carveout1_access3                = 0x03000000,
+	.mc_generalized_carveout1_access4                = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout1_cfg0                   = 0x04000C76,
+
+	.mc_generalized_carveout2_bom                    = 0x00000000,
+	.mc_generalized_carveout2_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout2_size_128kb             = 0x00000002,
+	.mc_generalized_carveout2_access0                = 0x00000000,
+	.mc_generalized_carveout2_access1                = 0x00000000,
+	.mc_generalized_carveout2_access2                = 0x03000000,
+	.mc_generalized_carveout2_access3                = 0x00000000,
+	.mc_generalized_carveout2_access4                = 0x00000300,
+	.mc_generalized_carveout2_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout2_cfg0                   = 0x0440167E,
+
+	.mc_generalized_carveout3_bom                    = 0x00000000,
+	.mc_generalized_carveout3_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout3_size_128kb             = 0x00000000,
+	.mc_generalized_carveout3_access0                = 0x00000000,
+	.mc_generalized_carveout3_access1                = 0x00000000,
+	.mc_generalized_carveout3_access2                = 0x03000000,
+	.mc_generalized_carveout3_access3                = 0x00000000,
+	.mc_generalized_carveout3_access4                = 0x00000300,
+	.mc_generalized_carveout3_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout3_cfg0                   = 0x04401E7E,
+
+	.mc_generalized_carveout4_bom                    = 0x00000000,
+	.mc_generalized_carveout4_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout4_size_128kb             = 0x00000008,
+	.mc_generalized_carveout4_access0                = 0x00000000,
+	.mc_generalized_carveout4_access1                = 0x00000000,
+	.mc_generalized_carveout4_access2                = 0x00300000,
+	.mc_generalized_carveout4_access3                = 0x00000000,
+	.mc_generalized_carveout4_access4                = 0x000000C0,
+	.mc_generalized_carveout4_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout4_cfg0                   = 0x04002446,
+
+	.mc_generalized_carveout5_bom                    = 0x00000000,
+	.mc_generalized_carveout5_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout5_size_128kb             = 0x00000008,
+	.mc_generalized_carveout5_access0                = 0x00000000,
+	.mc_generalized_carveout5_access1                = 0x00000000,
+	.mc_generalized_carveout5_access2                = 0x00300000,
+	.mc_generalized_carveout5_access3                = 0x00000000,
+	.mc_generalized_carveout5_access4                = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout5_cfg0                   = 0x04002C46,
+
+	/* Specifies enable for CA training */
+	.emc_ca_training_enable                          = 0x00000000,
+	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
+	.swizzle_rank_byte_encode                        = 0x000000EC,
+
+	/* Specifies enable and offset for patched boot rom write */
+	.boot_rom_patch_control                          = 0x00000000,
+	/* Specifies data for patched boot rom write */
+	.boot_rom_patch_data                             = 0x00000000,
+
+	.mc_mts_carveout_bom                             = 0xFFF00000,
+	.mc_mts_carveout_adr_hi                          = 0x00000000,
+	.mc_mts_carveout_size_mb                         = 0x00000000,
+	.mc_mts_carveout_reg_ctrl                        = 0x00000000,
+
+	/* Specifies the untranslated memory access control */
+	.mc_untranslated_region_check                    = 0x00000000,
+
+	/* Just a place holder for special usage when there is no BCT for certain registers */
+	.bct_na                                          = 0x00000000,
+};
+
+//!TODO Find out what mc_video_protect_gpu_override0 and mc_video_protect_gpu_override1 new bits are.
+
+static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
+
+	// Samsung LPDDR4X 4GB X1X2 for prototype Iowa.
+	{ 0x000E0022, 0x3AC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
+	{ 0x001B0010, 0x3B0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank0_5.
+	{ 0x000E0022, 0x3C4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
+	{ 0x001B0010, 0x3C8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank1_5.
+	{ 0x00490043, 0x3CC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
+	{ 0x00420045, 0x3D0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
+	{ 0x00490047, 0x3D4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
+	{ 0x00460047, 0x3D8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_3.
+	{ 0x00000016, 0x3DC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
+	{ 0x00100000, 0x3E0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_5.
+	{ 0x00490043, 0x3E4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
+	{ 0x00420045, 0x3E8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
+	{ 0x00490047, 0x3EC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
+	{ 0x00460047, 0x3F0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_3.
+	{ 0x00000016, 0x3F4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
+	{ 0x00100000, 0x3F8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_5.
+	{ 0x00220022, 0x41C / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_0.
+	{ 0x000E000E, 0x420 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_1.
+	{ 0x00100010, 0x424 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_2.
+	{ 0x001B001B, 0x428 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_3.
+	{ 0x00000022, 0x42C / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_4.
+
+	// Samsung LPDDR4X 8GB K4UBE3D4AM-MGCJ Die-M for SDEV Iowa and Hoag.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_auto_cal_vref_sel0.
+	{ 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_adr_cfg. 2 Ranks.
+	{ 0x00000006, 0x1CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_quse.
+	{ 0x00000005, 0x1D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_quse_width.
+	{ 0x00000003, 0x1DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_einput.
+	{ 0x0000000C, 0x1E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_einput_duration.
+	{ 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw1.
+	{ 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw2.
+	{ 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw3.
+	{ 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw6.
+	{ 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw8.
+	{ 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw9.
+	{ 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw10.
+	{ 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw12.
+	{ 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw13.
+	{ 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw14.
+	{ 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw_extra.
+	{ 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_dev_select. Both devices.
+	{ 0x35353535, 0x350 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_vref_dq_0.
+	{ 0x35353535, 0x354 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_vref_dq_1.
+	{ 0x00100010, 0x3FC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_0.
+	{ 0x00100010, 0x400 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_1.
+	{ 0x00100010, 0x404 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_2.
+	{ 0x00100010, 0x408 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_3.
+	{ 0x00100010, 0x40C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_0.
+	{ 0x00100010, 0x410 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_1.
+	{ 0x00100010, 0x414 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_2.
+	{ 0x00100010, 0x418 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_3.
+	{ 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_zcal_mrw_cmd.
+	{ 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_zcal_init_dev1.
+	{ 0x00000000, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_tx_pwrd4.
+	{ 0x00001000, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_tx_pwrd5.
+	{ 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_adr_cfg. 2 Ranks.
+	{ 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_cfg. 8GB total density.
+	{ 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_arb_timing_r2r.
+	{ 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_arb_da_turns.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_video_protect_gpu_override1.
+
+	// Micron LPDDR4X 4GB MT53D1024M32D1NP-053-WT:E Die-E for retail Iowa and Hoag.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_auto_cal_vref_sel0.
+	{ 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_mrw14.
+	{ 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_dyn_self_ref_control.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // mc_video_protect_gpu_override1.
+
+	// Samsung LPDDR4X 4GB (Y01) Die-? for Iowa.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_auto_cal_vref_sel0.
+	{ 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_mrw14.
+	{ 0x80000713, 0x32C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_dyn_self_ref_control.
+	{ 0x32323232, 0x350 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_vref_dq_0.
+	{ 0x32323232, 0x354 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_vref_dq_1.
+	{ 0x000F0018, 0x3AC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
+	{ 0x000F0018, 0x3C4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
+	{ 0x00440048, 0x3CC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
+	{ 0x00440045, 0x3D0 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
+	{ 0x00470047, 0x3D4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
+	{ 0x0005000D, 0x3DC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
+	{ 0x00440048, 0x3E4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
+	{ 0x00440045, 0x3E8 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
+	{ 0x00470047, 0x3EC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
+	{ 0x0005000D, 0x3F4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
+	{ 0x00780078, 0x3FC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_0.
+	{ 0x00780078, 0x400 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_1.
+	{ 0x00780078, 0x404 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_2.
+	{ 0x00780078, 0x408 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_3.
+	{ 0x00780078, 0x40C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_0.
+	{ 0x00780078, 0x410 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_1.
+	{ 0x00780078, 0x414 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_2.
+	{ 0x00780078, 0x418 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_3.
+	{ 0x00180018, 0x41C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ddll_long_cmd_0.
+	{ 0x000F000F, 0x420 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ddll_long_cmd_1.
+	{ 0x00000018, 0x42C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ddll_long_cmd_4.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // mc_video_protect_gpu_override1.
+
+	// Samsung LPDDR4X 4GB K4U6E3S4AA-MGCL 10nm-class (1y-X03) Die-A for retail Iowa, Hoag and Aula.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_auto_cal_vref_sel0.
+	{ 0x00000006, 0x1CC / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_quse.
+	{ 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_quse_width.
+	{ 0x00000003, 0x1DC / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_einput.
+	{ 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_einput_duration.
+	{ 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_mrw14.
+	{ 0x80000713, 0x32C / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_dyn_self_ref_control.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // mc_video_protect_gpu_override1.
+
+	// Samsung LPDDR4X 8GB K4UBE3D4AA-MGCL 10nm-class (1y-X03) Die-A for SDEV Iowa, Hoag and Aula.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_auto_cal_vref_sel0.
+	{ 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_adr_cfg. 2 Ranks.
+	{ 0x00000006, 0x1CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_quse.
+	{ 0x00000005, 0x1D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_quse_width.
+	{ 0x00000003, 0x1DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_einput.
+	{ 0x0000000C, 0x1E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_einput_duration.
+	{ 0x00000008, 0x24C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_tfaw.
+	{ 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw1.
+	{ 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw2.
+	{ 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw3.
+	{ 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw6.
+	{ 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw8.
+	{ 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw9.
+	{ 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw10.
+	{ 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw12.
+	{ 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw13.
+	{ 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw14.
+	{ 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw_extra.
+	{ 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_dev_select. Both devices.
+	{ 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_zcal_mrw_cmd.
+	{ 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_zcal_init_dev1.
+	{ 0x00000000, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_pmacro_tx_pwrd4.
+	{ 0x00001000, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_pmacro_tx_pwrd5.
+	{ 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_adr_cfg. 2 Ranks.
+	{ 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_cfg. 8GB total density.
+	{ 0x00000001, 0x670 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_arb_timing_faw.
+	{ 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_arb_timing_r2r.
+	{ 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_arb_da_turns.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_video_protect_gpu_override1.
+
+	// Samsung LPDDR4X 4GB 10nm-class (1y-Y01) Die-? for Iowa.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_auto_cal_vref_sel0.
+	{ 0x00000008, 0x24C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_tfaw.
+	{ 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_mrw14.
+	{ 0x80000713, 0x32C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_dyn_self_ref_control.
+	{ 0x000F0018, 0x3AC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
+	{ 0x000F0018, 0x3C4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
+	{ 0x00440048, 0x3CC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
+	{ 0x00440045, 0x3D0 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
+	{ 0x00470047, 0x3D4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
+	{ 0x0005000D, 0x3DC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
+	{ 0x00440048, 0x3E4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
+	{ 0x00440045, 0x3E8 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
+	{ 0x00470047, 0x3EC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
+	{ 0x0005000D, 0x3F4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
+	{ 0x00180018, 0x41C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_0.
+	{ 0x000F000F, 0x420 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_1.
+	{ 0x00000018, 0x42C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_4.
+	{ 0x00000001, 0x670 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // mc_emem_arb_timing_faw.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override1.
+
+	// Samsung LPDDR4X 8GB 10nm-class (1y-Y01) Die-? for SDEV Iowa.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_auto_cal_vref_sel0.
+	{ 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_adr_cfg. 2 Ranks.
+	{ 0x00000008, 0x24C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_tfaw.
+	{ 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw1.
+	{ 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw2.
+	{ 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw3.
+	{ 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw6.
+	{ 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw8.
+	{ 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw9.
+	{ 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw10.
+	{ 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw12.
+	{ 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw13.
+	{ 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw14.
+	{ 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw_extra.
+	{ 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_dev_select. Both devices.
+	{ 0x32323232, 0x350 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ib_vref_dq_0.
+	{ 0x32323232, 0x354 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ib_vref_dq_1.
+	{ 0x000F0018, 0x3AC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
+	{ 0x000F0018, 0x3C4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
+	{ 0x00440048, 0x3CC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
+	{ 0x00440045, 0x3D0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
+	{ 0x00470047, 0x3D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
+	{ 0x0005000D, 0x3DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
+	{ 0x00440048, 0x3E4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
+	{ 0x00440045, 0x3E8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
+	{ 0x00470047, 0x3EC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
+	{ 0x0005000D, 0x3F4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
+	{ 0x00180018, 0x41C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_0.
+	{ 0x000F000F, 0x420 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_1.
+	{ 0x00000018, 0x42C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_4.
+	{ 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_zcal_mrw_cmd.
+	{ 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_zcal_init_dev1.
+	{ 0x00000000, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_tx_pwrd4.
+	{ 0x00001000, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_tx_pwrd5.
+	{ 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_adr_cfg. 2 Ranks.
+	{ 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_cfg. 8GB total density.
+	{ 0x00000001, 0x670 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_arb_timing_faw.
+	{ 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_arb_timing_r2r.
+	{ 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_arb_da_turns.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override1.
+
+/*
+	// Samsung LPDDR4X 8GB 10nm-class (1y-A01) Die-? for SDEV Aula?
+	{ 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_adr_cfg. 2 Ranks.
+	{ 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw1.
+	{ 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw2.
+	{ 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw3.
+	{ 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw6.
+	{ 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw8.
+	{ 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw9.
+	{ 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw10.
+	{ 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw12.
+	{ 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw13.
+	{ 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw14.
+	{ 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw_extra.
+	{ 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_dev_select. Both devices.
+	{ 0x35353535, 0x350 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dq_0.
+	{ 0x35353535, 0x354 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dq_1.
+	{ 0x35353535, 0x358 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dqs_0.
+	{ 0x35353535, 0x35C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dqs_1.
+	{ 0x00480048, 0x3FC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_0.
+	{ 0x00480048, 0x400 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_1.
+	{ 0x00480048, 0x404 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_2.
+	{ 0x00480048, 0x408 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_3.
+	{ 0x00480048, 0x40C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_0.
+	{ 0x00480048, 0x410 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_1.
+	{ 0x00480048, 0x414 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_2.
+	{ 0x00480048, 0x418 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_3.
+	{ 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_zcal_mrw_cmd.
+	{ 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_zcal_init_dev1.
+	{ 0x00010100, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_tx_pwrd4.
+	{ 0x00400010, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_tx_pwrd5.
+	{ 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_adr_cfg. 2 Ranks.
+	{ 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_cfg. 8GB total density.
+	{ 0x00000002, 0x670 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_timing_faw.
+	{ 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_timing_r2r.
+	{ 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_da_turns.
+*/
+
+	// Micron LPDDR4X 4GB MT53D1024M32D1NP-053-WT:F 10nm-class (1y-01) Die-F for Newer Iowa/Hoag/Aula.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_auto_cal_vref_sel0.
+	{ 0x00000006, 0x1CC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_quse.
+	{ 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_quse_width.
+	{ 0x00000003, 0x1DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_einput.
+	{ 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_einput_duration.
+	{ 0x00000008, 0x24C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_tfaw.
+	{ 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_mrw14.
+	{ 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_dyn_self_ref_control.
+	{ 0x00000001, 0x670 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // mc_emem_arb_timing_faw.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // mc_video_protect_gpu_override1.
+
+	// Hynix LPDDR4X 4GB 10nm-class (1y-01) Die-A for Unknown Iowa/Hoag/Aula.
+	{ 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_auto_cal_config2.
+	{ 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_auto_cal_vref_sel0.
+	{ 0x00000006, 0x1CC / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_quse.
+	{ 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_quse_width.
+	{ 0x00000003, 0x1DC / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_einput.
+	{ 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_einput_duration.
+	{ 0x00000008, 0x24C / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_tfaw.
+	{ 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_mrw14.
+	{ 0x80000713, 0x32C / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_dyn_self_ref_control.
+	{ 0x00000001, 0x670 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_emem_arb_timing_faw.
+	{ 0xE4FACB43, 0x6D4 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_vpr_override. + TSEC, NVENC.
+	{ 0x0600FED3, 0x6D8 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_vpr_override1. + TSECB, TSEC1, TSECB1.
+	{ 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_gpu_override0.
+	{ 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_gpu_override1.
+
+	//!TODO: Too many duplicates.
+};

bdk/mem/sdram_lp0.c

@@ -2,7 +2,7 @@
  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  * Copyright 2014 Google Inc.
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -17,16 +17,7 @@
 #include <soc/t210.h>
 #include <soc/pmc_lp0_t210.h>
 #include <mem/sdram_lp0_param_t210.h>
-
+#include <mem/sdram_lp0_param_t210b01.h>
-/*
- * This function reads SDRAM parameters from the common BCT format and
- * writes them into PMC scratch registers (where the BootROM expects them
- * on LP0 resume).
- */
-void sdram_lp0_save_params(const void *params)
-{
-	struct sdram_params *sdram = (struct sdram_params *)params;
-	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)PMC_BASE;
 
 #define pack(src, src_bits, dst, dst_bits) { \
 	u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
@@ -46,6 +37,16 @@ void sdram_lp0_save_params(const void *params)
 /* 32 bits version c macro */
 #define c32(value, pmcreg) pmc->pmcreg = value
 
+/*
+ * This function reads SDRAM parameters from the common BCT format and
+ * writes them into PMC scratch registers (where the BootROM expects them
+ * on LP0 resume).
+ */
+static void _sdram_lp0_save_params_t210(const void *params)
+{
+	struct sdram_params_t210 *sdram = (struct sdram_params_t210 *)params;
+	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)PMC_BASE;
+
 	//TODO: pkg1.1 (1.X - 3.X) reads them from MC.
 	// Patch carveout parameters.
 	/*sdram->McGeneralizedCarveout1Bom = 0;
@@ -1124,3 +1125,414 @@ void sdram_lp0_save_params(const void *params)
 	c32(0, scratch4);
 	s(PllMStableTime, 9:0, scratch4, 9:0);
 }
+/*
+#pragma GCC diagnostic ignored "-Wparentheses"
+
+static void _sdram_lp0_save_params_t210b01(const void *params)
+{
+	struct sdram_params_t210b01 *sdram = (struct sdram_params_t210b01 *)params;
+	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)PMC_BASE;
+
+	u32 tmp = 0;
+
+	sdram->mc_generalized_carveout1_cfg0 = 0;
+	sdram->mc_generalized_carveout2_cfg0 = 0;
+	sdram->mc_generalized_carveout3_cfg0 = 0;
+	sdram->mc_generalized_carveout4_cfg0 = 0;
+	sdram->mc_generalized_carveout5_cfg0 = 0;
+
+	// Patch SDRAM parameters.
+	u32 t0 = sdram->emc_swizzle_rank0_byte0 << 5 >> 29 > sdram->emc_swizzle_rank0_byte0 << 1 >> 29;
+	u32 t1 = (t0 & 0xFFFFFFEF) | ((sdram->emc_swizzle_rank1_byte0 << 5 >> 29 > sdram->emc_swizzle_rank1_byte0 << 1 >> 29) << 4);
+	u32 t2 = (t1 & 0xFFFFFFFD) | ((sdram->emc_swizzle_rank0_byte1 << 5 >> 29 > sdram->emc_swizzle_rank0_byte1 << 1 >> 29) << 1);
+	u32 t3 = (t2 & 0xFFFFFFDF) | ((sdram->emc_swizzle_rank1_byte1 << 5 >> 29 > sdram->emc_swizzle_rank1_byte1 << 1 >> 29) << 5);
+	u32 t4 = (t3 & 0xFFFFFFFB) | ((sdram->emc_swizzle_rank0_byte2 << 5 >> 29 > sdram->emc_swizzle_rank0_byte2 << 1 >> 29) << 2);
+	u32 t5 = (t4 & 0xFFFFFFBF) | ((sdram->emc_swizzle_rank1_byte2 << 5 >> 29 > sdram->emc_swizzle_rank1_byte2 << 1 >> 29) << 6);
+	u32 t6 = (t5 & 0xFFFFFFF7) | ((sdram->emc_swizzle_rank0_byte3 << 5 >> 29 > sdram->emc_swizzle_rank0_byte3 << 1 >> 29) << 3);
+	u32 t7 = (t6 & 0xFFFFFF7F) | ((sdram->emc_swizzle_rank1_byte3 << 5 >> 29 > sdram->emc_swizzle_rank1_byte3 << 1 >> 29) << 7);
+	sdram->swizzle_rank_byte_encode = t7;
+	sdram->emc_bct_spare2 = 0x40000DD8;
+	sdram->emc_bct_spare3 = t7;
+
+	s(emc_clock_source, 7:0, scratch6, 15:8);
+	s(emc_clock_source_dll, 7:0, scratch6, 23:16);
+	s(emc_clock_source, 31:29, scratch6, 26:24);
+	s(emc_clock_source_dll, 31:29, scratch6, 29:27);
+	s(emc_clock_source_dll, 11:10, scratch6, 31:30);
+	pmc->scratch7 = (sdram->emc_rc << 24) | ((sdram->emc_zqcal_lpddr4_warm_boot << 27 >> 31 << 23) | ((sdram->emc_zqcal_lpddr4_warm_boot << 30 >> 31 << 22) | ((sdram->emc_zqcal_lpddr4_warm_boot << 21) & 0x3FFFFF | ((sdram->clk_rst_pllm_misc20_override << 20) & 0x1FFFFF | ((sdram->clk_rst_pllm_misc20_override << 28 >> 31 << 19) | ((sdram->clk_rst_pllm_misc20_override << 27 >> 31 << 18) | ((sdram->clk_rst_pllm_misc20_override << 26 >> 31 << 17) | ((sdram->clk_rst_pllm_misc20_override << 21 >> 31 << 16) | ((sdram->clk_rst_pllm_misc20_override << 20 >> 31 << 15) | ((sdram->clk_rst_pllm_misc20_override << 19 >> 31 << 14) | ((sdram->clk_rst_pllm_misc20_override << 18 >> 31 << 13) | ((sdram->emc_clock_source << 15 >> 31 << 12) | ((sdram->emc_clock_source << 11 >> 31 << 11) | ((sdram->emc_clock_source << 12 >> 31 << 10) | ((sdram->emc_clock_source << 6 >> 31 << 9) | ((sdram->emc_clock_source << 16 >> 31 << 8) | ((32 * sdram->emc_clock_source >> 31 << 7) | ((16 * sdram->emc_clock_source >> 31 << 6) | (16 * (sdram->emc_zqcal_lpddr4_warm_boot >> 30) | (4 * (sdram->clk_rst_pllm_misc20_override << 29 >> 30) | ((sdram->clk_rst_pllm_misc20_override << 22 >> 30) | 4 * (pmc->scratch7 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFFFFFF;
+	pmc->scratch8 = (sdram->emc_pmacro_bg_bias_ctrl0 << 18 >> 30 << 30) | ((4 * pmc->scratch8) >> 2);
+	pmc->scratch14 = ((u8)(sdram->emc_cfg_pipe_clk) << 31) | (2 * (((u8)(sdram->emc_fdpd_ctrl_cmd_no_ramp) << 30) | pmc->scratch14 & 0xBFFFFFFF) >> 1);
+	s(emc_qrst, 6:0, scratch15, 26:20);
+	s(emc_qrst, 20:16, scratch15, 31:27);
+	s(emc_pmacro_cmd_tx_drive, 5:0, scratch16, 25:20);
+	s(emc_pmacro_cmd_tx_drive, 13:8, scratch16, 31:26);
+	pmc->scratch17 = (16 * sdram->emc_fbio_cfg8 >> 31 << 31) | (2 * ((32 * sdram->emc_fbio_cfg8 >> 31 << 30) | ((sdram->emc_fbio_cfg8 << 6 >> 31 << 29) | ((sdram->emc_fbio_cfg8 << 7 >> 31 << 28) | ((sdram->emc_fbio_cfg8 << 8 >> 31 << 27) | ((sdram->emc_fbio_cfg8 << 9 >> 31 << 26) | ((sdram->emc_fbio_cfg8 << 10 >> 31 << 25) | ((sdram->emc_fbio_cfg8 << 11 >> 31 << 24) | ((sdram->emc_fbio_cfg8 << 12 >> 31 << 23) | ((sdram->emc_fbio_cfg8 << 13 >> 31 << 22) | ((sdram->emc_fbio_cfg8 << 14 >> 31 << 21) | ((sdram->emc_fbio_cfg8 << 15 >> 31 << 20) | pmc->scratch17 & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch18 = ((u16)(sdram->emc_txsr_dll) << 20) | pmc->scratch18 & 0xFFFFF;
+	pmc->scratch19 = (sdram->emc_txdsrvttgen << 20) | pmc->scratch19 & 0xFFFFF;
+	s32(emc_cfg_rsv, scratch22);
+	s32(emc_auto_cal_config, scratch23);
+	s32(emc_auto_cal_vref_sel0, scratch24);
+	s32(emc_pmacro_brick_ctrl_rfu1, scratch25);
+	s32(emc_pmacro_brick_ctrl_rfu2, scratch26);
+	s32(emc_pmc_scratch1, scratch27);
+	s32(emc_pmc_scratch2, scratch28);
+	s32(emc_pmc_scratch3, scratch29);
+	pmc->scratch30 = (sdram->emc_pmacro_perbit_rfu_ctrl0 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl0 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl0 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl0 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl0 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl0 & 3 | 4 * (pmc->scratch30 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch31 = (sdram->emc_pmacro_perbit_rfu_ctrl1 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl1 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl1 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl1 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl1 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl1 & 3 | 4 * (pmc->scratch31 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch32 = (sdram->emc_pmacro_perbit_rfu_ctrl2 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl2 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl2 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl2 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl2 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl2 & 3 | 4 * (pmc->scratch32 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch33 = (sdram->emc_pmacro_perbit_rfu_ctrl3 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl3 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl3 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl3 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl3 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl3 & 3 | 4 * (pmc->scratch33 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch40 = (sdram->emc_pmacro_perbit_rfu_ctrl4 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl4 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl4 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl4 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl4 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl4 & 3 | 4 * (pmc->scratch40 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch42 = (sdram->emc_pmacro_perbit_rfu_ctrl5 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl5 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl5 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl5 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl5 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl5 & 3 | 4 * (pmc->scratch42 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch44 = (sdram->mc_emem_arb_da_turns >> 24 << 24) | ((sdram->mc_emem_arb_da_turns >> 16 << 16) | ((sdram->mc_emem_arb_da_turns << 16 >> 24 << 8) | (sdram->mc_emem_arb_da_turns & 0xFF | (pmc->scratch44 >> 8 << 8)) & 0xFFFF00FF) & 0xFF00FFFF) & 0xFFFFFF;
+	pmc->scratch64 = ((u16)(sdram->mc_emem_arb_misc2) << 31) | (2 * ((sdram->emc_fbio_spare << 30) | ((sdram->emc_fbio_spare << 24 >> 26 << 24) | ((sdram->emc_fbio_spare << 16 >> 24 << 16) | ((sdram->emc_fbio_spare << 8 >> 24 << 8) | ((sdram->emc_fbio_spare >> 24) | (pmc->scratch64 >> 8 << 8)) & 0xFFFF00FF) & 0xFF00FFFF) & 0xC0FFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch65 = ((u16)(sdram->mc_da_cfg0) << 31 >> 1) | ((2 * sdram->mc_emem_arb_misc0 >> 29 << 27) | ((16 * sdram->mc_emem_arb_misc0 >> 31 << 26) | ((32 * sdram->mc_emem_arb_misc0 >> 26 << 20) | ((sdram->mc_emem_arb_misc0 << 11 >> 27 << 15) | ((sdram->mc_emem_arb_misc0 << 17 >> 25 << 8) | ((u8)sdram->mc_emem_arb_misc0 | (pmc->scratch65 >> 8 << 8)) & 0xFFFF80FF) & 0xFFF07FFF) & 0xFC0FFFFF) & 0xFBFFFFFF) & 0xC7FFFFFF) & 0xBFFFFFFF;
+	pmc->scratch66 = (sdram->emc_fdpd_ctrl_cmd >> 30 << 27) | ((4 * sdram->emc_fdpd_ctrl_cmd >> 31 << 26) | ((8 * sdram->emc_fdpd_ctrl_cmd >> 27 << 21) | ((sdram->emc_fdpd_ctrl_cmd << 8 >> 28 << 17) | ((sdram->emc_fdpd_ctrl_cmd << 15 >> 27 << 12) | ((sdram->emc_fdpd_ctrl_cmd << 20 >> 28 << 8) | ((u8)sdram->emc_fdpd_ctrl_cmd | (pmc->scratch66 >> 8 << 8)) & 0xFFFFF0FF) & 0xFFFE0FFF) & 0xFFE1FFFF) & 0xFC1FFFFF) & 0xFBFFFFFF) & 0xE7FFFFFF;
+	pmc->scratch67 = ((u8)(sdram->emc_burst_refresh_num) << 28) | ((16 * sdram->emc_auto_cal_config2 >> 30 << 26) | ((sdram->emc_auto_cal_config2 << 6 >> 30 << 24) | ((sdram->emc_auto_cal_config2 << 8 >> 30 << 22) | ((sdram->emc_auto_cal_config2 << 10 >> 30 << 20) | ((sdram->emc_auto_cal_config2 << 12 >> 30 << 18) | ((sdram->emc_auto_cal_config2 << 14 >> 30 << 16) | ((sdram->emc_auto_cal_config2 << 16 >> 30 << 14) | ((sdram->emc_auto_cal_config2 << 18 >> 30 << 12) | ((sdram->emc_auto_cal_config2 << 20 >> 30 << 10) | ((sdram->emc_auto_cal_config2 << 22 >> 30 << 8) | ((sdram->emc_auto_cal_config2 << 24 >> 30 << 6) | (16 * (sdram->emc_auto_cal_config2 << 26 >> 30) | (4 * (sdram->emc_auto_cal_config2 << 28 >> 30) | (sdram->emc_auto_cal_config2 & 3 | 4 * (pmc->scratch67 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xFFFFFFF;
+	pmc->scratch68 = ((u8)(sdram->emc_tppd) << 28) | ((sdram->emc_cfg_dig_dll >> 31 << 27) | ((2 * sdram->emc_cfg_dig_dll >> 31 << 26) | ((16 * sdram->emc_cfg_dig_dll >> 31 << 25) | ((sdram->emc_cfg_dig_dll << 6 >> 22 << 15) | ((sdram->emc_cfg_dig_dll << 16 >> 31 << 14) | ((sdram->emc_cfg_dig_dll << 17 >> 31 << 13) | ((sdram->emc_cfg_dig_dll << 18 >> 30 << 11) | ((sdram->emc_cfg_dig_dll << 21 >> 29 << 8) | ((sdram->emc_cfg_dig_dll << 24 >> 30 << 6) | (32 * (sdram->emc_cfg_dig_dll << 26 >> 31) | (16 * (sdram->emc_cfg_dig_dll << 27 >> 31) | (8 * (sdram->emc_cfg_dig_dll << 28 >> 31) | (4 * (sdram->emc_cfg_dig_dll << 29 >> 31) | (2 * (sdram->emc_cfg_dig_dll << 30 >> 31) | (sdram->emc_cfg_dig_dll & 1 | 2 * (pmc->scratch68 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFF3F) & 0xFFFFF8FF) & 0xFFFFE7FF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFE007FFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xFFFFFFF;
+	pmc->scratch69 = (sdram->emc_r2r << 28) | ((sdram->emc_fdpd_ctrl_dq >> 30 << 26) | ((8 * sdram->emc_fdpd_ctrl_dq >> 27 << 21) | ((sdram->emc_fdpd_ctrl_dq << 8 >> 28 << 17) | ((sdram->emc_fdpd_ctrl_dq << 15 >> 27 << 12) | ((sdram->emc_fdpd_ctrl_dq << 20 >> 28 << 8) | ((u8)sdram->emc_fdpd_ctrl_dq | (pmc->scratch69 >> 8 << 8)) & 0xFFFFF0FF) & 0xFFFE0FFF) & 0xFFE1FFFF) & 0xFC1FFFFF) & 0xF3FFFFFF) & 0xFFFFFFF;
+	pmc->scratch70 = (sdram->emc_w2w << 28) | ((2 * sdram->emc_pmacro_ib_vref_dq_0 >> 25 << 21) | ((sdram->emc_pmacro_ib_vref_dq_0 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ib_vref_dq_0 << 17 >> 25 << 7) | (sdram->emc_pmacro_ib_vref_dq_0 & 0x7F | (pmc->scratch70 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xFFFFFFF;
+	pmc->scratch71 = (sdram->emc_pmacro_vttgen_ctrl0 << 12 >> 28 << 28) | ((2 * sdram->emc_pmacro_ib_vref_dq_1 >> 25 << 21) | ((sdram->emc_pmacro_ib_vref_dq_1 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ib_vref_dq_1 << 17 >> 25 << 7) | ((pmc->scratch71 >> 7 << 7) | sdram->emc_pmacro_ib_vref_dq_1 & 0x7F) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xFFFFFFF;
+	pmc->scratch72 = (((sdram->emc_pmacro_ib_vref_dqs_0 << 17 >> 25 << 7) | ((pmc->scratch72 >> 7 << 7) | sdram->emc_pmacro_ib_vref_dqs_0 & 0x7F) & 0xFFFFC07F) & 0xFFE03FFF | (sdram->emc_pmacro_ib_vref_dqs_0 << 9 >> 25 << 14)) & 0xF01FFFFF | (2 * sdram->emc_pmacro_ib_vref_dqs_0 >> 25 << 21);
+	pmc->scratch73 = (2 * sdram->emc_pmacro_ib_vref_dqs_1 >> 25 << 21) | ((sdram->emc_pmacro_ib_vref_dqs_1 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ib_vref_dqs_1 << 17 >> 25 << 7) | ((pmc->scratch73 >> 7 << 7) | sdram->emc_pmacro_ib_vref_dqs_1 & 0x7F) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF;
+	pmc->scratch74 = (2 * sdram->emc_pmacro_ddll_short_cmd_0 >> 25 << 21) | ((sdram->emc_pmacro_ddll_short_cmd_0 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ddll_short_cmd_0 << 17 >> 25 << 7) | (sdram->emc_pmacro_ddll_short_cmd_0 & 0x7F | (pmc->scratch74 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF;
+	pmc->scratch75 = (2 * sdram->emc_pmacro_ddll_short_cmd_1 >> 25 << 21) | ((sdram->emc_pmacro_ddll_short_cmd_1 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ddll_short_cmd_1 << 17 >> 25 << 7) | (sdram->emc_pmacro_ddll_short_cmd_1 & 0x7F | (pmc->scratch75 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF;
+	pmc->scratch76 = (sdram->emc_rp << 26) | ((4 * sdram->emc_dll_cfg0 >> 31 << 25) | ((8 * sdram->emc_dll_cfg0 >> 31 << 24) | ((16 * sdram->emc_dll_cfg0 >> 28 << 20) | ((sdram->emc_dll_cfg0 << 8 >> 28 << 16) | ((sdram->emc_dll_cfg0 << 12 >> 28 << 12) | ((sdram->emc_dll_cfg0 << 16 >> 28 << 8) | ((sdram->emc_dll_cfg0 << 20 >> 24) | (pmc->scratch76 >> 8 << 8)) & 0xFFFFF0FF) & 0xFFFF0FFF) & 0xFFF0FFFF) & 0xFF0FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0x3FFFFFF;
+	tmp = (sdram->emc_pmacro_tx_pwrd0 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd0 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd0 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd0 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd0 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd0 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd0 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd0 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd0 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd0 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd0 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd0 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd0 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd0 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd0 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd0 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd0 & 1 | 2 * (pmc->scratch77 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF;
+	pmc->scratch77 = (sdram->emc_r2w << 26) | ((4 * sdram->emc_pmacro_tx_pwrd0 >> 31 << 25) | ((8 * sdram->emc_pmacro_tx_pwrd0 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd0 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd0 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd0 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd0 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd0 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd0 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd0 << 11 >> 31 << 17) | tmp & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0x3FFFFFF;
+	tmp = ((8 * sdram->emc_pmacro_tx_pwrd1 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd1 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd1 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd1 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd1 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd1 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd1 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd1 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd1 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd1 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd1 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd1 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd1 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd1 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd1 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd1 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd1 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd1 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd1 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd1 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd1 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd1 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd1 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd1 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd1 & 1 | 2 * (pmc->scratch78 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF;
+	pmc->scratch78 = (sdram->emc_w2r << 26) | ((4 * sdram->emc_pmacro_tx_pwrd1 >> 31 << 25) | tmp) & 0x3FFFFFF;
+	tmp = ((8 * sdram->emc_pmacro_tx_pwrd2 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd2 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd2 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd2 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd2 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd2 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd2 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd2 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd2 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd2 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd2 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd2 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd2 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd2 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd2 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd2 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd2 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd2 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd2 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd2 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd2 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd2 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd2 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd2 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd2 & 1 | 2 * (pmc->scratch79 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF;
+	pmc->scratch79 = (sdram->emc_r2p << 26) | ((4 * sdram->emc_pmacro_tx_pwrd2 >> 31 << 25) | tmp) & 0x3FFFFFF;
+	tmp = (sdram->emc_pmacro_tx_pwrd3 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd3 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd3 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd3 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd3 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd3 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd3 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd3 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd3 & 1 | 2 * (pmc->scratch80 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF;
+	pmc->scratch80 = ((u8)(sdram->emc_ccdmw) << 26) | ((4 * sdram->emc_pmacro_tx_pwrd3 >> 31 << 25) | ((8 * sdram->emc_pmacro_tx_pwrd3 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd3 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd3 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd3 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd3 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd3 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd3 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd3 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd3 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd3 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd3 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd3 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd3 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd3 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd3 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd3 << 22 >> 31 << 9) | tmp & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0x3FFFFFF;
+	tmp = ((8 * sdram->emc_pmacro_tx_pwrd4 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd4 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd4 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd4 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd4 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd4 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd4 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd4 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd4 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd4 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd4 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd4 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd4 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd4 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd4 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd4 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd4 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd4 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd4 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd4 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd4 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd4 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd4 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd4 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd4 & 1 | 2 * (pmc->scratch81 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF;
+	pmc->scratch81 = ((u8)(sdram->emc_rd_rcd) << 26) | ((4 * sdram->emc_pmacro_tx_pwrd4 >> 31 << 25) | tmp) & 0x3FFFFFF;
+	tmp = ((8 * sdram->emc_pmacro_tx_pwrd5 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd5 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd5 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd5 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd5 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd5 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd5 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd5 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd5 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd5 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd5 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd5 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd5 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd5 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd5 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd5 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd5 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd5 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd5 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd5 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd5 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd5 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd5 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd5 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd5 & 1 | 2 * (pmc->scratch82 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF;
+	pmc->scratch82 = ((u16)(sdram->emc_wr_rcd) << 26) | ((4 * sdram->emc_pmacro_tx_pwrd5 >> 31 << 25) | tmp) & 0x3FFFFFF;
+	pmc->scratch83 = ((u8)(sdram->emc_config_sample_delay) << 25) | ((sdram->emc_auto_cal_channel >> 31 << 24) | ((2 * sdram->emc_auto_cal_channel >> 31 << 23) | ((4 * sdram->emc_auto_cal_channel >> 31 << 22) | ((16 * sdram->emc_auto_cal_channel >> 25 << 15) | ((sdram->emc_auto_cal_channel << 11 >> 27 << 10) | ((sdram->emc_auto_cal_channel << 20 >> 28 << 6) | (sdram->emc_auto_cal_channel & 0x3F | (pmc->scratch83 >> 6 << 6)) & 0xFFFFFC3F) & 0xFFFF83FF) & 0xFFC07FFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0x1FFFFFF;
+	pmc->scratch84 = (sdram->emc_sel_dpd_ctrl << 13 >> 29 << 29) | ((sdram->emc_sel_dpd_ctrl << 23 >> 31 << 28) | ((sdram->emc_sel_dpd_ctrl << 26 >> 31 << 27) | ((sdram->emc_sel_dpd_ctrl << 27 >> 31 << 26) | ((sdram->emc_sel_dpd_ctrl << 28 >> 31 << 25) | ((sdram->emc_sel_dpd_ctrl << 29 >> 31 << 24) | ((4 * sdram->emc_pmacro_rx_term >> 26 << 18) | ((sdram->emc_pmacro_rx_term << 10 >> 26 << 12) | ((sdram->emc_pmacro_rx_term << 18 >> 26 << 6) | (sdram->emc_pmacro_rx_term & 0x3F | (pmc->scratch84 >> 6 << 6)) & 0xFFFFF03F) & 0xFFFC0FFF) & 0xFF03FFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF;
+	pmc->scratch85 = (4 * sdram->emc_obdly >> 30 << 30) | (4 * ((sdram->emc_obdly << 24) | ((4 * sdram->emc_pmacro_dq_tx_drive >> 26 << 18) | ((sdram->emc_pmacro_dq_tx_drive << 10 >> 26 << 12) | ((sdram->emc_pmacro_dq_tx_drive << 18 >> 26 << 6) | (sdram->emc_pmacro_dq_tx_drive & 0x3F | (pmc->scratch85 >> 6 << 6)) & 0xFFFFF03F) & 0xFFFC0FFF) & 0xFF03FFFF) & 0xC0FFFFFF) >> 2);
+	pmc->scratch86 = (sdram->emc_pmacro_vttgen_ctrl1 << 10 >> 30 << 30) | (4 * ((sdram->emc_pmacro_vttgen_ctrl1 << 16 >> 26 << 24) | ((4 * sdram->emc_pmacro_ca_tx_drive >> 26 << 18) | ((sdram->emc_pmacro_ca_tx_drive << 10 >> 26 << 12) | ((sdram->emc_pmacro_ca_tx_drive << 18 >> 26 << 6) | (sdram->emc_pmacro_ca_tx_drive & 0x3F | (pmc->scratch86 >> 6 << 6)) & 0xFFFFF03F) & 0xFFFC0FFF) & 0xFF03FFFF) & 0xC0FFFFFF) >> 2);
+	pmc->scratch87 = (sdram->emc_pmacro_vttgen_ctrl2 >> 16 << 24) | ((16 * sdram->emc_pmacro_zcrtl >> 30 << 22) | ((sdram->emc_pmacro_zcrtl << 6 >> 30 << 20) | ((sdram->emc_pmacro_zcrtl << 8 >> 30 << 18) | ((sdram->emc_pmacro_zcrtl << 10 >> 30 << 16) | ((sdram->emc_pmacro_zcrtl << 12 >> 30 << 14) | ((sdram->emc_pmacro_zcrtl << 14 >> 30 << 12) | ((sdram->emc_pmacro_zcrtl << 16 >> 30 << 10) | ((sdram->emc_pmacro_zcrtl << 18 >> 30 << 8) | ((sdram->emc_pmacro_zcrtl << 20 >> 30 << 6) | (16 * (sdram->emc_pmacro_zcrtl << 22 >> 30) | (4 * (sdram->emc_pmacro_zcrtl << 24 >> 30) | ((sdram->emc_pmacro_zcrtl << 26 >> 30) | 4 * (pmc->scratch87 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFFFFFF;
+	pmc->scratch88 = (sdram->mc_emem_arb_timing_rc << 24) | ((sdram->emc_zcal_interval << 14) | ((sdram->emc_zcal_interval << 8 >> 18) | (pmc->scratch88 >> 14 << 14)) & 0xFF003FFF) & 0xFFFFFF;
+	pmc->scratch89 = ((u16)(sdram->mc_emem_arb_rsv) << 24) | ((sdram->emc_data_brlshft0 << 8 >> 29 << 21) | ((sdram->emc_data_brlshft0 << 11 >> 29 << 18) | ((sdram->emc_data_brlshft0 << 14 >> 29 << 15) | ((sdram->emc_data_brlshft0 << 17 >> 29 << 12) | ((sdram->emc_data_brlshft0 << 20 >> 29 << 9) | ((sdram->emc_data_brlshft0 << 23 >> 29 << 6) | (8 * (sdram->emc_data_brlshft0 << 26 >> 29) | (sdram->emc_data_brlshft0 & 7 | 8 * (pmc->scratch89 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0xFFFFFF;
+	pmc->scratch90 = (sdram->emc_data_brlshft1 << 8 >> 29 << 21) | ((sdram->emc_data_brlshft1 << 11 >> 29 << 18) | ((sdram->emc_data_brlshft1 << 14 >> 29 << 15) | ((sdram->emc_data_brlshft1 << 17 >> 29 << 12) | ((sdram->emc_data_brlshft1 << 20 >> 29 << 9) | ((sdram->emc_data_brlshft1 << 23 >> 29 << 6) | (8 * (sdram->emc_data_brlshft1 << 26 >> 29) | (sdram->emc_data_brlshft1 & 7 | 8 * (pmc->scratch90 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF;
+	pmc->scratch91 = (sdram->emc_dqs_brlshft0 << 8 >> 29 << 21) | ((sdram->emc_dqs_brlshft0 << 11 >> 29 << 18) | ((sdram->emc_dqs_brlshft0 << 14 >> 29 << 15) | ((sdram->emc_dqs_brlshft0 << 17 >> 29 << 12) | ((sdram->emc_dqs_brlshft0 << 20 >> 29 << 9) | ((sdram->emc_dqs_brlshft0 << 23 >> 29 << 6) | (8 * (sdram->emc_dqs_brlshft0 << 26 >> 29) | (sdram->emc_dqs_brlshft0 & 7 | 8 * (pmc->scratch91 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF;
+	pmc->scratch92 = (sdram->emc_dqs_brlshft1 << 8 >> 29 << 21) | ((sdram->emc_dqs_brlshft1 << 11 >> 29 << 18) | ((sdram->emc_dqs_brlshft1 << 14 >> 29 << 15) | ((sdram->emc_dqs_brlshft1 << 17 >> 29 << 12) | ((sdram->emc_dqs_brlshft1 << 20 >> 29 << 9) | ((sdram->emc_dqs_brlshft1 << 23 >> 29 << 6) | (8 * (sdram->emc_dqs_brlshft1 << 26 >> 29) | (sdram->emc_dqs_brlshft1 & 7 | 8 * (pmc->scratch92 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF;
+	pmc->scratch93 = (2 * sdram->emc_swizzle_rank0_byte0 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank0_byte0 >> 29 << 18) | ((sdram->emc_swizzle_rank0_byte0 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte0 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte0 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte0 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte0 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte0 & 7 | 8 * (pmc->scratch93 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF;
+	pmc->scratch94 = ((u8)(sdram->emc_cfg) << 27 >> 31 << 31) | (2 * ((sdram->emc_ras << 24) | ((2 * sdram->emc_swizzle_rank0_byte1 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank0_byte1 >> 29 << 18) | ((sdram->emc_swizzle_rank0_byte1 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte1 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte1 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte1 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte1 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte1 & 7 | 8 * (pmc->scratch94 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch95 = ((u8)(sdram->emc_cfg) << 26 >> 31 << 31) | (2 * ((sdram->emc_w2p << 24) | ((2 * sdram->emc_swizzle_rank0_byte2 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank0_byte2 >> 29 << 18) | ((sdram->emc_swizzle_rank0_byte2 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte2 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte2 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte2 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte2 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte2 & 7 | 8 * (pmc->scratch95 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch96 = ((u8)(sdram->emc_cfg) << 25 >> 31 << 31) | (2 * ((sdram->emc_qsafe << 24) | ((2 * sdram->emc_swizzle_rank0_byte3 >> 29 << 21) | (((sdram->emc_swizzle_rank0_byte3 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte3 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte3 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte3 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte3 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte3 & 7 | 8 * (pmc->scratch96 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF | (32 * sdram->emc_swizzle_rank0_byte3 >> 29 << 18)) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch97 = ((u8)(sdram->emc_cfg) << 24 >> 31 << 31) | (2 * ((sdram->emc_rdv << 24) | ((2 * sdram->emc_swizzle_rank1_byte0 >> 29 << 21) | (((sdram->emc_swizzle_rank1_byte0 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte0 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte0 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte0 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte0 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte0 & 7 | 8 * (pmc->scratch97 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF | (32 * sdram->emc_swizzle_rank1_byte0 >> 29 << 18)) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch98 = ((u16)(sdram->emc_cfg) << 23 >> 31 << 31) | (2 * (((u16)(sdram->emc_rw2pden) << 24) | ((2 * sdram->emc_swizzle_rank1_byte1 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank1_byte1 >> 29 << 18) | ((sdram->emc_swizzle_rank1_byte1 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte1 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte1 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte1 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte1 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte1 & 7 | 8 * (pmc->scratch98 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch99 = ((u16)(sdram->emc_cfg) << 22 >> 31 << 31) | (2 * ((sdram->emc_tfaw << 24) | ((2 * sdram->emc_swizzle_rank1_byte2 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank1_byte2 >> 29 << 18) | ((sdram->emc_swizzle_rank1_byte2 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte2 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte2 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte2 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte2 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte2 & 7 | 8 * (pmc->scratch99 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch100 = (sdram->emc_cfg << 13 >> 31 << 31) | (2 * ((sdram->emc_tclkstable << 24) | ((2 * sdram->emc_swizzle_rank1_byte3 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank1_byte3 >> 29 << 18) | ((sdram->emc_swizzle_rank1_byte3 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte3 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte3 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte3 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte3 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte3 & 7 | 8 * (pmc->scratch100 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1);
+	tmp = 2 * (((u8)(sdram->emc_trtm) << 24) | ((16 * sdram->emc_cfg_pipe2 >> 31 << 23) | ((32 * sdram->emc_cfg_pipe2 >> 31 << 22) | ((sdram->emc_cfg_pipe2 << 6 >> 31 << 21) | ((sdram->emc_cfg_pipe2 << 7 >> 31 << 20) | ((sdram->emc_cfg_pipe2 << 8 >> 31 << 19) | ((sdram->emc_cfg_pipe2 << 9 >> 31 << 18) | ((sdram->emc_cfg_pipe2 << 10 >> 31 << 17) | ((sdram->emc_cfg_pipe2 << 11 >> 31 << 16) | ((sdram->emc_cfg_pipe2 << 12 >> 31 << 15) | ((sdram->emc_cfg_pipe2 << 13 >> 31 << 14) | ((sdram->emc_cfg_pipe2 << 14 >> 31 << 13) | ((sdram->emc_cfg_pipe2 << 15 >> 31 << 12) | ((sdram->emc_cfg_pipe2 << 20 >> 31 << 11) | ((sdram->emc_cfg_pipe2 << 21 >> 31 << 10) | ((sdram->emc_cfg_pipe2 << 22 >> 31 << 9) | ((sdram->emc_cfg_pipe2 << 23 >> 31 << 8) | ((sdram->emc_cfg_pipe2 << 24 >> 31 << 7) | ((sdram->emc_cfg_pipe2 << 25 >> 31 << 6) | (32 * (sdram->emc_cfg_pipe2 << 26 >> 31) | (16 * (sdram->emc_cfg_pipe2 << 27 >> 31) | (8 * (sdram->emc_cfg_pipe2 << 28 >> 31) | (4 * (sdram->emc_cfg_pipe2 << 29 >> 31) | (2 * (sdram->emc_cfg_pipe2 << 30 >> 31) | (sdram->emc_cfg_pipe2 & 1 | 2 * (pmc->scratch101 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1;
+	pmc->scratch101 = (sdram->emc_cfg << 10 >> 31 << 31) | tmp;
+	tmp = (2 * (pmc->scratch102 >> 1) | sdram->emc_cfg_pipe1 & 1) & 0xFFFFFFFD;
+	pmc->scratch102 = (sdram->emc_cfg << 9 >> 31 << 31) | (2 * (((u8)(sdram->emc_twtm) << 24) | ((16 * sdram->emc_cfg_pipe1 >> 31 << 23) | ((32 * sdram->emc_cfg_pipe1 >> 31 << 22) | ((sdram->emc_cfg_pipe1 << 6 >> 31 << 21) | ((sdram->emc_cfg_pipe1 << 7 >> 31 << 20) | ((sdram->emc_cfg_pipe1 << 8 >> 31 << 19) | ((sdram->emc_cfg_pipe1 << 9 >> 31 << 18) | ((sdram->emc_cfg_pipe1 << 10 >> 31 << 17) | ((sdram->emc_cfg_pipe1 << 11 >> 31 << 16) | ((sdram->emc_cfg_pipe1 << 12 >> 31 << 15) | ((sdram->emc_cfg_pipe1 << 13 >> 31 << 14) | ((sdram->emc_cfg_pipe1 << 14 >> 31 << 13) | ((sdram->emc_cfg_pipe1 << 15 >> 31 << 12) | ((sdram->emc_cfg_pipe1 << 20 >> 31 << 11) | ((sdram->emc_cfg_pipe1 << 21 >> 31 << 10) | ((sdram->emc_cfg_pipe1 << 22 >> 31 << 9) | ((sdram->emc_cfg_pipe1 << 23 >> 31 << 8) | ((sdram->emc_cfg_pipe1 << 24 >> 31 << 7) | ((sdram->emc_cfg_pipe1 << 25 >> 31 << 6) | (32 * (sdram->emc_cfg_pipe1 << 26 >> 31) | (16 * (sdram->emc_cfg_pipe1 << 27 >> 31) | (8 * (sdram->emc_cfg_pipe1 << 28 >> 31) | (4 * (sdram->emc_cfg_pipe1 << 29 >> 31) | (2 * (sdram->emc_cfg_pipe1 << 30 >> 31) | tmp) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1);
+	tmp = 2 * (((u8)(sdram->emc_tratm) << 24) | ((sdram->emc_pmacro_ddll_pwrd0 >> 31 << 23) | ((2 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 22) | ((8 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 21) | ((16 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 20) | ((32 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 19) | ((sdram->emc_pmacro_ddll_pwrd0 << 6 >> 31 << 18) | ((sdram->emc_pmacro_ddll_pwrd0 << 8 >> 31 << 17) | ((sdram->emc_pmacro_ddll_pwrd0 << 9 >> 31 << 16) | ((sdram->emc_pmacro_ddll_pwrd0 << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_pwrd0 << 12 >> 31 << 14) | ((sdram->emc_pmacro_ddll_pwrd0 << 13 >> 31 << 13) | ((sdram->emc_pmacro_ddll_pwrd0 << 14 >> 31 << 12) | ((sdram->emc_pmacro_ddll_pwrd0 << 16 >> 31 << 11) | ((sdram->emc_pmacro_ddll_pwrd0 << 17 >> 31 << 10) | ((sdram->emc_pmacro_ddll_pwrd0 << 19 >> 31 << 9) | ((sdram->emc_pmacro_ddll_pwrd0 << 20 >> 31 << 8) | ((sdram->emc_pmacro_ddll_pwrd0 << 21 >> 31 << 7) | ((sdram->emc_pmacro_ddll_pwrd0 << 22 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_pwrd0 << 24 >> 31) | (16 * (sdram->emc_pmacro_ddll_pwrd0 << 25 >> 31) | (8 * (sdram->emc_pmacro_ddll_pwrd0 << 27 >> 31) | (4 * (sdram->emc_pmacro_ddll_pwrd0 << 28 >> 31) | (2 * (sdram->emc_pmacro_ddll_pwrd0 << 29 >> 31) | ((sdram->emc_pmacro_ddll_pwrd0 << 30 >> 31) | 2 * (pmc->scratch103 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1;
+	pmc->scratch103 = (sdram->emc_cfg << 8 >> 31 << 31) | tmp;
+	tmp = 2 * (((u8)(sdram->emc_twatm) << 24) | ((sdram->emc_pmacro_ddll_pwrd1 >> 31 << 23) | ((2 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 22) | ((8 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 21) | ((16 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 20) | ((32 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 19) | ((sdram->emc_pmacro_ddll_pwrd1 << 6 >> 31 << 18) | ((sdram->emc_pmacro_ddll_pwrd1 << 8 >> 31 << 17) | ((sdram->emc_pmacro_ddll_pwrd1 << 9 >> 31 << 16) | ((sdram->emc_pmacro_ddll_pwrd1 << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_pwrd1 << 12 >> 31 << 14) | ((sdram->emc_pmacro_ddll_pwrd1 << 13 >> 31 << 13) | ((sdram->emc_pmacro_ddll_pwrd1 << 14 >> 31 << 12) | ((sdram->emc_pmacro_ddll_pwrd1 << 16 >> 31 << 11) | ((sdram->emc_pmacro_ddll_pwrd1 << 17 >> 31 << 10) | ((sdram->emc_pmacro_ddll_pwrd1 << 19 >> 31 << 9) | ((sdram->emc_pmacro_ddll_pwrd1 << 20 >> 31 << 8) | ((sdram->emc_pmacro_ddll_pwrd1 << 21 >> 31 << 7) | ((sdram->emc_pmacro_ddll_pwrd1 << 22 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_pwrd1 << 24 >> 31) | (16 * (sdram->emc_pmacro_ddll_pwrd1 << 25 >> 31) | (8 * (sdram->emc_pmacro_ddll_pwrd1 << 27 >> 31) | (4 * (sdram->emc_pmacro_ddll_pwrd1 << 28 >> 31) | (2 * (sdram->emc_pmacro_ddll_pwrd1 << 29 >> 31) | ((sdram->emc_pmacro_ddll_pwrd1 << 30 >> 31) | 2 * (pmc->scratch104 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1;
+	pmc->scratch104 = (sdram->emc_cfg << 7 >> 31 << 31) | tmp;
+	tmp = (sdram->emc_pmacro_ddll_pwrd2 << 22 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_pwrd2 << 24 >> 31) | (16 * (sdram->emc_pmacro_ddll_pwrd2 << 25 >> 31) | (8 * (sdram->emc_pmacro_ddll_pwrd2 << 27 >> 31) | (4 * (sdram->emc_pmacro_ddll_pwrd2 << 28 >> 31) | (2 * (sdram->emc_pmacro_ddll_pwrd2 << 29 >> 31) | ((sdram->emc_pmacro_ddll_pwrd2 << 30 >> 31) | 2 * (pmc->scratch105 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF;
+	pmc->scratch105 = (sdram->emc_cfg << 6 >> 31 << 31) | (2 * (((u8)(sdram->emc_tr2ref) << 24) | ((sdram->emc_pmacro_ddll_pwrd2 >> 31 << 23) | ((2 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 22) | ((8 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 21) | ((16 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 20) | ((32 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 19) | ((sdram->emc_pmacro_ddll_pwrd2 << 6 >> 31 << 18) | ((sdram->emc_pmacro_ddll_pwrd2 << 8 >> 31 << 17) | ((sdram->emc_pmacro_ddll_pwrd2 << 9 >> 31 << 16) | ((sdram->emc_pmacro_ddll_pwrd2 << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_pwrd2 << 12 >> 31 << 14) | ((sdram->emc_pmacro_ddll_pwrd2 << 13 >> 31 << 13) | ((sdram->emc_pmacro_ddll_pwrd2 << 14 >> 31 << 12) | ((sdram->emc_pmacro_ddll_pwrd2 << 16 >> 31 << 11) | ((sdram->emc_pmacro_ddll_pwrd2 << 17 >> 31 << 10) | ((sdram->emc_pmacro_ddll_pwrd2 << 19 >> 31 << 9) | ((sdram->emc_pmacro_ddll_pwrd2 << 20 >> 31 << 8) | ((sdram->emc_pmacro_ddll_pwrd2 << 21 >> 31 << 7) | tmp & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch106 = (32 * sdram->emc_cfg >> 31 << 31) | (2 * (((u16)(sdram->emc_pdex2mrr) << 24) | ((8 * sdram->emc_pmacro_ddll_periodic_offset >> 31 << 23) | ((16 * sdram->emc_pmacro_ddll_periodic_offset >> 31 << 22) | ((32 * sdram->emc_pmacro_ddll_periodic_offset >> 31 << 21) | ((sdram->emc_pmacro_ddll_periodic_offset << 6 >> 31 << 20) | ((sdram->emc_pmacro_ddll_periodic_offset << 7 >> 31 << 19) | ((sdram->emc_pmacro_ddll_periodic_offset << 8 >> 31 << 18) | ((sdram->emc_pmacro_ddll_periodic_offset << 9 >> 31 << 17) | ((sdram->emc_pmacro_ddll_periodic_offset << 10 >> 31 << 16) | ((sdram->emc_pmacro_ddll_periodic_offset << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_periodic_offset << 15 >> 31 << 14) | ((sdram->emc_pmacro_ddll_periodic_offset << 16 >> 31 << 13) | ((sdram->emc_pmacro_ddll_periodic_offset << 17 >> 31 << 12) | ((sdram->emc_pmacro_ddll_periodic_offset << 18 >> 31 << 11) | ((sdram->emc_pmacro_ddll_periodic_offset << 19 >> 31 << 10) | ((sdram->emc_pmacro_ddll_periodic_offset << 20 >> 31 << 9) | ((sdram->emc_pmacro_ddll_periodic_offset << 21 >> 31 << 8) | ((sdram->emc_pmacro_ddll_periodic_offset << 22 >> 31 << 7) | ((sdram->emc_pmacro_ddll_periodic_offset << 23 >> 31 << 6) | (sdram->emc_pmacro_ddll_periodic_offset & 0x3F | (pmc->scratch106 >> 6 << 6)) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch107 = (8 * sdram->emc_cfg >> 31 << 31) | (2 * ((sdram->emc_clken_override << 15 >> 31 << 30) | ((sdram->emc_clken_override << 23 >> 31 << 29) | ((sdram->emc_clken_override << 24 >> 31 << 28) | ((sdram->emc_clken_override << 25 >> 31 << 27) | ((sdram->emc_clken_override << 28 >> 31 << 26) | ((sdram->emc_clken_override << 29 >> 31 << 25) | ((sdram->emc_clken_override << 30 >> 31 << 24) | ((sdram->mc_emem_arb_da_covers << 8 >> 24 << 16) | ((sdram->mc_emem_arb_da_covers << 16 >> 24 << 8) | (sdram->mc_emem_arb_da_covers & 0xFF | (pmc->scratch107 >> 8 << 8)) & 0xFFFF00FF) & 0xFF00FFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch108 = (sdram->emc_rfc_pb << 23) | ((sdram->emc_xm2_comp_pad_ctrl >> 24 << 15) | ((sdram->emc_xm2_comp_pad_ctrl << 12 >> 24 << 7) | ((sdram->emc_xm2_comp_pad_ctrl << 20 >> 31 << 6) | (32 * (sdram->emc_xm2_comp_pad_ctrl << 22 >> 31) | (4 * (sdram->emc_xm2_comp_pad_ctrl << 25 >> 29) | (sdram->emc_xm2_comp_pad_ctrl & 3 | 4 * (pmc->scratch108 >> 2)) & 0xFFFFFFE3) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFF807F) & 0xFF807FFF) & 0x7FFFFF;
+	pmc->scratch109 = (sdram->emc_cfg_update >> 31 << 31) | (2 * ((2 * sdram->emc_cfg_update >> 31 << 30) | ((4 * sdram->emc_cfg_update >> 31 << 29) | ((8 * sdram->emc_cfg_update >> 31 << 28) | ((sdram->emc_cfg_update << 21 >> 30 << 26) | ((sdram->emc_cfg_update << 23 >> 31 << 25) | ((sdram->emc_cfg_update << 29 >> 30 << 23) | ((sdram->emc_cfg_update << 22) & 0x7FFFFF | ((sdram->emc_auto_cal_config3 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config3 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config3 << 17 >> 25 << 7) | ((pmc->scratch109 >> 7 << 7) | sdram->emc_auto_cal_config3 & 0x7F) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFE7FFFFF) & 0xFDFFFFFF) & 0xF3FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch110 = (sdram->emc_rfc << 22) | ((sdram->emc_auto_cal_config4 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config4 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config4 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config4 & 0x7F | (pmc->scratch110 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0x3FFFFF;
+	pmc->scratch111 = ((u16)(sdram->emc_txsr) << 22) | ((sdram->emc_auto_cal_config5 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config5 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config5 << 17 >> 25 << 7) | ((pmc->scratch111 >> 7 << 7) | sdram->emc_auto_cal_config5 & 0x7F) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0x3FFFFF;
+	pmc->scratch112 = (16 * sdram->emc_mc2emc_q >> 28 << 28) | ((sdram->emc_mc2emc_q << 21 >> 29 << 25) | ((sdram->emc_mc2emc_q << 22) & 0x1FFFFFF | ((sdram->emc_auto_cal_config6 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config6 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config6 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config6 & 0x7F | (pmc->scratch112 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xFFFFFFF;
+	pmc->scratch113 = (sdram->mc_emem_arb_ring1_throttle << 11 >> 27 << 27) | ((sdram->mc_emem_arb_ring1_throttle << 22) | ((sdram->emc_auto_cal_config7 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config7 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config7 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config7 & 0x7F | (pmc->scratch113 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xF83FFFFF) & 0x7FFFFFF;
+	pmc->scratch114 = (sdram->emc_auto_cal_config8 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config8 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config8 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config8 & 0x7F | (pmc->scratch114 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF;
+	pmc->scratch115 = (4 * sdram->emc_cfg >> 31 << 31) | (2 * (((u16)(sdram->emc_ar2pden) << 22) | ((sdram->emc_fbio_cfg7 << 10 >> 30 << 20) | ((sdram->emc_fbio_cfg7 << 12 >> 31 << 19) | ((sdram->emc_fbio_cfg7 << 13 >> 31 << 18) | ((sdram->emc_fbio_cfg7 << 14 >> 31 << 17) | ((sdram->emc_fbio_cfg7 << 15 >> 31 << 16) | ((sdram->emc_fbio_cfg7 << 16 >> 31 << 15) | ((sdram->emc_fbio_cfg7 << 17 >> 31 << 14) | ((sdram->emc_fbio_cfg7 << 18 >> 31 << 13) | ((sdram->emc_fbio_cfg7 << 19 >> 31 << 12) | ((sdram->emc_fbio_cfg7 << 20 >> 31 << 11) | ((sdram->emc_fbio_cfg7 << 21 >> 31 << 10) | ((sdram->emc_fbio_cfg7 << 22 >> 31 << 9) | ((sdram->emc_fbio_cfg7 << 23 >> 31 << 8) | ((sdram->emc_fbio_cfg7 << 24 >> 31 << 7) | ((sdram->emc_fbio_cfg7 << 25 >> 31 << 6) | (32 * (sdram->emc_fbio_cfg7 << 26 >> 31) | (16 * (sdram->emc_fbio_cfg7 << 27 >> 31) | (8 * (sdram->emc_fbio_cfg7 << 28 >> 31) | (4 * (sdram->emc_fbio_cfg7 << 29 >> 31) | (2 * (sdram->emc_fbio_cfg7 << 30 >> 31) | (sdram->emc_fbio_cfg7 & 1 | 2 * (pmc->scratch115 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFCFFFFF) & 0x803FFFFF) >> 1);
+	pmc->scratch123 = (2 * sdram->emc_cfg >> 31 << 31) | (2 * ((sdram->emc_rfc_slr << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_0 & 0x7FF | (pmc->scratch123 >> 11 << 11)) & 0xFFC007FF) & 0x803FFFFF) >> 1);
+	pmc->scratch124 = (sdram->emc_cfg >> 31 << 31) | (2 * ((4 * sdram->emc_ibdly >> 30 << 29) | ((sdram->emc_ibdly << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_1 & 0x7FF | (pmc->scratch124 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1);
+	pmc->scratch125 = (sdram->emc_fbio_cfg5 << 27 >> 31 << 31) | (2 * (((u16)(sdram->mc_emem_arb_timing_rfcpb) << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_2 & 0x7FF | (pmc->scratch125 >> 11 << 11)) & 0xFFC007FF) & 0x803FFFFF) >> 1);
+	pmc->scratch126 = (sdram->emc_fbio_cfg5 << 16 >> 29 << 29) | ((sdram->emc_auto_cal_config9 << 25 >> 31 << 28) | ((sdram->emc_auto_cal_config9 << 26 >> 31 << 27) | ((sdram->emc_auto_cal_config9 << 27 >> 31 << 26) | ((sdram->emc_auto_cal_config9 << 28 >> 31 << 25) | ((sdram->emc_auto_cal_config9 << 29 >> 31 << 24) | ((sdram->emc_auto_cal_config9 << 30 >> 31 << 23) | ((sdram->emc_auto_cal_config9 << 22) & 0x7FFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_3 & 0x7FF | (pmc->scratch126 >> 11 << 11)) & 0xFFC007FF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF;
+	pmc->scratch127 = ((u8)(sdram->emc_cfg2) << 26 >> 29 << 29) | ((sdram->emc_rdv_mask << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_4 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_4 & 0x7FF | (pmc->scratch127 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF;
+	pmc->scratch128 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 27 >> 29 << 29) | (((u8)(sdram->emc_rdv_early_mask) << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_5 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_5 & 0x7FF | (pmc->scratch128 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF;
+	pmc->scratch129 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 22 >> 29 << 29) | ((sdram->emc_rdv_early << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_0 & 0x7FF | (pmc->scratch129 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF;
+	pmc->scratch130 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 17 >> 29 << 29) | ((4 * sdram->emc_quse_width >> 31 << 28) | ((8 * sdram->emc_quse_width >> 31 << 27) | ((sdram->emc_quse_width << 22) & 0x7FFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_1 & 0x7FF | (pmc->scratch130 >> 11 << 11)) & 0xFFC007FF) & 0xF83FFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF;
+	pmc->scratch131 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 12 >> 29 << 29) | (((u16)(sdram->emc_pmacro_ddll_short_cmd_2) << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_2 & 0x7FF | (pmc->scratch131 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF;
+	pmc->scratch132 = (sdram->emc_pmacro_data_pad_tx_ctrl << 27 >> 29 << 29) | ((sdram->emc_pmacro_cmd_rx_term_mode << 18 >> 31 << 28) | ((sdram->emc_pmacro_cmd_rx_term_mode << 22 >> 30 << 26) | ((sdram->emc_pmacro_cmd_rx_term_mode << 26 >> 30 << 24) | ((sdram->emc_pmacro_cmd_rx_term_mode << 22) & 0xFFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_3 & 0x7FF | (pmc->scratch132 >> 11 << 11)) & 0xFFC007FF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF;
+	pmc->scratch133 = (sdram->emc_pmacro_data_pad_tx_ctrl << 22 >> 29 << 29) | ((sdram->emc_pmacro_data_rx_term_mode << 18 >> 31 << 28) | ((sdram->emc_pmacro_data_rx_term_mode << 22 >> 30 << 26) | ((sdram->emc_pmacro_data_rx_term_mode << 26 >> 30 << 24) | ((sdram->emc_pmacro_data_rx_term_mode << 22) & 0xFFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank1_4 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_4 & 0x7FF | (pmc->scratch133 >> 11 << 11)) & 0xFFC007FF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF;
+	pmc->scratch134 = (sdram->emc_pmacro_data_pad_tx_ctrl << 17 >> 29 << 29) | ((sdram->mc_emem_arb_timing_rp << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank1_5 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_5 & 0x7FF | (pmc->scratch134 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF;
+	pmc->scratch135 = (sdram->emc_pmacro_data_pad_tx_ctrl << 12 >> 29 << 29) | ((sdram->mc_emem_arb_timing_ras << 22) | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_0 & 0x7FF | (pmc->scratch135 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF;
+	pmc->scratch136 = (sdram->emc_fbio_cfg5 << 23 >> 31 << 31) | (2 * ((sdram->emc_cfg << 14 >> 30 << 29) | ((sdram->mc_emem_arb_timing_faw << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_1 & 0x7FF | (pmc->scratch136 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1);
+	pmc->scratch137 = (sdram->emc_fbio_cfg5 << 21 >> 31 << 31) | (2 * ((sdram->emc_fbio_cfg5 << 29) | ((sdram->mc_emem_arb_timing_rap2pre << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_2 & 0x7FF | (pmc->scratch137 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1);
+	pmc->scratch138 = (sdram->emc_fbio_cfg5 << 19 >> 31 << 31) | (2 * ((sdram->emc_fbio_cfg5 << 28 >> 30 << 29) | ((sdram->mc_emem_arb_timing_wap2pre << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_3 & 0x7FF | (pmc->scratch138 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1);
+	pmc->scratch139 = (sdram->emc_fbio_cfg5 << 7 >> 31 << 31) | (2 * ((16 * sdram->emc_cfg2 >> 30 << 29) | (((u8)(sdram->mc_emem_arb_timing_r2w) << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_4 & 0x7FF | (pmc->scratch139 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1);
+	pmc->scratch140 = (16 * sdram->emc_fbio_cfg5 >> 31 << 31) | (2 * ((32 * sdram->emc_fbio_cfg5 >> 31 << 30) | ((sdram->emc_fbio_cfg5 << 6 >> 31 << 29) | (((u8)(sdram->mc_emem_arb_timing_w2r) << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_5 & 0x7FF | (pmc->scratch140 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch141 = (sdram->emc_fbio_cfg5 << 8 >> 28 << 28) | (((u16)(sdram->emc_wdv) << 22) | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_0 & 0x7FF | (pmc->scratch141 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xFFFFFFF;
+	pmc->scratch142 = ((u8)(sdram->emc_cfg2) << 31) | (2 * ((sdram->emc_fbio_cfg5 >> 31 << 30) | ((2 * sdram->emc_fbio_cfg5 >> 31 << 29) | ((8 * sdram->emc_fbio_cfg5 >> 31 << 28) | ((sdram->emc_quse << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_1 & 0x7FF | (pmc->scratch142 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch143 = (((u16)(sdram->emc_cfg2) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_cfg2) << 24) >> 31 << 30) | ((((u16)(sdram->emc_cfg2) << 29) >> 31 << 29) | ((((u16)(sdram->emc_cfg2) << 30) >> 31 << 28) | (((u8)(sdram->emc_pdex2wr) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_2 & 0x7FF | (pmc->scratch143 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch144 = (sdram->emc_cfg2 << 15 >> 31 << 31) | (2 * ((sdram->emc_cfg2 << 16 >> 31 << 30) | ((sdram->emc_cfg2 << 17 >> 31 << 29) | ((sdram->emc_cfg2 << 20 >> 31 << 28) | (((u8)(sdram->emc_pdex2rd) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_3 & 0x7FF | (pmc->scratch144 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch145 = (sdram->emc_cfg2 << 7 >> 31 << 31) | (2 * ((sdram->emc_cfg2 << 8 >> 31 << 30) | ((sdram->emc_cfg2 << 9 >> 31 << 29) | ((sdram->emc_cfg2 << 11 >> 31 << 28) | (((u16)(sdram->emc_pdex2che) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_4 & 0x7FF | (pmc->scratch145 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch146 = (2 * sdram->emc_cfg2 >> 31 << 31) | (2 * ((4 * sdram->emc_cfg2 >> 31 << 30) | (((sdram->emc_cfg2 << 6 >> 31 << 28) | (((u8)(sdram->emc_pchg2pden) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_5 & 0x7FF | (pmc->scratch146 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF | (8 * sdram->emc_cfg2 >> 31 << 29)) & 0xBFFFFFFF) >> 1);
+	pmc->scratch147 = (((u8)(sdram->emc_cfg_pipe) << 29) >> 31 << 31) | (2 * ((((u8)(sdram->emc_cfg_pipe) << 30) >> 31 << 30) | ((((u8)(sdram->emc_cfg_pipe) << 31) >> 2) | ((sdram->emc_cfg2 >> 31 << 28) | (((u16)(sdram->emc_act2pden) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_0 & 0x7FF | (pmc->scratch147 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch148 = (((u8)(sdram->emc_cfg_pipe) << 25) >> 31 << 31) | (2 * ((((u8)(sdram->emc_cfg_pipe) << 26) >> 31 << 30) | ((((u8)(sdram->emc_cfg_pipe) << 27) >> 31 << 29) | ((((u8)(sdram->emc_cfg_pipe) << 28) >> 31 << 28) | (((u16)(sdram->emc_cke2pden) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_1 & 0x7FF | (pmc->scratch148 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch149 = (((u16)(sdram->emc_cfg_pipe) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_cfg_pipe) << 22) >> 31 << 30) | ((((u16)(sdram->emc_cfg_pipe) << 23) >> 31 << 29) | ((((u16)(sdram->emc_cfg_pipe) << 24) >> 31 << 28) | ((sdram->emc_tcke << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_2 & 0x7FF | (pmc->scratch149 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch150 = (sdram->emc_cfg_pipe << 13 >> 31 << 31) | (2 * ((sdram->emc_cfg_pipe << 14 >> 31 << 30) | (((sdram->emc_cfg_pipe << 20 >> 31 << 28) | ((sdram->emc_trpab << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_3 & 0x7FF | (pmc->scratch150 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF | (sdram->emc_cfg_pipe << 15 >> 31 << 29)) & 0xBFFFFFFF) >> 1);
+	pmc->scratch151 = (sdram->emc_cfg_pipe << 9 >> 31 << 31) | (2 * ((sdram->emc_cfg_pipe << 10 >> 31 << 30) | ((sdram->emc_cfg_pipe << 11 >> 31 << 29) | ((sdram->emc_cfg_pipe << 12 >> 31 << 28) | ((sdram->emc_einput << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_4 & 0x7FF | (pmc->scratch151 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch152 = (32 * sdram->emc_cfg_pipe >> 31 << 31) | (2 * ((sdram->emc_cfg_pipe << 6 >> 31 << 30) | ((sdram->emc_cfg_pipe << 7 >> 31 << 29) | ((sdram->emc_cfg_pipe << 8 >> 31 << 28) | ((sdram->emc_einput_duration << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_5 & 0x7FF | (pmc->scratch152 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch153 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 29) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 30) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 31) >> 2) | ((16 * sdram->emc_cfg_pipe >> 31 << 28) | ((sdram->emc_puterm_extra << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_0 & 0x7FF | (pmc->scratch153 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch154 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 25) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 26) >> 31 << 30) | (((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 28) >> 31 << 28) | ((sdram->emc_tckesr << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_1 & 0x7FF | (pmc->scratch154 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF | (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 27) >> 31 << 29)) & 0xBFFFFFFF) >> 1);
+	pmc->scratch155 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 22) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 23) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 24) >> 31 << 28) | ((sdram->emc_tpd << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_2 & 0x7FF | (pmc->scratch155 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch156 = (sdram->emc_pmacro_tx_sel_clk_src0 << 12 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src0 << 13 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 14 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 15 >> 31 << 28) | ((sdram->emc_wdv_mask << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_3 & 0x7FF | (pmc->scratch156 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch157 = (sdram->emc_pmacro_tx_sel_clk_src0 << 8 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src0 << 9 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 10 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 11 >> 31 << 28) | (((u16)(sdram->emc_wdv_chk) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_4 & 0x7FF | (pmc->scratch157 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch158 = ((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 31) | (2 * ((32 * sdram->emc_pmacro_tx_sel_clk_src0 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 6 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 7 >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft0) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft0) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_5 & 0x7FF | (pmc->scratch158 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch159 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 27) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 28) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 29) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 30) >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft1) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft1) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_0 & 0x7FF | (pmc->scratch159 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch160 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 23) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 24) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 25) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 26) >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft2) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft2) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_1 & 0x7FF | (pmc->scratch160 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch161 = (sdram->emc_pmacro_tx_sel_clk_src1 << 14 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src1 << 15 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 21 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 22 >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft3) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft3) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_2 & 0x7FF | (pmc->scratch161 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch162 = (sdram->emc_pmacro_tx_sel_clk_src1 << 10 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src1 << 11 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 12 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 13 >> 31 << 28) | (((u16)(sdram->emc_wev) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_3 & 0x7FF | (pmc->scratch162 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch163 = (sdram->emc_pmacro_tx_sel_clk_src1 << 6 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src1 << 7 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 8 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 9 >> 31 << 28) | (((u16)(sdram->emc_wsv) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_0 & 0x7FF | (pmc->scratch163 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch164 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 29) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 30) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 31) >> 2) | ((32 * sdram->emc_pmacro_tx_sel_clk_src1 >> 31 << 28) | (((u8)(sdram->emc_cfg3) << 25 >> 29 << 25) | (((u8)(sdram->emc_cfg3) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_1 & 0x7FF | (pmc->scratch164 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch165 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 25) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 26) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 27) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 28) >> 31 << 28) | ((sdram->emc_puterm_width << 23) & 0xFFFFFFF | ((sdram->emc_puterm_width >> 31 << 22) | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_2 & 0x7FF | (pmc->scratch165 >> 11 << 11)) & 0xFFC007FF) & 0xFFBFFFFF) & 0xF07FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch166 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 22) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 23) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 24) >> 31 << 28) | ((sdram->mc_emem_arb_timing_rcd << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_3 & 0x7FF | (pmc->scratch166 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch167 = (sdram->emc_pmacro_tx_sel_clk_src3 << 12 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src3 << 13 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 14 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 15 >> 31 << 28) | (((u16)(sdram->mc_emem_arb_timing_ccdmw) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ddll_long_cmd_0 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_0 & 0x7FF | (pmc->scratch167 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch168 = (sdram->emc_pmacro_tx_sel_clk_src3 << 8 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src3 << 9 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 10 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 11 >> 31 << 28) | ((sdram->mc_emem_arb_override << 28 >> 31 << 27) | (((sdram->mc_emem_arb_override << 21 >> 31 << 25) | ((sdram->mc_emem_arb_override << 15 >> 31 << 24) | ((32 * sdram->mc_emem_arb_override >> 31 << 23) | ((16 * sdram->mc_emem_arb_override >> 31 << 22) | ((32 * sdram->emc_pmacro_ddll_long_cmd_1 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_1 & 0x7FF | (pmc->scratch168 >> 11 << 11)) & 0xFFC007FF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF | (sdram->mc_emem_arb_override << 27 >> 31 << 26)) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch169 = ((u16)(sdram->emc_rext) << 27) | (((u16)(sdram->emc_rrd) << 22) | ((32 * sdram->emc_pmacro_ddll_long_cmd_2 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_2 & 0x7FF | (pmc->scratch169 >> 11 << 11)) & 0xFFC007FF) & 0xF83FFFFF) & 0x7FFFFFF;
+	pmc->scratch170 = ((u16)(sdram->emc_wext) << 27) | ((sdram->emc_tclkstop << 22) | ((32 * sdram->emc_pmacro_ddll_long_cmd_3 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_3 & 0x7FF | (pmc->scratch170 >> 11 << 11)) & 0xFFC007FF) & 0xF83FFFFF) & 0x7FFFFFF;
+	tmp = (32 * sdram->emc_pmacro_perbit_fgcg_ctrl0 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl0 & 1 | 2 * (pmc->scratch171 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF;
+	pmc->scratch171 = (sdram->emc_we_duration << 27) | ((sdram->emc_ref_ctrl2 >> 31 << 26) | ((32 * sdram->emc_ref_ctrl2 >> 29 << 23) | ((sdram->emc_ref_ctrl2 << 22) & 0x7FFFFF | tmp & 0xFFBFFFFF) & 0xFC7FFFFF) & 0xFBFFFFFF) & 0x7FFFFFF;
+	tmp = (sdram->emc_pmacro_pad_cfg_ctrl << 22 >> 31 << 28) | ((sdram->emc_pmacro_pad_cfg_ctrl << 27) & 0xFFFFFFF | ((sdram->emc_ws_duration << 22) & 0x7FFFFFF | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl1 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl1 & 1 | 2 * (pmc->scratch172 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xF83FFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF;
+	pmc->scratch172 = (sdram->emc_pmacro_pad_cfg_ctrl << 14 >> 30 << 30) | (4 * ((sdram->emc_pmacro_pad_cfg_ctrl << 18 >> 31 << 29) | tmp & 0xDFFFFFFF) >> 2);
+	pmc->scratch173 = ((u8)(sdram->mc_emem_arb_timing_r2r) << 27) | ((sdram->mc_emem_arb_timing_rrd << 22) | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl2 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl2 & 1 | 2 * (pmc->scratch173 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xF83FFFFF) & 0x7FFFFFF;
+	tmp = 32 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl3 & 1 | 2 * (pmc->scratch174 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF;
+	pmc->scratch174 = ((u16)(sdram->emc_pmacro_tx_sel_clk_src2) << 30 >> 31 << 31) | (2 * (((u16)(sdram->emc_pmacro_tx_sel_clk_src2) << 30) | ((32 * sdram->emc_pmacro_tx_sel_clk_src3 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 6 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 7 >> 31 << 27) | (((u8)(sdram->mc_emem_arb_timing_w2w) << 22) & 0x7FFFFFF | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl3 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 25 >> 31 << 6) | tmp & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xF83FFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	tmp = (sdram->emc_pmacro_tx_sel_clk_src2 << 28 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 29 >> 31 << 22) | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl4 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl4 & 1 | 2 * (pmc->scratch175 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF;
+	pmc->scratch175 = (sdram->emc_pmacro_tx_sel_clk_src2 << 15 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src2 << 21 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 22 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 23 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 24 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 25 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 26 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 27 >> 31 << 24) | tmp & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	tmp = (sdram->emc_pmacro_tx_sel_clk_src2 << 12 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 13 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 14 >> 31 << 22) | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl5 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl5 & 1 | 2 * (pmc->scratch176 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF;
+	pmc->scratch176 = (32 * sdram->emc_pmacro_tx_sel_clk_src2 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src2 << 6 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 7 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 8 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 9 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 10 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 11 >> 31 << 25) | tmp & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch177 = (sdram->emc_pmacro_tx_sel_clk_src4 << 22 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src4 << 23 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 24 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 25 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 26 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 27 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 28 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 29 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 30 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 22) & 0x7FFFFF | ((sdram->mc_emem_arb_cfg >> 28 << 18) | ((16 * sdram->mc_emem_arb_cfg >> 28 << 14) | ((sdram->mc_emem_arb_cfg << 11 >> 27 << 9) | (sdram->mc_emem_arb_cfg & 0x1FF | (pmc->scratch177 >> 9 << 9)) & 0xFFFFC1FF) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch178 = (sdram->emc_pmacro_tx_sel_clk_src4 << 7 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src4 << 8 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 9 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 10 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 11 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 12 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 13 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 14 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 15 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 21 >> 31 << 22) | ((sdram->mc_emem_arb_misc1 >> 28 << 18) | ((sdram->mc_emem_arb_misc1 << 6 >> 30 << 16) | ((sdram->mc_emem_arb_misc1 << 8 >> 29 << 13) | (16 * (sdram->mc_emem_arb_misc1 << 19 >> 23) | (8 * (sdram->mc_emem_arb_misc1 << 28 >> 31) | (4 * (sdram->mc_emem_arb_misc1 << 29 >> 31) | (2 * (sdram->mc_emem_arb_misc1 << 30 >> 31) | (sdram->mc_emem_arb_misc1 & 1 | 2 * (pmc->scratch178 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFE00F) & 0xFFFF1FFF) & 0xFFFCFFFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch179 = (sdram->emc_odt_write >> 31 << 31) | (2 * ((sdram->emc_odt_write << 20 >> 28 << 27) | ((sdram->emc_odt_write << 26 >> 31 << 26) | ((sdram->emc_odt_write << 27 >> 31 << 25) | ((sdram->emc_odt_write << 21) & 0x1FFFFFF | ((32 * sdram->emc_mrs_wait_cnt2 >> 21 << 10) | (sdram->emc_mrs_wait_cnt2 & 0x3FF | (pmc->scratch179 >> 10 << 10)) & 0xFFE003FF) & 0xFE1FFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0x87FFFFFF) >> 1);
+	pmc->scratch180 = (sdram->emc_pmacro_ib_rxrt << 21) | ((32 * sdram->emc_mrs_wait_cnt >> 21 << 10) | (sdram->emc_mrs_wait_cnt & 0x3FF | (pmc->scratch180 >> 10 << 10)) & 0xFFE003FF) & 0x1FFFFF;
+	pmc->scratch181 = ((u16)(sdram->emc_pmacro_ddll_long_cmd_4) << 21) | sdram->emc_auto_cal_interval & 0x1FFFFF;
+	pmc->scratch182 = (sdram->mc_emem_arb_outstanding_req >> 31 << 31) | (2 * ((2 * sdram->mc_emem_arb_outstanding_req >> 31 << 30) | ((sdram->mc_emem_arb_outstanding_req << 23 >> 2) | ((sdram->emc_emem_arb_refpb_hp_ctrl << 9 >> 25 << 14) | ((sdram->emc_emem_arb_refpb_hp_ctrl << 17 >> 25 << 7) | (sdram->emc_emem_arb_refpb_hp_ctrl & 0x7F | (pmc->scratch182 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xC01FFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch183 = (4 * sdram->emc_pmacro_cmd_ctrl0 >> 31 << 31) | (2 * ((8 * sdram->emc_pmacro_cmd_ctrl0 >> 31 << 30) | ((sdram->emc_pmacro_cmd_ctrl0 << 7 >> 31 << 29) | ((sdram->emc_pmacro_cmd_ctrl0 << 10 >> 31 << 28) | ((sdram->emc_pmacro_cmd_ctrl0 << 11 >> 31 << 27) | ((sdram->emc_pmacro_cmd_ctrl0 << 15 >> 31 << 26) | ((sdram->emc_pmacro_cmd_ctrl0 << 18 >> 31 << 25) | ((sdram->emc_pmacro_cmd_ctrl0 << 19 >> 31 << 24) | ((sdram->emc_pmacro_cmd_ctrl0 << 23 >> 31 << 23) | ((sdram->emc_pmacro_cmd_ctrl0 << 26 >> 31 << 22) | ((sdram->emc_pmacro_cmd_ctrl0 << 27 >> 31 << 21) | ((sdram->emc_pmacro_cmd_ctrl0 << 20) & 0x1FFFFF | ((4 * sdram->emc_xm2_comp_pad_ctrl2 >> 26 << 14) | ((sdram->emc_xm2_comp_pad_ctrl2 << 10 >> 30 << 12) | ((sdram->emc_xm2_comp_pad_ctrl2 << 14 >> 31 << 11) | ((sdram->emc_xm2_comp_pad_ctrl2 << 15 >> 31 << 10) | ((sdram->emc_xm2_comp_pad_ctrl2 << 16 >> 30 << 8) | ((sdram->emc_xm2_comp_pad_ctrl2 << 18 >> 30 << 6) | (4 * (sdram->emc_xm2_comp_pad_ctrl2 << 26 >> 28) | (sdram->emc_xm2_comp_pad_ctrl2 & 3 | 4 * (pmc->scratch183 >> 2)) & 0xFFFFFFC3) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFCFFF) & 0xFFF03FFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch184 = (4 * sdram->emc_pmacro_cmd_ctrl1 >> 31 << 31) | (2 * ((8 * sdram->emc_pmacro_cmd_ctrl1 >> 31 << 30) | ((sdram->emc_pmacro_cmd_ctrl1 << 7 >> 31 << 29) | ((sdram->emc_pmacro_cmd_ctrl1 << 10 >> 31 << 28) | ((sdram->emc_pmacro_cmd_ctrl1 << 11 >> 31 << 27) | ((sdram->emc_pmacro_cmd_ctrl1 << 15 >> 31 << 26) | ((sdram->emc_pmacro_cmd_ctrl1 << 18 >> 31 << 25) | ((sdram->emc_pmacro_cmd_ctrl1 << 19 >> 31 << 24) | ((sdram->emc_pmacro_cmd_ctrl1 << 23 >> 31 << 23) | ((sdram->emc_pmacro_cmd_ctrl1 << 26 >> 31 << 22) | ((sdram->emc_pmacro_cmd_ctrl1 << 27 >> 31 << 21) | ((sdram->emc_pmacro_cmd_ctrl1 << 20) & 0x1FFFFF | ((sdram->emc_cfg_dig_dll_1 << 12 >> 28 << 16) | ((sdram->emc_cfg_dig_dll_1 << 16 >> 28 << 12) | ((sdram->emc_cfg_dig_dll_1 << 20 >> 26 << 6) | (2 * (sdram->emc_cfg_dig_dll_1 << 26 >> 27) | (sdram->emc_cfg_dig_dll_1 & 1 | 2 * (pmc->scratch184 >> 1)) & 0xFFFFFFC1) & 0xFFFFF03F) & 0xFFFF0FFF) & 0xFFF0FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch185 = (4 * sdram->emc_pmacro_cmd_ctrl2 >> 31 << 31) | (2 * ((8 * sdram->emc_pmacro_cmd_ctrl2 >> 31 << 30) | ((sdram->emc_pmacro_cmd_ctrl2 << 7 >> 31 << 29) | ((sdram->emc_pmacro_cmd_ctrl2 << 10 >> 31 << 28) | ((sdram->emc_pmacro_cmd_ctrl2 << 11 >> 31 << 27) | ((sdram->emc_pmacro_cmd_ctrl2 << 15 >> 31 << 26) | ((sdram->emc_pmacro_cmd_ctrl2 << 18 >> 31 << 25) | ((sdram->emc_pmacro_cmd_ctrl2 << 19 >> 31 << 24) | ((sdram->emc_pmacro_cmd_ctrl2 << 23 >> 31 << 23) | ((sdram->emc_pmacro_cmd_ctrl2 << 26 >> 31 << 22) | ((sdram->emc_pmacro_cmd_ctrl2 << 27 >> 31 << 21) | ((sdram->emc_pmacro_cmd_ctrl2 << 20) & 0x1FFFFF | ((sdram->emc_quse_brlshft0 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft0 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft0 << 22 >> 27) | (sdram->emc_quse_brlshft0 & 0x1F | 32 * (pmc->scratch185 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch186 = (sdram->emc_pmacro_dsr_vttgen_ctrl0 >> 8 << 24) | ((sdram->emc_pmacro_dsr_vttgen_ctrl0 << 20) | ((sdram->emc_quse_brlshft1 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft1 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft1 << 22 >> 27) | (sdram->emc_quse_brlshft1 & 0x1F | 32 * (pmc->scratch186 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFF0FFFFF) & 0xFFFFFF;
+	pmc->scratch187 = (sdram->emc_pmacro_perbit_rfu1_ctrl0 << 10 >> 30 << 30) | (4 * ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 12 >> 30 << 28) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 14 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 26 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 28 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 20) & 0x3FFFFF | ((sdram->emc_quse_brlshft2 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft2 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft2 << 22 >> 27) | (sdram->emc_quse_brlshft2 & 0x1F | 32 * (pmc->scratch187 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch188 = (sdram->emc_pmacro_perbit_rfu1_ctrl1 << 10 >> 30 << 30) | (4 * ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 12 >> 30 << 28) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 14 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 26 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 28 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 20) & 0x3FFFFF | ((sdram->emc_quse_brlshft3 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft3 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft3 << 22 >> 27) | (sdram->emc_quse_brlshft3 & 0x1F | 32 * (pmc->scratch188 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->scratch189 = (sdram->emc_trefbw << 18) | ((sdram->emc_dbg >> 31 << 17) | ((2 * sdram->emc_dbg >> 31 << 16) | ((4 * sdram->emc_dbg >> 31 << 15) | ((8 * sdram->emc_dbg >> 31 << 14) | ((16 * sdram->emc_dbg >> 30 << 12) | ((sdram->emc_dbg << 6 >> 31 << 11) | ((sdram->emc_dbg << 7 >> 31 << 10) | ((sdram->emc_dbg << 18 >> 31 << 9) | ((sdram->emc_dbg << 19 >> 31 << 8) | ((sdram->emc_dbg << 20 >> 31 << 7) | ((sdram->emc_dbg << 21 >> 31 << 6) | (32 * (sdram->emc_dbg << 22 >> 31) | (16 * (sdram->emc_dbg << 27 >> 31) | (8 * (sdram->emc_dbg << 28 >> 31) | (4 * (sdram->emc_dbg << 29 >> 31) | (2 * (sdram->emc_dbg << 30 >> 31) | (sdram->emc_dbg & 1 | 2 * (pmc->scratch189 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFCFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0x3FFFF;
+	pmc->scratch191 = (sdram->emc_qpop << 9 >> 25 << 25) | ((sdram->emc_qpop << 18) | ((sdram->emc_zcal_wait_cnt >> 31 << 17) | ((sdram->emc_zcal_wait_cnt << 10 >> 26 << 11) | (sdram->emc_zcal_wait_cnt & 0x7FF | (pmc->scratch191 >> 11 << 11)) & 0xFFFE07FF) & 0xFFFDFFFF) & 0xFE03FFFF) & 0x1FFFFFF;
+	pmc->scratch192 = (sdram->emc_pmacro_tx_sel_clk_src4 << 6 >> 31 << 31) | (2 * ((sdram->emc_pmacro_auto_cal_common << 15 >> 31 << 30) | ((sdram->emc_pmacro_auto_cal_common << 18 >> 26 << 24) | ((sdram->emc_pmacro_auto_cal_common << 18) & 0xFFFFFF | ((sdram->emc_zcal_mrw_cmd >> 30 << 16) | ((sdram->emc_zcal_mrw_cmd << 8 >> 24 << 8) | (sdram->emc_zcal_mrw_cmd & 0xFF | (pmc->scratch192 >> 8 << 8)) & 0xFFFF00FF) & 0xFFFCFFFF) & 0xFF03FFFF) & 0xC0FFFFFF) & 0xBFFFFFFF) >> 1);
+	tmp = (sdram->emc_dll_cfg1 << 7 >> 31 << 17) | ((sdram->emc_dll_cfg1 << 10 >> 31 << 16) | ((sdram->emc_dll_cfg1 << 11 >> 31 << 15) | ((sdram->emc_dll_cfg1 << 14 >> 30 << 13) | ((sdram->emc_dll_cfg1 << 18 >> 31 << 12) | ((sdram->emc_dll_cfg1 << 19 >> 31 << 11) | ((pmc->scratch193 >> 11 << 11) | sdram->emc_dll_cfg1 & 0x7FF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFF9FFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF;
+	pmc->scratch193 = (sdram->emc_pmacro_tx_sel_clk_src5 << 31) | (2 * ((32 * sdram->emc_pmacro_tx_sel_clk_src4 >> 31 << 30) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 10 >> 30 << 28) | (((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 14 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 26 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 28 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 18) & 0xFFFFF | tmp & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl2 << 12 >> 30 << 26)) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch194 = (sdram->emc_pmacro_tx_sel_clk_src5 << 29 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src5 << 30 >> 31 << 30) | ((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 10 >> 30 << 28) | (((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 14 >> 30 << 24) | (((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 28 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 18) & 0xFFFFF | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 14 >> 30 << 16) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 16 >> 30 << 14) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 18 >> 30 << 12) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 20 >> 30 << 10) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 22 >> 30 << 8) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 26 >> 30) | (4 * (sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 28 >> 30) | (sdram->emc_pmacro_cmd_brick_ctrl_fdpd & 3 | 4 * (pmc->scratch194 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl3 << 26 >> 30 << 22)) & 0xFCFFFFFF) & 0xF3FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl3 << 12 >> 30 << 26)) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch195 = (sdram->emc_pmacro_tx_sel_clk_src5 << 27 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src5 << 28 >> 31 << 30) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 10 >> 30 << 28) | (((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 14 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 26 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 28 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 18) & 0xFFFFF | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 14 >> 30 << 16) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 16 >> 30 << 14) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 18 >> 30 << 12) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 20 >> 30 << 10) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 22 >> 30 << 8) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_data_brick_ctrl_fdpd << 26 >> 30) | (4 * (sdram->emc_pmacro_data_brick_ctrl_fdpd << 28 >> 30) | (sdram->emc_pmacro_data_brick_ctrl_fdpd & 3 | 4 * (pmc->scratch195 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl4 << 12 >> 30 << 26)) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch196 = (sdram->emc_emem_arb_refpb_bank_ctrl >> 31 << 31) | (2 * ((sdram->emc_emem_arb_refpb_bank_ctrl << 17 >> 25 << 24) | ((sdram->emc_emem_arb_refpb_bank_ctrl << 17) & 0xFFFFFF | ((sdram->emc_dyn_self_ref_control >> 31 << 16) | (sdram->emc_dyn_self_ref_control & 0xFFFF | (pmc->scratch196 >> 16 << 16)) & 0xFFFEFFFF) & 0xFF01FFFF) & 0x80FFFFFF) >> 1);
+	pmc->scratch197 = (sdram->emc_pmacro_tx_sel_clk_src5 << 24 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src5 << 25 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 26 >> 31 << 29) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 10 >> 30 << 27) | (((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 14 >> 30 << 23) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 26 >> 30 << 21) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 28 >> 30 << 19) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 17) & 0x7FFFF | ((16 * sdram->emc_pmacro_cmd_pad_rx_ctrl >> 28 << 13) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 8 >> 31 << 12) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 9 >> 31 << 11) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 10 >> 31 << 10) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 12 >> 28 << 6) | (32 * (sdram->emc_pmacro_cmd_pad_rx_ctrl << 16 >> 31) | (16 * (sdram->emc_pmacro_cmd_pad_rx_ctrl << 19 >> 31) | (4 * (sdram->emc_pmacro_cmd_pad_rx_ctrl << 26 >> 30) | (sdram->emc_pmacro_cmd_pad_rx_ctrl & 3 | 4 * (pmc->scratch197 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFC3F) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFE1FFF) & 0xFFF9FFFF) & 0xFFE7FFFF) & 0xFF9FFFFF) & 0xFE7FFFFF) & 0xF9FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl5 << 12 >> 30 << 25)) & 0xE7FFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch198 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 31) | (2 * ((32 * sdram->emc_pmacro_tx_sel_clk_src5 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 6 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 7 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 8 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 9 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 10 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 11 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 12 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 13 >> 31 << 22) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 14 >> 31 << 21) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 15 >> 31 << 20) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 21 >> 31 << 19) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 22 >> 31 << 18) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 23 >> 31 << 17) | ((16 * sdram->emc_pmacro_data_pad_rx_ctrl >> 28 << 13) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 8 >> 31 << 12) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 9 >> 31 << 11) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 10 >> 31 << 10) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 12 >> 28 << 6) | (32 * (sdram->emc_pmacro_data_pad_rx_ctrl << 16 >> 31) | (16 * (sdram->emc_pmacro_data_pad_rx_ctrl << 19 >> 31) | (4 * (sdram->emc_pmacro_data_pad_rx_ctrl << 26 >> 30) | (sdram->emc_pmacro_data_pad_rx_ctrl & 3 | 4 * (pmc->scratch198 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFC3F) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFE1FFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch199 = (8 * sdram->emc_cmd_q >> 27 << 27) | ((sdram->emc_cmd_q << 17 >> 29 << 24) | ((sdram->emc_cmd_q << 21 >> 29 << 21) | ((sdram->emc_cmd_q << 16) & 0x1FFFFF | (((u16)(sdram->emc_refresh) << 16 >> 22 << 6) | (sdram->emc_refresh & 0x3F | (pmc->scratch199 >> 6 << 6)) & 0xFFFF003F) & 0xFFE0FFFF) & 0xFF1FFFFF) & 0xF8FFFFFF) & 0x7FFFFFF;
+	pmc->scratch210 = (sdram->emc_auto_cal_vref_sel1 << 16 >> 31 << 31) | (2 * ((sdram->emc_auto_cal_vref_sel1 << 17 >> 25 << 24) | ((sdram->emc_auto_cal_vref_sel1 << 24 >> 31 << 23) | ((sdram->emc_auto_cal_vref_sel1 << 16) & 0x7FFFFF | (sdram->emc_acpd_control & 0xFFFF | (pmc->scratch210 >> 16 << 16)) & 0xFF80FFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1);
+	tmp = 8 * (sdram->emc_pmacro_auto_cal_cfg0 << 28 >> 31) | (4 * (sdram->emc_pmacro_auto_cal_cfg0 << 29 >> 31) | (2 * (sdram->emc_pmacro_auto_cal_cfg0 << 30 >> 31) | (sdram->emc_pmacro_auto_cal_cfg0 & 1 | 2 * (pmc->scratch211 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7;
+	tmp = (sdram->emc_pmacro_auto_cal_cfg1 << 7 >> 31 << 28) | ((sdram->emc_pmacro_auto_cal_cfg1 << 12 >> 31 << 27) | ((sdram->emc_pmacro_auto_cal_cfg1 << 13 >> 31 << 26) | ((sdram->emc_pmacro_auto_cal_cfg1 << 14 >> 31 << 25) | ((sdram->emc_pmacro_auto_cal_cfg1 << 15 >> 31 << 24) | ((sdram->emc_pmacro_auto_cal_cfg1 << 20 >> 31 << 23) | ((sdram->emc_pmacro_auto_cal_cfg1 << 21 >> 31 << 22) | ((sdram->emc_pmacro_auto_cal_cfg1 << 22 >> 31 << 21) | ((sdram->emc_pmacro_auto_cal_cfg1 << 23 >> 31 << 20) | ((sdram->emc_pmacro_auto_cal_cfg1 << 28 >> 31 << 19) | ((sdram->emc_pmacro_auto_cal_cfg1 << 29 >> 31 << 18) | ((sdram->emc_pmacro_auto_cal_cfg1 << 30 >> 31 << 17) | ((sdram->emc_pmacro_auto_cal_cfg1 << 16) & 0x1FFFF | ((16 * sdram->emc_pmacro_auto_cal_cfg0 >> 31 << 15) | ((32 * sdram->emc_pmacro_auto_cal_cfg0 >> 31 << 14) | ((sdram->emc_pmacro_auto_cal_cfg0 << 6 >> 31 << 13) | ((sdram->emc_pmacro_auto_cal_cfg0 << 7 >> 31 << 12) | ((sdram->emc_pmacro_auto_cal_cfg0 << 12 >> 31 << 11) | ((sdram->emc_pmacro_auto_cal_cfg0 << 13 >> 31 << 10) | ((sdram->emc_pmacro_auto_cal_cfg0 << 14 >> 31 << 9) | ((sdram->emc_pmacro_auto_cal_cfg0 << 15 >> 31 << 8) | ((sdram->emc_pmacro_auto_cal_cfg0 << 20 >> 31 << 7) | ((sdram->emc_pmacro_auto_cal_cfg0 << 21 >> 31 << 6) | (32 * (sdram->emc_pmacro_auto_cal_cfg0 << 22 >> 31) | (16 * (sdram->emc_pmacro_auto_cal_cfg0 << 23 >> 31) | tmp & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF;
+	pmc->scratch211 = (16 * sdram->emc_pmacro_auto_cal_cfg1 >> 31 << 31) | (2 * ((32 * sdram->emc_pmacro_auto_cal_cfg1 >> 31 << 30) | ((sdram->emc_pmacro_auto_cal_cfg1 << 6 >> 31 << 29) | tmp & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->scratch212 = (sdram->emc_xm2_comp_pad_ctrl3 << 8 >> 28 << 28) | ((sdram->emc_xm2_comp_pad_ctrl3 << 14 >> 31 << 27) | ((sdram->emc_xm2_comp_pad_ctrl3 << 15 >> 31 << 26) | ((sdram->emc_xm2_comp_pad_ctrl3 << 16 >> 30 << 24) | ((sdram->emc_xm2_comp_pad_ctrl3 << 18 >> 30 << 22) | ((sdram->emc_xm2_comp_pad_ctrl3 << 26 >> 28 << 18) | ((sdram->emc_xm2_comp_pad_ctrl3 << 16) & 0x3FFFF | ((16 * sdram->emc_pmacro_auto_cal_cfg2 >> 31 << 15) | ((32 * sdram->emc_pmacro_auto_cal_cfg2 >> 31 << 14) | ((sdram->emc_pmacro_auto_cal_cfg2 << 6 >> 31 << 13) | ((sdram->emc_pmacro_auto_cal_cfg2 << 7 >> 31 << 12) | ((sdram->emc_pmacro_auto_cal_cfg2 << 12 >> 31 << 11) | ((sdram->emc_pmacro_auto_cal_cfg2 << 13 >> 31 << 10) | ((sdram->emc_pmacro_auto_cal_cfg2 << 14 >> 31 << 9) | ((sdram->emc_pmacro_auto_cal_cfg2 << 15 >> 31 << 8) | ((sdram->emc_pmacro_auto_cal_cfg2 << 20 >> 31 << 7) | ((sdram->emc_pmacro_auto_cal_cfg2 << 21 >> 31 << 6) | (32 * (sdram->emc_pmacro_auto_cal_cfg2 << 22 >> 31) | (16 * (sdram->emc_pmacro_auto_cal_cfg2 << 23 >> 31) | (8 * (sdram->emc_pmacro_auto_cal_cfg2 << 28 >> 31) | (4 * (sdram->emc_pmacro_auto_cal_cfg2 << 29 >> 31) | (2 * (sdram->emc_pmacro_auto_cal_cfg2 << 30 >> 31) | (sdram->emc_pmacro_auto_cal_cfg2 & 1 | 2 * (pmc->scratch212 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFCFFFF) & 0xFFC3FFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xFFFFFFF;
+	pmc->scratch213 = ((u16)(sdram->emc_prerefresh_req_cnt) << 16) | (u16)(sdram->emc_cfg_dig_dll_period);
+	pmc->scratch214 = (sdram->emc_pmacro_data_pi_ctrl << 10 >> 26 << 26) | ((sdram->emc_pmacro_data_pi_ctrl << 19 >> 31 << 25) | ((sdram->emc_pmacro_data_pi_ctrl << 20 >> 28 << 21) | ((sdram->emc_pmacro_data_pi_ctrl << 27 >> 31 << 20) | ((sdram->emc_pmacro_data_pi_ctrl << 16) & 0xFFFFF | ((sdram->emc_pmacro_ddll_bypass >> 31 << 15) | ((2 * sdram->emc_pmacro_ddll_bypass >> 31 << 14) | ((4 * sdram->emc_pmacro_ddll_bypass >> 31 << 13) | ((16 * sdram->emc_pmacro_ddll_bypass >> 31 << 12) | ((32 * sdram->emc_pmacro_ddll_bypass >> 31 << 11) | ((sdram->emc_pmacro_ddll_bypass << 6 >> 31 << 10) | ((sdram->emc_pmacro_ddll_bypass << 7 >> 31 << 9) | ((sdram->emc_pmacro_ddll_bypass << 15 >> 31 << 8) | ((sdram->emc_pmacro_ddll_bypass << 16 >> 31 << 7) | ((sdram->emc_pmacro_ddll_bypass << 17 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_bypass << 18 >> 31) | (16 * (sdram->emc_pmacro_ddll_bypass << 20 >> 31) | (8 * (sdram->emc_pmacro_ddll_bypass << 21 >> 31) | (4 * (sdram->emc_pmacro_ddll_bypass << 22 >> 31) | (2 * (sdram->emc_pmacro_ddll_bypass << 23 >> 31) | (sdram->emc_pmacro_ddll_bypass & 1 | 2 * (pmc->scratch214 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFF0FFFF) & 0xFFEFFFFF) & 0xFE1FFFFF) & 0xFDFFFFFF) & 0x3FFFFFF;
+	pmc->scratch215 = (sdram->emc_pmacro_cmd_pi_ctrl << 10 >> 26 << 10) | ((sdram->emc_pmacro_cmd_pi_ctrl << 19 >> 31 << 9) | (32 * (sdram->emc_pmacro_cmd_pi_ctrl << 20 >> 28) | (16 * (sdram->emc_pmacro_cmd_pi_ctrl << 27 >> 31) | (sdram->emc_pmacro_cmd_pi_ctrl & 0xF | 16 * (pmc->scratch215 >> 4)) & 0xFFFFFFEF) & 0xFFFFFE1F) & 0xFFFFFDFF) & 0xFFFF03FF;
+	tmp = (sdram->emc_pmacro_data_pad_tx_ctrl << 7 >> 31 << 24) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 8 >> 31 << 23) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 9 >> 31 << 22) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 10 >> 31 << 21) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 15 >> 31 << 20) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 16 >> 31 << 19) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 21 >> 31 << 18) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 25 >> 31 << 17) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 26 >> 31 << 16) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 15) & 0xFFFF | ((2 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 14) | ((4 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 13) | ((8 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 12) | ((16 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 11) | ((32 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 10) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 6 >> 31 << 9) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 7 >> 31 << 8) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 8 >> 31 << 7) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 9 >> 31 << 6) | (32 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 10 >> 31) | (16 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 15 >> 31) | (8 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 16 >> 31) | (4 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 21 >> 31) | (2 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 25 >> 31) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 26 >> 31) | 2 * (pmc->scratch216 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF;
+
+	s(emc_pin_gpio, 1:0, scratch9, 31:30);
+	s(emc_pin_gpio_enable, 1:0, scratch10, 31:30);
+	s(emc_dev_select, 1:0, scratch11, 31:30);
+	s(emc_zcal_warm_cold_boot_enables, 1:0, scratch12, 31:30);
+	s(emc_cfg_dig_dll_period_warm_boot, 1:0, scratch13, 31:30);
+	s32(emc_bct_spare13, scratch45);
+	s32(emc_bct_spare12, scratch46);
+	s32(emc_bct_spare7, scratch47);
+	s32(emc_bct_spare6, scratch48);
+	s32(emc_bct_spare5, scratch50);
+	s32(emc_bct_spare4, scratch51);
+	s32(emc_bct_spare3, scratch56);
+	s32(emc_bct_spare2, scratch57);
+	s32(emc_bct_spare1, scratch58);
+	s32(emc_bct_spare0, scratch59);
+	s32(emc_bct_spare9, scratch60);
+	s32(emc_bct_spare8, scratch61);
+	s32(boot_rom_patch_data, scratch62);
+	s32(boot_rom_patch_control, scratch63);
+	s(mc_clken_override_allwarm_boot, 0:0, scratch65, 31:31);
+	pmc->scratch66 = pmc->scratch66 & 0x1FFFFFFF | ((u8)(sdram->emc_extra_refresh_num) << 29);
+	pmc->scratch72 = pmc->scratch72 & 0x8FFFFFFF | ((u16)(sdram->pmc_io_dpd3_req_wait) << 28) & 0x70000000;
+	pmc->scratch72 = ((2 * pmc->scratch72) >> 1) | ((u16)(sdram->emc_clken_override_allwarm_boot) << 31);
+	pmc->scratch73 = pmc->scratch73 & 0x8FFFFFFF | ((u8)(sdram->memory_type) << 28) & 0x70000000;
+	pmc->scratch73 = ((2 * pmc->scratch73) >> 1) | (sdram->emc_mrs_warm_boot_enable << 31);
+	pmc->scratch74 = pmc->scratch74 & 0x8FFFFFFF | (sdram->pmc_io_dpd4_req_wait << 28) & 0x70000000;
+	pmc->scratch74 = ((2 * pmc->scratch74) >> 1) | (sdram->clear_clock2_mc1 << 31);
+	pmc->scratch75 = pmc->scratch75 & 0xEFFFFFFF | (sdram->emc_warm_boot_extramode_reg_write_enable << 28) & 0x10000000;
+	pmc->scratch75 = pmc->scratch75 & 0xDFFFFFFF | (sdram->clk_rst_pllm_misc20_override_enable << 29) & 0x20000000;
+	pmc->scratch75 = pmc->scratch75 & 0xBFFFFFFF | ((u16)(sdram->emc_dbg_write_mux) << 30) & 0x40000000;
+	pmc->scratch75 = ((2 * pmc->scratch75) >> 1) | ((u16)(sdram->ahb_arbitration_xbar_ctrl_meminit_done) << 31);
+	pmc->scratch90 = pmc->scratch90 & 0xFFFFFF | (sdram->emc_timing_control_wait << 24);
+	pmc->scratch91 = pmc->scratch91 & 0xFFFFFF | (sdram->emc_zcal_warm_boot_wait << 24);
+	pmc->scratch92 = pmc->scratch92 & 0xFFFFFF | (sdram->warm_boot_wait << 24);
+	pmc->scratch93 = pmc->scratch93 & 0xFFFFFF | ((u16)(sdram->emc_pin_program_wait) << 24);
+	pmc->scratch114 = pmc->scratch114 & 0x3FFFFF | ((u16)(sdram->emc_auto_cal_wait) << 22);
+	pmc->scratch215 = (u16)pmc->scratch215 | ((u16)(sdram->swizzle_rank_byte_encode) << 16);
+	pmc->scratch216 = (2 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 30) | ((4 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 29) | ((8 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 28) | ((16 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 27) | ((32 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 26) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 6 >> 31 << 25) | tmp & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF;
+	s(emc_mrw_lpddr2zcal_warm_boot, 23:16, scratch5, 7:0);
+	s(emc_mrw_lpddr2zcal_warm_boot, 7:0, scratch5, 15:8);
+	s(emc_warm_boot_mrw_extra, 23:16, scratch5, 23:16);
+	s(emc_warm_boot_mrw_extra, 7:0, scratch5, 31:24);
+	s(emc_mrw_lpddr2zcal_warm_boot, 31:30, scratch6, 1:0);
+	s(emc_warm_boot_mrw_extra, 31:30, scratch6, 3:2);
+	s(emc_mrw_lpddr2zcal_warm_boot, 27:26, scratch6, 5:4);
+	s(emc_warm_boot_mrw_extra, 27:26, scratch6, 7:6);
+	s(emc_mrw6, 27:0, scratch8, 27:0);
+	s(emc_mrw6, 31:30, scratch8, 29:28);
+	s(emc_mrw8, 27:0, scratch9, 27:0);
+	s(emc_mrw8, 31:30, scratch9, 29:28);
+	s(emc_mrw9, 27:0, scratch10, 27:0);
+	s(emc_mrw9, 31:30, scratch10, 29:28);
+	s(emc_mrw10, 27:0, scratch11, 27:0);
+	s(emc_mrw10, 31:30, scratch11, 29:28);
+	s(emc_mrw12, 27:0, scratch12, 27:0);
+	s(emc_mrw12, 31:30, scratch12, 29:28);
+	s(emc_mrw13, 27:0, scratch13, 27:0);
+	s(emc_mrw13, 31:30, scratch13, 29:28);
+	s(emc_mrw14, 27:0, scratch14, 27:0);
+	s(emc_mrw14, 31:30, scratch14, 29:28);
+	s(emc_mrw1, 7:0, scratch15, 7:0);
+	s(emc_mrw1, 23:16, scratch15, 15:8);
+	s(emc_mrw1, 27:26, scratch15, 17:16);
+	s(emc_mrw1, 31:30, scratch15, 19:18);
+	s(emc_warm_boot_mrw_extra, 7:0, scratch16, 7:0);
+	s(emc_warm_boot_mrw_extra, 23:16, scratch16, 15:8);
+	s(emc_warm_boot_mrw_extra, 27:26, scratch16, 17:16);
+	s(emc_warm_boot_mrw_extra, 31:30, scratch16, 19:18);
+	s(emc_mrw2, 7:0, scratch17, 7:0);
+	s(emc_mrw2, 23:16, scratch17, 15:8);
+	s(emc_mrw2, 27:26, scratch17, 17:16);
+	s(emc_mrw2, 31:30, scratch17, 19:18);
+	pmc->scratch18 = (sdram->emc_mrw3 >> 30 << 18) | ((16 * sdram->emc_mrw3 >> 31 << 17) | ((32 * sdram->emc_mrw3 >> 31 << 16) | ((sdram->emc_mrw3 << 8 >> 24 << 8) | ((u8)sdram->emc_mrw3 | (pmc->scratch18 >> 8 << 8)) & 0xFFFF00FF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFF3FFFF;
+	pmc->scratch19 = (sdram->emc_mrw4 >> 30 << 18) | ((16 * sdram->emc_mrw4 >> 31 << 17) | ((32 * sdram->emc_mrw4 >> 31 << 16) | ((sdram->emc_mrw4 << 8 >> 24 << 8) | ((u8)sdram->emc_mrw4 | (pmc->scratch19 >> 8 << 8)) & 0xFFFF00FF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFF3FFFF;
+	s32(emc_cmd_mapping_byte, secure_scratch8);
+	s32(emc_pmacro_brick_mapping0, secure_scratch9);
+	s32(emc_pmacro_brick_mapping1, secure_scratch10);
+	s32(emc_pmacro_brick_mapping2, secure_scratch11);
+	s32(mc_video_protect_gpu_override0, secure_scratch12);
+	pmc->secure_scratch13 = ((u16)(sdram->emc_adr_cfg) << 31) | (2 * ((((u16)(sdram->mc_untranslated_region_check) << 22) >> 31 << 30) | ((((u16)(sdram->mc_untranslated_region_check) << 23) >> 31 << 29) | (((u16)(sdram->mc_untranslated_region_check) << 28) & 0x1FFFFFFF | ((2 * sdram->emc_cmd_mapping_cmd0_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd0_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd0_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd0_0 & 0x7F | (pmc->secure_scratch13 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch14 = (sdram->mc_video_protect_write_access << 30 >> 31 << 31) | (2 * ((sdram->mc_video_protect_write_access << 30) | ((sdram->mc_video_protect_bom_adr_hi << 30 >> 2) | ((2 * sdram->emc_cmd_mapping_cmd0_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd0_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd0_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd0_1 & 0x7F | (pmc->secure_scratch14 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch15 = ((u16)(sdram->mc_mts_carveout_adr_hi) << 30) | (4 * ((sdram->mc_sec_carveout_adr_hi << 28) | ((2 * sdram->emc_cmd_mapping_cmd1_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd1_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd1_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd1_0 & 0x7F | (pmc->secure_scratch15 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->secure_scratch16 = (sdram->mc_generalized_carveout3_bom_hi << 30) | (4 * ((sdram->mc_generalized_carveout5_bom_hi << 28) | ((2 * sdram->emc_cmd_mapping_cmd1_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd1_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd1_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd1_1 & 0x7F | (pmc->secure_scratch16 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->secure_scratch17 = ((u16)(sdram->mc_generalized_carveout4_bom_hi) << 30) | (4 * (((u16)(sdram->mc_generalized_carveout2_bom_hi) << 28) | ((2 * sdram->emc_cmd_mapping_cmd2_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd2_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd2_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd2_0 & 0x7F | (pmc->secure_scratch17 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) >> 2);
+	pmc->secure_scratch18 = (sdram->emc_fbio_cfg8 << 16 >> 31 << 31) | (2 * (((u16)(sdram->emc_fbio_spare) << 30 >> 31 << 30) | ((sdram->mc_generalized_carveout1_bom_hi << 30 >> 2) | ((2 * sdram->emc_cmd_mapping_cmd2_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd2_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd2_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd2_1 & 0x7F | (pmc->secure_scratch18 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch19 = (sdram->mc_video_protect_vpr_override << 31) | (2 * (((u16)(sdram->mc_mts_carveout_reg_ctrl) << 30) | ((sdram->mc_sec_carveout_protect_write_access << 31 >> 2) | (((u16)(sdram->mc_emem_adr_cfg) << 28) & 0x1FFFFFFF | ((2 * sdram->emc_cmd_mapping_cmd3_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd3_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd3_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd3_0 & 0x7F | (pmc->secure_scratch19 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch20 = (sdram->mc_generalized_carveout2_cfg0 << 25 >> 28 << 28) | ((2 * sdram->emc_cmd_mapping_cmd3_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd3_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd3_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd3_1 & 0x7F | (pmc->secure_scratch20 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xFFFFFFF;
+	pmc->secure_scratch39 = (sdram->mc_video_protect_vpr_override << 30 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout2_cfg0 << 21 >> 28 << 27) | ((32 * sdram->mc_generalized_carveout4_cfg0 >> 31 << 26) | ((sdram->mc_generalized_carveout4_cfg0 << 6 >> 31 << 25) | ((sdram->mc_generalized_carveout4_cfg0 << 7 >> 31 << 24) | ((sdram->mc_generalized_carveout4_cfg0 << 8 >> 31 << 23) | ((sdram->mc_generalized_carveout4_cfg0 << 9 >> 31 << 22) | ((sdram->mc_generalized_carveout4_cfg0 << 10 >> 28 << 18) | ((sdram->mc_generalized_carveout4_cfg0 << 14 >> 28 << 14) | ((sdram->mc_generalized_carveout4_cfg0 << 18 >> 29 << 11) | ((sdram->mc_generalized_carveout4_cfg0 << 21 >> 28 << 7) | (8 * (sdram->mc_generalized_carveout4_cfg0 << 25 >> 28) | (4 * (sdram->mc_generalized_carveout4_cfg0 << 29 >> 31) | (2 * (sdram->mc_generalized_carveout4_cfg0 << 30 >> 31) | (sdram->mc_generalized_carveout4_cfg0 & 1 | 2 * (pmc->secure_scratch39 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFF87) & 0xFFFFF87F) & 0xFFFFC7FF) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0x87FFFFFF) >> 1);
+	pmc->secure_scratch40 = (sdram->mc_video_protect_vpr_override << 29 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout2_cfg0 << 14 >> 28 << 27) | ((32 * sdram->mc_generalized_carveout5_cfg0 >> 31 << 26) | ((sdram->mc_generalized_carveout5_cfg0 << 6 >> 31 << 25) | ((sdram->mc_generalized_carveout5_cfg0 << 7 >> 31 << 24) | ((sdram->mc_generalized_carveout5_cfg0 << 8 >> 31 << 23) | ((sdram->mc_generalized_carveout5_cfg0 << 9 >> 31 << 22) | ((sdram->mc_generalized_carveout5_cfg0 << 10 >> 28 << 18) | ((sdram->mc_generalized_carveout5_cfg0 << 14 >> 28 << 14) | ((sdram->mc_generalized_carveout5_cfg0 << 18 >> 29 << 11) | ((sdram->mc_generalized_carveout5_cfg0 << 21 >> 28 << 7) | (8 * (sdram->mc_generalized_carveout5_cfg0 << 25 >> 28) | (4 * (sdram->mc_generalized_carveout5_cfg0 << 29 >> 31) | (2 * (sdram->mc_generalized_carveout5_cfg0 << 30 >> 31) | (sdram->mc_generalized_carveout5_cfg0 & 1 | 2 * (pmc->secure_scratch40 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFF87) & 0xFFFFF87F) & 0xFFFFC7FF) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0x87FFFFFF) >> 1);
+	pmc->secure_scratch41 = (sdram->mc_generalized_carveout2_cfg0 << 18 >> 29 << 29) | ((sdram->mc_generalized_carveout2_cfg0 << 10 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd0_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd0_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd0_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd0_2 & 0x7F | (pmc->secure_scratch41 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0x1FFFFFFF;
+	pmc->secure_scratch42 = ((u16)(sdram->mc_generalized_carveout1_cfg0) << 18 >> 29 << 29) | (((u16)(sdram->mc_generalized_carveout1_cfg0) << 25 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd1_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd1_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd1_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd1_2 & 0x7F | (pmc->secure_scratch42 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0x1FFFFFFF;
+	pmc->secure_scratch43 = ((u16)(sdram->mc_generalized_carveout3_cfg0) << 18 >> 29 << 29) | (((u16)(sdram->mc_generalized_carveout1_cfg0) << 21 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd2_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd2_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd2_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd2_2 & 0x7F | (pmc->secure_scratch43 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0x1FFFFFFF;
+	pmc->secure_scratch44 = (sdram->mc_video_protect_vpr_override << 24 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 25 >> 31 << 30) | ((sdram->mc_video_protect_vpr_override << 28 >> 31 << 29) | ((sdram->mc_generalized_carveout1_cfg0 << 14 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd3_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd3_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd3_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd3_2 & 0x7F | (pmc->secure_scratch44 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	s(mc_emem_adr_cfg_channel_mask, 31:9, secure_scratch45, 22:0);
+	s(mc_emem_adr_cfg_dev0, 2:0, secure_scratch45, 25:23);
+	s(mc_emem_adr_cfg_dev0, 9:8, secure_scratch45, 27:26);
+	s(mc_emem_adr_cfg_dev0, 19:16, secure_scratch45, 31:28);
+	pmc->secure_scratch46 = (sdram->mc_video_protect_vpr_override << 23 >> 31 << 31) | (2 * ((sdram->mc_emem_adr_cfg_dev1 << 12 >> 28 << 27) | ((sdram->mc_emem_adr_cfg_dev1 << 22 >> 30 << 25) | ((sdram->mc_emem_adr_cfg_dev1 << 22) & 0x1FFFFFF | ((sdram->mc_emem_adr_cfg_bank_mask0 >> 10) | (pmc->secure_scratch46 >> 22 << 22)) & 0xFE3FFFFF) & 0xF9FFFFFF) & 0x87FFFFFF) >> 1);
+	pmc->secure_scratch47 = (sdram->mc_video_protect_vpr_override << 20 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 22 >> 31 << 30) | (((u8)(sdram->mc_generalized_carveout3_cfg0) << 25 >> 28 << 26) | ((sdram->mc_generalized_carveout1_cfg0 << 10 >> 28 << 22) | ((sdram->mc_emem_adr_cfg_bank_mask1 >> 10) | (pmc->secure_scratch47 >> 22 << 22)) & 0xFC3FFFFF) & 0xC3FFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch48 = (sdram->mc_video_protect_vpr_override << 16 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 17 >> 31 << 30) | ((sdram->mc_generalized_carveout3_cfg0 << 14 >> 28 << 26) | ((sdram->mc_generalized_carveout3_cfg0 << 21 >> 28 << 22) | ((sdram->mc_emem_adr_cfg_bank_mask2 >> 10) | (pmc->secure_scratch48 >> 22 << 22)) & 0xFC3FFFFF) & 0xC3FFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch49 = (sdram->mc_video_protect_vpr_override << 14 >> 31 << 31) | (2 * ((sdram->mc_emem_cfg >> 31 << 30) | ((sdram->mc_emem_cfg << 18 >> 2) | (sdram->mc_video_protect_gpu_override1 & 0xFFFF | (pmc->secure_scratch49 >> 16 << 16)) & 0xC000FFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch50 = (sdram->mc_video_protect_vpr_override << 12 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 13 >> 31 << 30) | ((sdram->mc_generalized_carveout1_bom >> 17 << 15) | ((sdram->mc_generalized_carveout3_bom >> 17) | (pmc->secure_scratch50 >> 15 << 15)) & 0xC0007FFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch51 = (sdram->mc_video_protect_vpr_override << 10 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 11 >> 31 << 30) | ((sdram->mc_generalized_carveout2_bom >> 17 << 15) | ((sdram->mc_generalized_carveout4_bom >> 17) | (pmc->secure_scratch51 >> 15 << 15)) & 0xC0007FFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch52 = (sdram->mc_video_protect_vpr_override << 9 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout3_cfg0 << 10 >> 28 << 27) | ((sdram->mc_video_protect_bom >> 20 << 15) | ((sdram->mc_generalized_carveout5_bom >> 17) | (pmc->secure_scratch52 >> 15 << 15)) & 0xF8007FFF) & 0x87FFFFFF) >> 1);
+	pmc->secure_scratch53 = (sdram->mc_video_protect_vpr_override1 << 27 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override1 << 30 >> 31 << 30) | ((sdram->mc_video_protect_vpr_override1 << 31 >> 2) | ((sdram->mc_video_protect_vpr_override >> 31 << 28) | ((2 * sdram->mc_video_protect_vpr_override >> 31 << 27) | ((4 * sdram->mc_video_protect_vpr_override >> 31 << 26) | ((32 * sdram->mc_video_protect_vpr_override >> 31 << 25) | ((sdram->mc_video_protect_vpr_override << 8 >> 31 << 24) | ((sdram->mc_sec_carveout_bom >> 20 << 12) | (sdram->mc_video_protect_size_mb & 0xFFF | (pmc->secure_scratch53 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch54 = (sdram->mc_video_protect_vpr_override1 << 19 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override1 << 20 >> 31 << 30) | ((sdram->mc_video_protect_vpr_override1 << 21 >> 31 << 29) | ((sdram->mc_video_protect_vpr_override1 << 22 >> 31 << 28) | ((sdram->mc_video_protect_vpr_override1 << 23 >> 31 << 27) | ((sdram->mc_video_protect_vpr_override1 << 24 >> 31 << 26) | ((sdram->mc_video_protect_vpr_override1 << 25 >> 31 << 25) | ((sdram->mc_video_protect_vpr_override1 << 26 >> 31 << 24) | ((sdram->mc_mts_carveout_bom >> 20 << 12) | (sdram->mc_sec_carveout_size_mb & 0xFFF | (pmc->secure_scratch54 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch55 = (sdram->mc_generalized_carveout2_cfg0 << 30 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout2_cfg0 << 30) | ((32 * sdram->mc_video_protect_vpr_override1 >> 31 << 29) | ((sdram->mc_video_protect_vpr_override1 << 6 >> 31 << 28) | ((sdram->mc_video_protect_vpr_override1 << 15 >> 31 << 27) | ((sdram->mc_video_protect_vpr_override1 << 16 >> 31 << 26) | ((sdram->mc_video_protect_vpr_override1 << 17 >> 31 << 25) | ((sdram->mc_video_protect_vpr_override1 << 18 >> 31 << 24) | (((u16)(sdram->mc_generalized_carveout4_size_128kb) << 12) & 0xFFFFFF | (sdram->mc_mts_carveout_size_mb & 0xFFF | (pmc->secure_scratch55 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch56 = ((u16)(sdram->mc_generalized_carveout1_cfg0) << 30 >> 31 << 31) | (2 * (((u16)(sdram->mc_generalized_carveout1_cfg0) << 30) | ((32 * sdram->mc_generalized_carveout2_cfg0 >> 31 << 29) | ((sdram->mc_generalized_carveout2_cfg0 << 6 >> 31 << 28) | ((sdram->mc_generalized_carveout2_cfg0 << 7 >> 31 << 27) | ((sdram->mc_generalized_carveout2_cfg0 << 8 >> 31 << 26) | ((sdram->mc_generalized_carveout2_cfg0 << 9 >> 31 << 25) | ((sdram->mc_generalized_carveout2_cfg0 << 29 >> 31 << 24) | (((u16)(sdram->mc_generalized_carveout2_size_128kb) << 12) & 0xFFFFFF | (sdram->mc_generalized_carveout3_size_128kb & 0xFFF | (pmc->secure_scratch56 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+	pmc->secure_scratch57 = ((u8)(sdram->mc_generalized_carveout3_cfg0) << 30 >> 31 << 31) | (2 * (((u8)(sdram->mc_generalized_carveout3_cfg0) << 30) | ((32 * sdram->mc_generalized_carveout1_cfg0 >> 31 << 29) | ((sdram->mc_generalized_carveout1_cfg0 << 6 >> 31 << 28) | ((sdram->mc_generalized_carveout1_cfg0 << 7 >> 31 << 27) | ((sdram->mc_generalized_carveout1_cfg0 << 8 >> 31 << 26) | ((sdram->mc_generalized_carveout1_cfg0 << 9 >> 31 << 25) | ((sdram->mc_generalized_carveout1_cfg0 << 29 >> 31 << 24) | ((sdram->mc_generalized_carveout5_size_128kb << 12) & 0xFFFFFF | (sdram->mc_generalized_carveout1_size_128kb & 0xFFF | (pmc->secure_scratch57 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1);
+
+	s32(mc_generalized_carveout1_access0, secure_scratch59);
+	s32(mc_generalized_carveout1_access1, secure_scratch60);
+	s32(mc_generalized_carveout1_access2, secure_scratch61);
+	s32(mc_generalized_carveout1_access3, secure_scratch62);
+	s32(mc_generalized_carveout1_access4, secure_scratch63);
+	s32(mc_generalized_carveout2_access0, secure_scratch64);
+	s32(mc_generalized_carveout2_access1, secure_scratch65);
+	s32(mc_generalized_carveout2_access2, secure_scratch66);
+	s32(mc_generalized_carveout2_access3, secure_scratch67);
+	s32(mc_generalized_carveout2_access4, secure_scratch68);
+	s32(mc_generalized_carveout3_access0, secure_scratch69);
+	s32(mc_generalized_carveout3_access1, secure_scratch70);
+	s32(mc_generalized_carveout3_access2, secure_scratch71);
+	s32(mc_generalized_carveout3_access3, secure_scratch72);
+	s32(mc_generalized_carveout3_access4, secure_scratch73);
+	s32(mc_generalized_carveout4_access0, secure_scratch74);
+	s32(mc_generalized_carveout4_access1, secure_scratch75);
+	s32(mc_generalized_carveout4_access2, secure_scratch76);
+	s32(mc_generalized_carveout4_access3, secure_scratch77);
+	s32(mc_generalized_carveout4_access4, secure_scratch78);
+	s32(mc_generalized_carveout5_access0, secure_scratch79);
+	s32(mc_generalized_carveout5_access1, secure_scratch80);
+	s32(mc_generalized_carveout5_access2, secure_scratch81);
+	s32(mc_generalized_carveout5_access3, secure_scratch82);
+	s32(mc_generalized_carveout1_force_internal_access0, secure_scratch84);
+	s32(mc_generalized_carveout1_force_internal_access1, secure_scratch85);
+	s32(mc_generalized_carveout1_force_internal_access2, secure_scratch86);
+	s32(mc_generalized_carveout1_force_internal_access3, secure_scratch87);
+	s32(mc_generalized_carveout1_force_internal_access4, secure_scratch88);
+	s32(mc_generalized_carveout2_force_internal_access0, secure_scratch89);
+	s32(mc_generalized_carveout2_force_internal_access1, secure_scratch90);
+	s32(mc_generalized_carveout2_force_internal_access2, secure_scratch91);
+	s32(mc_generalized_carveout2_force_internal_access3, secure_scratch92);
+	s32(mc_generalized_carveout2_force_internal_access4, secure_scratch93);
+	s32(mc_generalized_carveout3_force_internal_access0, secure_scratch94);
+	s32(mc_generalized_carveout3_force_internal_access1, secure_scratch95);
+	s32(mc_generalized_carveout3_force_internal_access2, secure_scratch96);
+	s32(mc_generalized_carveout3_force_internal_access3, secure_scratch97);
+	s32(mc_generalized_carveout3_force_internal_access4, secure_scratch98);
+	s32(mc_generalized_carveout4_force_internal_access0, secure_scratch99);
+	s32(mc_generalized_carveout4_force_internal_access1, secure_scratch100);
+	s32(mc_generalized_carveout4_force_internal_access2, secure_scratch101);
+	s32(mc_generalized_carveout4_force_internal_access3, secure_scratch102);
+	s32(mc_generalized_carveout4_force_internal_access4, secure_scratch103);
+	s32(mc_generalized_carveout5_force_internal_access0, secure_scratch104);
+	s32(mc_generalized_carveout5_force_internal_access1, secure_scratch105);
+	s32(mc_generalized_carveout5_force_internal_access2, secure_scratch106);
+	s32(mc_generalized_carveout5_force_internal_access3, secure_scratch107);
+
+	pmc->secure_scratch58 = 32 * (32 * sdram->mc_generalized_carveout3_cfg0 >> 31) | (16 * (sdram->mc_generalized_carveout3_cfg0 << 6 >> 31) | (8 * (sdram->mc_generalized_carveout3_cfg0 << 7 >> 31) | (4 * (sdram->mc_generalized_carveout3_cfg0 << 8 >> 31) | (2 * (sdram->mc_generalized_carveout3_cfg0 << 9 >> 31) | ((sdram->mc_generalized_carveout3_cfg0 << 29 >> 31) | 2 * (pmc->secure_scratch58 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF;
+
+	c32(0, scratch2);
+	s(pllm_input_divider, 7:0, scratch2, 7:0);
+	s(pllm_feedback_divider, 7:0, scratch2, 15:8);
+	s(pllm_post_divider, 4:0, scratch2, 20:16);
+	s(pllm_kvco, 0:0, scratch2, 17:17);
+	s(pllm_kcp, 1:0, scratch2, 19:18);
+
+	c32(0, scratch35);
+	s(pllm_setup_control, 15:0, scratch35, 15:0);
+
+	c32(0, scratch3);
+	s(pllm_input_divider, 7:0, scratch3, 7:0);
+	c(0x3e, scratch3, 15:8);
+	c(0, scratch3, 20:16);
+	s(pllm_kvco, 0:0, scratch3, 21:21);
+	s(pllm_kcp, 1:0, scratch3, 23:22);
+
+	c32(0, scratch36);
+	s(pllm_setup_control, 23:0, scratch36, 23:0);
+
+	c32(0, scratch4);
+	s(pllm_stable_time, 9:0, scratch4, 9:0); // s32(pllm_stable_time, scratch4);, s(pllm_stable_time, 31:0, scratch4, 31:10);
+	s(pllm_stable_time, 31:0, scratch4, 31:10);
+}
+
+#pragma GCC diagnostic pop
+*/
+void sdram_lp0_save_params(const void *params)
+{
+	// u32 chip_id = (APB_MISC(APB_MISC_GP_HIDREV) >> 4) & 0xF;
+
+	// if (chip_id != GP_HIDREV_MAJOR_T210B01)
+		_sdram_lp0_save_params_t210(params);
+	// else
+	// 	_sdram_lp0_save_params_t210b01(params);
+}

bdk/mem/sdram_lp0_param_t210.h

@@ -20,8 +20,8 @@
  * directly converting BCT config files (*.cfg) into C structure.
  */
 
-#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
+#ifndef __TEGRA210_SDRAM_PARAM_H__
-#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
+#define __TEGRA210_SDRAM_PARAM_H__
 
 #include <utils/types.h>
 
@@ -57,7 +57,7 @@ enum
 /**
  * Defines the SDRAM parameter structure
  */
-struct sdram_params
+struct sdram_params_t210
 {
 
 	/* Specifies the type of memory device */

bdk/mem/sdram_lp0_param_t210b01.h

@@ -0,0 +1,990 @@
+/*
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __TEGRA210B01_SDRAM_PARAM_H__
+#define __TEGRA210B01_SDRAM_PARAM_H__
+
+#include <utils/types.h>
+
+struct sdram_params_t210b01
+{
+	/* Specifies the type of memory device */
+	u32 memory_type;
+
+	/* MC/EMC clock source configuration */
+
+	/* Specifies the M value for PllM */
+	u32 pllm_input_divider;
+	/* Specifies the N value for PllM */
+	u32 pllm_feedback_divider;
+	/* Specifies the time to wait for PLLM to lock (in microseconds) */
+	u32 pllm_stable_time;
+	/* Specifies misc. control bits */
+	u32 pllm_setup_control;
+	/* Specifies the P value for PLLM */
+	u32 pllm_post_divider;
+	/* Specifies value for Charge Pump Gain Control */
+	u32 pllm_kcp;
+	/* Specifies VCO gain */
+	u32 pllm_kvco;
+	/* Spare BCT param */
+	u32 emc_bct_spare0;
+	/* Spare BCT param */
+	u32 emc_bct_spare1;
+	/* Spare BCT param */
+	u32 emc_bct_spare2;
+	/* Spare BCT param */
+	u32 emc_bct_spare3;
+	/* Spare BCT param */
+	u32 emc_bct_spare4;
+	/* Spare BCT param */
+	u32 emc_bct_spare5;
+	/* Spare BCT param */
+	u32 emc_bct_spare6;
+	/* Spare BCT param */
+	u32 emc_bct_spare7;
+	/* Spare BCT param */
+	u32 emc_bct_spare8;
+	/* Spare BCT param */
+	u32 emc_bct_spare9;
+	/* Spare BCT param */
+	u32 emc_bct_spare10;
+	/* Spare BCT param */
+	u32 emc_bct_spare11;
+	/* Spare BCT param */
+	u32 emc_bct_spare12;
+	/* Spare BCT param */
+	u32 emc_bct_spare13;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure0;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure1;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure2;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure3;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure4;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure5;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure6;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure7;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure8;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure9;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure10;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure11;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure12;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure13;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure14;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure15;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure16;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure17;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure18;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure19;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure20;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure21;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure22;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure23;
+
+	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
+	u32 emc_clock_source;
+	u32 emc_clock_source_dll;
+
+	/* Defines possible override for PLLLM_MISC2 */
+	u32 clk_rst_pllm_misc20_override;
+	/* enables override for PLLLM_MISC2 */
+	u32 clk_rst_pllm_misc20_override_enable;
+	/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
+	u32 clear_clock2_mc1;
+
+	/* Auto-calibration of EMC pads */
+
+	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
+	u32 emc_auto_cal_interval;
+	/*
+	 * Specifies the value for EMC_AUTO_CAL_CONFIG
+	 * Note: Trigger bits are set by the SDRAM code.
+	 */
+	u32 emc_auto_cal_config;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
+	u32 emc_auto_cal_config2;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
+	u32 emc_auto_cal_config3;
+	u32 emc_auto_cal_config4;
+	u32 emc_auto_cal_config5;
+	u32 emc_auto_cal_config6;
+	u32 emc_auto_cal_config7;
+	u32 emc_auto_cal_config8;
+	u32 emc_auto_cal_config9;
+
+	/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
+	u32 emc_auto_cal_vref_sel0;
+	u32 emc_auto_cal_vref_sel1;
+
+	/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
+	u32 emc_auto_cal_channel;
+
+	/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
+	u32 emc_pmacro_auto_cal_cfg0;
+	u32 emc_pmacro_auto_cal_cfg1;
+	u32 emc_pmacro_auto_cal_cfg2;
+
+	u32 emc_pmacro_rx_term;
+	u32 emc_pmacro_dq_tx_drive;
+	u32 emc_pmacro_ca_tx_drive;
+	u32 emc_pmacro_cmd_tx_drive;
+	u32 emc_pmacro_auto_cal_common;
+	u32 emc_pmacro_zcrtl;
+
+	/*
+	 * Specifies the time for the calibration
+	 * to stabilize (in microseconds)
+	 */
+	u32 emc_auto_cal_wait;
+
+	u32 emc_xm2_comp_pad_ctrl;
+	u32 emc_xm2_comp_pad_ctrl2;
+	u32 emc_xm2_comp_pad_ctrl3;
+
+	/*
+	 * DRAM size information
+	 * Specifies the value for EMC_ADR_CFG
+	 */
+	u32 emc_adr_cfg;
+
+	/*
+	 * Specifies the time to wait after asserting pin
+	 * CKE (in microseconds)
+	 */
+	u32 emc_pin_program_wait;
+	/* Specifies the extra delay before/after pin RESET/CKE command */
+	u32 emc_pin_extra_wait;
+
+	u32 emc_pin_gpio_enable;
+	u32 emc_pin_gpio;
+
+	/*
+	 * Specifies the extra delay after the first writing
+	 * of EMC_TIMING_CONTROL
+	 */
+	u32 emc_timing_control_wait;
+
+	/* Timing parameters required for the SDRAM */
+
+	/* Specifies the value for EMC_RC */
+	u32 emc_rc;
+	/* Specifies the value for EMC_RFC */
+	u32 emc_rfc;
+
+	u32 emc_rfc_pb;
+	u32 emc_ref_ctrl2;
+
+	/* Specifies the value for EMC_RFC_SLR */
+	u32 emc_rfc_slr;
+	/* Specifies the value for EMC_RAS */
+	u32 emc_ras;
+	/* Specifies the value for EMC_RP */
+	u32 emc_rp;
+	/* Specifies the value for EMC_R2R */
+	u32 emc_r2r;
+	/* Specifies the value for EMC_W2W */
+	u32 emc_w2w;
+	/* Specifies the value for EMC_R2W */
+	u32 emc_r2w;
+	/* Specifies the value for EMC_W2R */
+	u32 emc_w2r;
+	/* Specifies the value for EMC_R2P */
+	u32 emc_r2p;
+	/* Specifies the value for EMC_W2P */
+	u32 emc_w2p;
+	/* Specifies the value for EMC_RD_RCD */
+
+	u32 emc_tppd;
+	u32 emc_trtm;
+	u32 emc_twtm;
+	u32 emc_tratm;
+	u32 emc_twatm;
+	u32 emc_tr2ref;
+	u32 emc_ccdmw;
+
+	u32 emc_rd_rcd;
+	/* Specifies the value for EMC_WR_RCD */
+	u32 emc_wr_rcd;
+	/* Specifies the value for EMC_RRD */
+	u32 emc_rrd;
+	/* Specifies the value for EMC_REXT */
+	u32 emc_rext;
+	/* Specifies the value for EMC_WEXT */
+	u32 emc_wext;
+	/* Specifies the value for EMC_WDV */
+	u32 emc_wdv;
+
+	u32 emc_wdv_chk;
+	u32 emc_wsv;
+	u32 emc_wev;
+
+	/* Specifies the value for EMC_WDV_MASK */
+	u32 emc_wdv_mask;
+
+	u32 emc_ws_duration;
+	u32 emc_we_duration;
+
+	/* Specifies the value for EMC_QUSE */
+	u32 emc_quse;
+	/* Specifies the value for EMC_QUSE_WIDTH */
+	u32 emc_quse_width;
+	/* Specifies the value for EMC_IBDLY */
+	u32 emc_ibdly;
+
+	u32 emc_obdly;
+
+	/* Specifies the value for EMC_EINPUT */
+	u32 emc_einput;
+	/* Specifies the value for EMC_EINPUT_DURATION */
+	u32 emc_einput_duration;
+	/* Specifies the value for EMC_PUTERM_EXTRA */
+	u32 emc_puterm_extra;
+	/* Specifies the value for EMC_PUTERM_WIDTH */
+	u32 emc_puterm_width;
+
+	u32 emc_qrst;
+	u32 emc_qsafe;
+	u32 emc_rdv;
+	u32 emc_rdv_mask;
+
+	u32 emc_rdv_early;
+	u32 emc_rdv_early_mask;
+
+	/* Specifies the value for EMC_QPOP */
+	u32 emc_qpop;
+
+	/* Specifies the value for EMC_REFRESH */
+	u32 emc_refresh;
+	/* Specifies the value for EMC_BURST_REFRESH_NUM */
+	u32 emc_burst_refresh_num;
+	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
+	u32 emc_prerefresh_req_cnt;
+	/* Specifies the value for EMC_PDEX2WR */
+	u32 emc_pdex2wr;
+	/* Specifies the value for EMC_PDEX2RD */
+	u32 emc_pdex2rd;
+	/* Specifies the value for EMC_PCHG2PDEN */
+	u32 emc_pchg2pden;
+	/* Specifies the value for EMC_ACT2PDEN */
+	u32 emc_act2pden;
+	/* Specifies the value for EMC_AR2PDEN */
+	u32 emc_ar2pden;
+	/* Specifies the value for EMC_RW2PDEN */
+	u32 emc_rw2pden;
+
+	u32 emc_cke2pden;
+	u32 emc_pdex2che;
+	u32 emc_pdex2mrr;
+
+	/* Specifies the value for EMC_TXSR */
+	u32 emc_txsr;
+	/* Specifies the value for EMC_TXSRDLL */
+	u32 emc_txsr_dll;
+	/* Specifies the value for EMC_TCKE */
+	u32 emc_tcke;
+	/* Specifies the value for EMC_TCKESR */
+	u32 emc_tckesr;
+	/* Specifies the value for EMC_TPD */
+	u32 emc_tpd;
+	/* Specifies the value for EMC_TFAW */
+	u32 emc_tfaw;
+	/* Specifies the value for EMC_TRPAB */
+	u32 emc_trpab;
+	/* Specifies the value for EMC_TCLKSTABLE */
+	u32 emc_tclkstable;
+	/* Specifies the value for EMC_TCLKSTOP */
+	u32 emc_tclkstop;
+	/* Specifies the value for EMC_TREFBW */
+	u32 emc_trefbw;
+
+	/* FBIO configuration values */
+
+	/* Specifies the value for EMC_FBIO_CFG5 */
+	u32 emc_fbio_cfg5;
+	/* Specifies the value for EMC_FBIO_CFG7 */
+	u32 emc_fbio_cfg7;
+	u32 emc_fbio_cfg8;
+
+	/* Command mapping for CMD brick 0 */
+	u32 emc_cmd_mapping_cmd0_0;
+	u32 emc_cmd_mapping_cmd0_1;
+	u32 emc_cmd_mapping_cmd0_2;
+	u32 emc_cmd_mapping_cmd1_0;
+	u32 emc_cmd_mapping_cmd1_1;
+	u32 emc_cmd_mapping_cmd1_2;
+	u32 emc_cmd_mapping_cmd2_0;
+	u32 emc_cmd_mapping_cmd2_1;
+	u32 emc_cmd_mapping_cmd2_2;
+	u32 emc_cmd_mapping_cmd3_0;
+	u32 emc_cmd_mapping_cmd3_1;
+	u32 emc_cmd_mapping_cmd3_2;
+	u32 emc_cmd_mapping_byte;
+
+	/* Specifies the value for EMC_FBIO_SPARE */
+	u32 emc_fbio_spare;
+
+	/* Specifies the value for EMC_CFG_RSV */
+	u32 emc_cfg_rsv;
+
+	/* MRS command values */
+
+	/* Specifies the value for EMC_MRS */
+	u32 emc_mrs;
+	/* Specifies the MP0 command to initialize mode registers */
+	u32 emc_emrs;
+	/* Specifies the MP2 command to initialize mode registers */
+	u32 emc_emrs2;
+	/* Specifies the MP3 command to initialize mode registers */
+	u32 emc_emrs3;
+	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
+	u32 emc_mrw1;
+	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
+	u32 emc_mrw2;
+	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
+	u32 emc_mrw3;
+	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
+	u32 emc_mrw4;
+
+	/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
+	u32 emc_mrw6;
+	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
+	u32 emc_mrw8;
+	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
+	u32 emc_mrw9;
+	/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
+	u32 emc_mrw10;
+	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
+	u32 emc_mrw12;
+	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
+	u32 emc_mrw13;
+	/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
+	u32 emc_mrw14;
+
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at cold boot
+	 */
+	u32 emc_mrw_extra;
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at warm boot
+	 */
+	u32 emc_warm_boot_mrw_extra;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * warm boot
+	 */
+	u32 emc_warm_boot_extramode_reg_write_enable;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * cold boot
+	 */
+	u32 emc_extramode_reg_write_enable;
+
+	/* Specifies the EMC_MRW reset command value */
+	u32 emc_mrw_reset_command;
+	/* Specifies the EMC Reset wait time (in microseconds) */
+	u32 emc_mrw_reset_ninit_wait;
+	/* Specifies the value for EMC_MRS_WAIT_CNT */
+	u32 emc_mrs_wait_cnt;
+	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
+	u32 emc_mrs_wait_cnt2;
+
+	/* EMC miscellaneous configurations */
+
+	/* Specifies the value for EMC_CFG */
+	u32 emc_cfg;
+	/* Specifies the value for EMC_CFG_2 */
+	u32 emc_cfg2;
+	/* Specifies the pipe bypass controls */
+	u32 emc_cfg_pipe;
+
+	u32 emc_cfg_pipe_clk;
+	u32 emc_fdpd_ctrl_cmd_no_ramp;
+	u32 emc_cfg_update;
+
+	/* Specifies the value for EMC_DBG */
+	u32 emc_dbg;
+
+	u32 emc_dbg_write_mux;
+
+	/* Specifies the value for EMC_CMDQ */
+	u32 emc_cmd_q;
+	/* Specifies the value for EMC_MC2EMCQ */
+	u32 emc_mc2emc_q;
+	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
+	u32 emc_dyn_self_ref_control;
+
+	/* Specifies the value for MEM_INIT_DONE */
+	u32 ahb_arbitration_xbar_ctrl_meminit_done;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL */
+	u32 emc_cfg_dig_dll;
+	u32 emc_cfg_dig_dll_1;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
+	u32 emc_cfg_dig_dll_period;
+	/* Specifies the value of *DEV_SELECTN of various EMC registers */
+	u32 emc_dev_select;
+
+	/* Specifies the value for EMC_SEL_DPD_CTRL */
+	u32 emc_sel_dpd_ctrl;
+
+	/* Pads trimmer delays */
+	u32 emc_fdpd_ctrl_dq;
+	u32 emc_fdpd_ctrl_cmd;
+	u32 emc_pmacro_ib_vref_dq_0;
+	u32 emc_pmacro_ib_vref_dq_1;
+	u32 emc_pmacro_ib_vref_dqs_0;
+	u32 emc_pmacro_ib_vref_dqs_1;
+	u32 emc_pmacro_ib_rxrt;
+	u32 emc_cfg_pipe1;
+	u32 emc_cfg_pipe2;
+
+	/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
+	u32 emc_pmacro_quse_ddll_rank0_0;
+	u32 emc_pmacro_quse_ddll_rank0_1;
+	u32 emc_pmacro_quse_ddll_rank0_2;
+	u32 emc_pmacro_quse_ddll_rank0_3;
+	u32 emc_pmacro_quse_ddll_rank0_4;
+	u32 emc_pmacro_quse_ddll_rank0_5;
+	u32 emc_pmacro_quse_ddll_rank1_0;
+	u32 emc_pmacro_quse_ddll_rank1_1;
+	u32 emc_pmacro_quse_ddll_rank1_2;
+	u32 emc_pmacro_quse_ddll_rank1_3;
+	u32 emc_pmacro_quse_ddll_rank1_4;
+	u32 emc_pmacro_quse_ddll_rank1_5;
+
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
+
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
+
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
+
+	u32 emc_pmacro_ddll_long_cmd_0;
+	u32 emc_pmacro_ddll_long_cmd_1;
+	u32 emc_pmacro_ddll_long_cmd_2;
+	u32 emc_pmacro_ddll_long_cmd_3;
+	u32 emc_pmacro_ddll_long_cmd_4;
+	u32 emc_pmacro_ddll_short_cmd_0;
+	u32 emc_pmacro_ddll_short_cmd_1;
+	u32 emc_pmacro_ddll_short_cmd_2;
+
+	u32 emc_pmacro_ddll_periodic_offset;
+
+	/*
+	 * Specifies the delay after asserting CKE pin during a WarmBoot0
+	 * sequence (in microseconds)
+	 */
+	u32 warm_boot_wait;
+
+	/* Specifies the value for EMC_ODT_WRITE */
+	u32 emc_odt_write;
+
+	/* Periodic ZQ calibration */
+
+	/*
+	 * Specifies the value for EMC_ZCAL_INTERVAL
+	 * Value 0 disables ZQ calibration
+	 */
+	u32 emc_zcal_interval;
+	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
+	u32 emc_zcal_wait_cnt;
+	/* Specifies the value for EMC_ZCAL_MRW_CMD */
+	u32 emc_zcal_mrw_cmd;
+
+	/* DRAM initialization sequence flow control */
+
+	/* Specifies the MRS command value for resetting DLL */
+	u32 emc_mrs_reset_dll;
+	/* Specifies the command for ZQ initialization of device 0 */
+	u32 emc_zcal_init_dev0;
+	/* Specifies the command for ZQ initialization of device 1 */
+	u32 emc_zcal_init_dev1;
+	/*
+	 * Specifies the wait time after programming a ZQ initialization
+	 * command (in microseconds)
+	 */
+	u32 emc_zcal_init_wait;
+	/*
+	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
+	 * and warm boot [bit 1]
+	 */
+	u32 emc_zcal_warm_cold_boot_enables;
+
+	/*
+	 * Specifies the MRW command to LPDDR2 for ZQ calibration
+	 * on warmboot
+	 */
+	/* Is issued to both devices separately */
+	u32 emc_mrw_lpddr2zcal_warm_boot;
+	/*
+	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
+	 * Is issued to both devices separately
+	 */
+	u32 emc_zqcal_ddr3_warm_boot;
+
+	u32 emc_zqcal_lpddr4_warm_boot;
+
+	/*
+	 * Specifies the wait time for ZQ calibration on warmboot
+	 * (in microseconds)
+	 */
+	u32 emc_zcal_warm_boot_wait;
+	/*
+	 * Specifies the enable for DRAM Mode Register programming
+	 * at warm boot
+	 */
+	u32 emc_mrs_warm_boot_enable;
+	/*
+	 * Specifies the wait time after sending an MRS DLL reset command
+	 * in microseconds)
+	 */
+	u32 emc_mrs_reset_dll_wait;
+	/* Specifies the extra MRS command to initialize mode registers */
+	u32 emc_mrs_extra;
+	/* Specifies the extra MRS command at warm boot */
+	u32 emc_warm_boot_mrs_extra;
+	/* Specifies the EMRS command to enable the DDR2 DLL */
+	u32 emc_emrs_ddr2_dll_enable;
+	/* Specifies the MRS command to reset the DDR2 DLL */
+	u32 emc_mrs_ddr2_dll_reset;
+	/* Specifies the EMRS command to set OCD calibration */
+	u32 emc_emrs_ddr2_ocd_calib;
+	/*
+	 * Specifies the wait between initializing DDR and setting OCD
+	 * calibration (in microseconds)
+	 */
+	u32 emc_ddr2_wait;
+	/* Specifies the value for EMC_CLKEN_OVERRIDE */
+	u32 emc_clken_override;
+	/*
+	 * Specifies LOG2 of the extra refresh numbers after booting
+	 * Program 0 to disable
+	 */
+	u32 emc_extra_refresh_num;
+	/* Specifies the master override for all EMC clocks */
+	u32 emc_clken_override_allwarm_boot;
+	/* Specifies the master override for all MC clocks */
+	u32 mc_clken_override_allwarm_boot;
+	/* Specifies digital dll period, choosing between 4 to 64 ms */
+	u32 emc_cfg_dig_dll_period_warm_boot;
+
+	/* Pad controls */
+
+	/* Specifies the value for PMC_VDDP_SEL */
+	u32 pmc_vddp_sel;
+	/* Specifies the wait time after programming PMC_VDDP_SEL */
+	u32 pmc_vddp_sel_wait;
+	/* Specifies the value for PMC_DDR_CFG */
+	u32 pmc_ddr_cfg;
+	/* Specifies the value for PMC_IO_DPD3_REQ */
+	u32 pmc_io_dpd3_req;
+	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
+	u32 pmc_io_dpd3_req_wait;
+
+	u32 pmc_io_dpd4_req_wait;
+
+	/* Specifies the value for PMC_REG_SHORT */
+	u32 pmc_reg_short;
+	/* Specifies the value for PMC_NO_IOPOWER */
+	u32 pmc_no_io_power;
+
+	u32 pmc_ddr_ctrl_wait;
+	u32 pmc_ddr_ctrl;
+
+	/* Specifies the value for EMC_ACPD_CONTROL */
+	u32 emc_acpd_control;
+
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
+	u32 emc_swizzle_rank0_byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
+	u32 emc_swizzle_rank0_byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
+	u32 emc_swizzle_rank0_byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
+	u32 emc_swizzle_rank0_byte3;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
+	u32 emc_swizzle_rank1_byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
+	u32 emc_swizzle_rank1_byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
+	u32 emc_swizzle_rank1_byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
+	u32 emc_swizzle_rank1_byte3;
+
+	/* Specifies the value for EMC_TXDSRVTTGEN */
+	u32 emc_txdsrvttgen;
+
+	/* Specifies the value for EMC_DATA_BRLSHFT_0 */
+	u32 emc_data_brlshft0;
+	u32 emc_data_brlshft1;
+
+	u32 emc_dqs_brlshft0;
+	u32 emc_dqs_brlshft1;
+
+	u32 emc_cmd_brlshft0;
+	u32 emc_cmd_brlshft1;
+	u32 emc_cmd_brlshft2;
+	u32 emc_cmd_brlshft3;
+
+	u32 emc_quse_brlshft0;
+	u32 emc_quse_brlshft1;
+	u32 emc_quse_brlshft2;
+	u32 emc_quse_brlshft3;
+
+	u32 emc_dll_cfg0;
+	u32 emc_dll_cfg1;
+
+	u32 emc_pmc_scratch1;
+	u32 emc_pmc_scratch2;
+	u32 emc_pmc_scratch3;
+
+	u32 emc_pmacro_pad_cfg_ctrl;
+
+	u32 emc_pmacro_vttgen_ctrl0;
+	u32 emc_pmacro_vttgen_ctrl1;
+	u32 emc_pmacro_vttgen_ctrl2;
+	u32 emc_pmacro_dsr_vttgen_ctrl0;
+	u32 emc_pmacro_brick_ctrl_rfu1;
+	u32 emc_pmacro_cmd_brick_ctrl_fdpd;
+	u32 emc_pmacro_brick_ctrl_rfu2;
+	u32 emc_pmacro_data_brick_ctrl_fdpd;
+	u32 emc_pmacro_bg_bias_ctrl0;
+	u32 emc_pmacro_data_pad_rx_ctrl;
+	u32 emc_pmacro_cmd_pad_rx_ctrl;
+	u32 emc_pmacro_data_rx_term_mode;
+	u32 emc_pmacro_cmd_rx_term_mode;
+	u32 emc_pmacro_data_pad_tx_ctrl;
+	u32 emc_pmacro_cmd_pad_tx_ctrl;
+	u32 emc_cfg3;
+
+	u32 emc_pmacro_tx_pwrd0;
+	u32 emc_pmacro_tx_pwrd1;
+	u32 emc_pmacro_tx_pwrd2;
+	u32 emc_pmacro_tx_pwrd3;
+	u32 emc_pmacro_tx_pwrd4;
+	u32 emc_pmacro_tx_pwrd5;
+
+	u32 emc_config_sample_delay;
+
+	u32 emc_pmacro_brick_mapping0;
+	u32 emc_pmacro_brick_mapping1;
+	u32 emc_pmacro_brick_mapping2;
+
+	u32 emc_pmacro_tx_sel_clk_src0;
+	u32 emc_pmacro_tx_sel_clk_src1;
+	u32 emc_pmacro_tx_sel_clk_src2;
+	u32 emc_pmacro_tx_sel_clk_src3;
+	u32 emc_pmacro_tx_sel_clk_src4;
+	u32 emc_pmacro_tx_sel_clk_src5;
+
+	u32 emc_pmacro_perbit_fgcg_ctrl0;
+	u32 emc_pmacro_perbit_fgcg_ctrl1;
+	u32 emc_pmacro_perbit_fgcg_ctrl2;
+	u32 emc_pmacro_perbit_fgcg_ctrl3;
+	u32 emc_pmacro_perbit_fgcg_ctrl4;
+	u32 emc_pmacro_perbit_fgcg_ctrl5;
+	u32 emc_pmacro_perbit_rfu_ctrl0;
+	u32 emc_pmacro_perbit_rfu_ctrl1;
+	u32 emc_pmacro_perbit_rfu_ctrl2;
+	u32 emc_pmacro_perbit_rfu_ctrl3;
+	u32 emc_pmacro_perbit_rfu_ctrl4;
+	u32 emc_pmacro_perbit_rfu_ctrl5;
+	u32 emc_pmacro_perbit_rfu1_ctrl0;
+	u32 emc_pmacro_perbit_rfu1_ctrl1;
+	u32 emc_pmacro_perbit_rfu1_ctrl2;
+	u32 emc_pmacro_perbit_rfu1_ctrl3;
+	u32 emc_pmacro_perbit_rfu1_ctrl4;
+	u32 emc_pmacro_perbit_rfu1_ctrl5;
+
+	u32 emc_pmacro_data_pi_ctrl;
+	u32 emc_pmacro_cmd_pi_ctrl;
+
+	u32 emc_pmacro_ddll_bypass;
+
+	u32 emc_pmacro_ddll_pwrd0;
+	u32 emc_pmacro_ddll_pwrd1;
+	u32 emc_pmacro_ddll_pwrd2;
+
+	u32 emc_pmacro_cmd_ctrl0;
+	u32 emc_pmacro_cmd_ctrl1;
+	u32 emc_pmacro_cmd_ctrl2;
+
+	/* DRAM size information */
+
+	/* Specifies the value for MC_EMEM_ADR_CFG */
+	u32 mc_emem_adr_cfg;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
+	u32 mc_emem_adr_cfg_dev0;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
+	u32 mc_emem_adr_cfg_dev1;
+
+	u32 mc_emem_adr_cfg_channel_mask;
+
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
+	u32 mc_emem_adr_cfg_bank_mask0;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
+	u32 mc_emem_adr_cfg_bank_mask1;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
+	u32 mc_emem_adr_cfg_bank_mask2;
+
+	/*
+	 * Specifies the value for MC_EMEM_CFG which holds the external memory
+	 * size (in KBytes)
+	 */
+	u32 mc_emem_cfg;
+
+	/* MC arbitration configuration */
+
+	/* Specifies the value for MC_EMEM_ARB_CFG */
+	u32 mc_emem_arb_cfg;
+	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
+	u32 mc_emem_arb_outstanding_req;
+
+	u32 emc_emem_arb_refpb_hp_ctrl;
+	u32 emc_emem_arb_refpb_bank_ctrl;
+
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
+	u32 mc_emem_arb_timing_rcd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
+	u32 mc_emem_arb_timing_rp;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
+	u32 mc_emem_arb_timing_rc;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
+	u32 mc_emem_arb_timing_ras;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
+	u32 mc_emem_arb_timing_faw;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
+	u32 mc_emem_arb_timing_rrd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
+	u32 mc_emem_arb_timing_rap2pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
+	u32 mc_emem_arb_timing_wap2pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
+	u32 mc_emem_arb_timing_r2r;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
+	u32 mc_emem_arb_timing_w2w;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
+	u32 mc_emem_arb_timing_r2w;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
+	u32 mc_emem_arb_timing_w2r;
+
+	u32 mc_emem_arb_timing_rfcpb;
+
+	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
+	u32 mc_emem_arb_da_turns;
+	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
+	u32 mc_emem_arb_da_covers;
+	/* Specifies the value for MC_EMEM_ARB_MISC0 */
+	u32 mc_emem_arb_misc0;
+	/* Specifies the value for MC_EMEM_ARB_MISC1 */
+	u32 mc_emem_arb_misc1;
+	u32 mc_emem_arb_misc2;
+
+	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
+	u32 mc_emem_arb_ring1_throttle;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
+	u32 mc_emem_arb_override;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
+	u32 mc_emem_arb_override1;
+	/* Specifies the value for MC_EMEM_ARB_RSV */
+	u32 mc_emem_arb_rsv;
+
+	u32 mc_da_cfg0;
+	u32 mc_emem_arb_timing_ccdmw;
+
+	/* Specifies the value for MC_CLKEN_OVERRIDE */
+	u32 mc_clken_override;
+
+	/* Specifies the value for MC_STAT_CONTROL */
+	u32 mc_stat_control;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
+	u32 mc_video_protect_bom;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
+	u32 mc_video_protect_bom_adr_hi;
+	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
+	u32 mc_video_protect_size_mb;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
+	u32 mc_video_protect_vpr_override;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
+	u32 mc_video_protect_vpr_override1;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
+	u32 mc_video_protect_gpu_override0;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
+	u32 mc_video_protect_gpu_override1;
+	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
+	u32 mc_sec_carveout_bom;
+	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
+	u32 mc_sec_carveout_adr_hi;
+	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
+	u32 mc_sec_carveout_size_mb;
+	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
+	u32 mc_video_protect_write_access;
+	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
+	u32 mc_sec_carveout_protect_write_access;
+
+	u32 mc_generalized_carveout1_bom;
+	u32 mc_generalized_carveout1_bom_hi;
+	u32 mc_generalized_carveout1_size_128kb;
+	u32 mc_generalized_carveout1_access0;
+	u32 mc_generalized_carveout1_access1;
+	u32 mc_generalized_carveout1_access2;
+	u32 mc_generalized_carveout1_access3;
+	u32 mc_generalized_carveout1_access4;
+	u32 mc_generalized_carveout1_force_internal_access0;
+	u32 mc_generalized_carveout1_force_internal_access1;
+	u32 mc_generalized_carveout1_force_internal_access2;
+	u32 mc_generalized_carveout1_force_internal_access3;
+	u32 mc_generalized_carveout1_force_internal_access4;
+	u32 mc_generalized_carveout1_cfg0;
+
+	u32 mc_generalized_carveout2_bom;
+	u32 mc_generalized_carveout2_bom_hi;
+	u32 mc_generalized_carveout2_size_128kb;
+	u32 mc_generalized_carveout2_access0;
+	u32 mc_generalized_carveout2_access1;
+	u32 mc_generalized_carveout2_access2;
+	u32 mc_generalized_carveout2_access3;
+	u32 mc_generalized_carveout2_access4;
+	u32 mc_generalized_carveout2_force_internal_access0;
+	u32 mc_generalized_carveout2_force_internal_access1;
+	u32 mc_generalized_carveout2_force_internal_access2;
+	u32 mc_generalized_carveout2_force_internal_access3;
+	u32 mc_generalized_carveout2_force_internal_access4;
+	u32 mc_generalized_carveout2_cfg0;
+
+	u32 mc_generalized_carveout3_bom;
+	u32 mc_generalized_carveout3_bom_hi;
+	u32 mc_generalized_carveout3_size_128kb;
+	u32 mc_generalized_carveout3_access0;
+	u32 mc_generalized_carveout3_access1;
+	u32 mc_generalized_carveout3_access2;
+	u32 mc_generalized_carveout3_access3;
+	u32 mc_generalized_carveout3_access4;
+	u32 mc_generalized_carveout3_force_internal_access0;
+	u32 mc_generalized_carveout3_force_internal_access1;
+	u32 mc_generalized_carveout3_force_internal_access2;
+	u32 mc_generalized_carveout3_force_internal_access3;
+	u32 mc_generalized_carveout3_force_internal_access4;
+	u32 mc_generalized_carveout3_cfg0;
+
+	u32 mc_generalized_carveout4_bom;
+	u32 mc_generalized_carveout4_bom_hi;
+	u32 mc_generalized_carveout4_size_128kb;
+	u32 mc_generalized_carveout4_access0;
+	u32 mc_generalized_carveout4_access1;
+	u32 mc_generalized_carveout4_access2;
+	u32 mc_generalized_carveout4_access3;
+	u32 mc_generalized_carveout4_access4;
+	u32 mc_generalized_carveout4_force_internal_access0;
+	u32 mc_generalized_carveout4_force_internal_access1;
+	u32 mc_generalized_carveout4_force_internal_access2;
+	u32 mc_generalized_carveout4_force_internal_access3;
+	u32 mc_generalized_carveout4_force_internal_access4;
+	u32 mc_generalized_carveout4_cfg0;
+
+	u32 mc_generalized_carveout5_bom;
+	u32 mc_generalized_carveout5_bom_hi;
+	u32 mc_generalized_carveout5_size_128kb;
+	u32 mc_generalized_carveout5_access0;
+	u32 mc_generalized_carveout5_access1;
+	u32 mc_generalized_carveout5_access2;
+	u32 mc_generalized_carveout5_access3;
+	u32 mc_generalized_carveout5_access4;
+	u32 mc_generalized_carveout5_force_internal_access0;
+	u32 mc_generalized_carveout5_force_internal_access1;
+	u32 mc_generalized_carveout5_force_internal_access2;
+	u32 mc_generalized_carveout5_force_internal_access3;
+	u32 mc_generalized_carveout5_force_internal_access4;
+	u32 mc_generalized_carveout5_cfg0;
+
+	/* Specifies enable for CA training */
+	u32 emc_ca_training_enable;
+	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
+	u32 swizzle_rank_byte_encode;
+	/* Specifies enable and offset for patched boot rom write */
+	u32 boot_rom_patch_control;
+	/* Specifies data for patched boot rom write */
+	u32 boot_rom_patch_data;
+
+	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
+	u32 mc_mts_carveout_bom;
+	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
+	u32 mc_mts_carveout_adr_hi;
+	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
+	u32 mc_mts_carveout_size_mb;
+	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
+	u32 mc_mts_carveout_reg_ctrl;
+
+	u32 mc_untranslated_region_check;
+
+	/* Just a place holder for special usage when there is no BCT for certain registers */
+	u32 bct_na;
+};
+
+#endif

bdk/mem/sdram_param_t210.h

@@ -37,7 +37,7 @@
 /**
  * Defines the SDRAM parameter structure
  */
-typedef struct _sdram_params
+typedef struct _sdram_params_t210_t
 {
 	/* Specifies the type of memory device */
 	u32 memory_type;
@@ -925,6 +925,6 @@ typedef struct _sdram_params
 	u32 mc_mts_carveout_size_mb;
 	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
 	u32 mc_mts_carveout_reg_ctrl;
-} sdram_params_t;
+} sdram_params_t210_t;
 
 #endif

bdk/mem/sdram_param_t210b01.h

@@ -0,0 +1,989 @@
+/*
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _SDRAM_PARAM_T210B01_H_
+#define _SDRAM_PARAM_T210B01_H_
+
+typedef struct _sdram_params_t210b01_t
+{
+	/* Specifies the type of memory device */
+	u32 memory_type;
+
+	/* MC/EMC clock source configuration */
+
+	/* Specifies the M value for PllM */
+	u32 pllm_input_divider;
+	/* Specifies the N value for PllM */
+	u32 pllm_feedback_divider;
+	/* Specifies the time to wait for PLLM to lock (in microseconds) */
+	u32 pllm_stable_time;
+	/* Specifies misc. control bits */
+	u32 pllm_setup_control;
+	/* Specifies the P value for PLLM */
+	u32 pllm_post_divider;
+	/* Specifies value for Charge Pump Gain Control */
+	u32 pllm_kcp;
+	/* Specifies VCO gain */
+	u32 pllm_kvco;
+	/* Spare BCT param */
+	u32 emc_bct_spare0;
+	/* Spare BCT param */
+	u32 emc_bct_spare1;
+	/* Spare BCT param */
+	u32 emc_bct_spare2;
+	/* Spare BCT param */
+	u32 emc_bct_spare3;
+	/* Spare BCT param */
+	u32 emc_bct_spare4;
+	/* Spare BCT param */
+	u32 emc_bct_spare5;
+	/* Spare BCT param */
+	u32 emc_bct_spare6;
+	/* Spare BCT param */
+	u32 emc_bct_spare7;
+	/* Spare BCT param */
+	u32 emc_bct_spare8;
+	/* Spare BCT param */
+	u32 emc_bct_spare9;
+	/* Spare BCT param */
+	u32 emc_bct_spare10;
+	/* Spare BCT param */
+	u32 emc_bct_spare11;
+	/* Spare BCT param */
+	u32 emc_bct_spare12;
+	/* Spare BCT param */
+	u32 emc_bct_spare13;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure0;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure1;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure2;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure3;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure4;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure5;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure6;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure7;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure8;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure9;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure10;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure11;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure12;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure13;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure14;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure15;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure16;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure17;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure18;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure19;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure20;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure21;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure22;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure23;
+
+	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
+	u32 emc_clock_source;
+	u32 emc_clock_source_dll;
+
+	/* Defines possible override for PLLLM_MISC2 */
+	u32 clk_rst_pllm_misc20_override;
+	/* enables override for PLLLM_MISC2 */
+	u32 clk_rst_pllm_misc20_override_enable;
+	/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
+	u32 clear_clock2_mc1;
+
+	/* Auto-calibration of EMC pads */
+
+	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
+	u32 emc_auto_cal_interval;
+	/*
+	 * Specifies the value for EMC_AUTO_CAL_CONFIG
+	 * Note: Trigger bits are set by the SDRAM code.
+	 */
+	u32 emc_auto_cal_config;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
+	u32 emc_auto_cal_config2;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
+	u32 emc_auto_cal_config3;
+	u32 emc_auto_cal_config4;
+	u32 emc_auto_cal_config5;
+	u32 emc_auto_cal_config6;
+	u32 emc_auto_cal_config7;
+	u32 emc_auto_cal_config8;
+	u32 emc_auto_cal_config9;
+
+	/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
+	u32 emc_auto_cal_vref_sel0;
+	u32 emc_auto_cal_vref_sel1;
+
+	/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
+	u32 emc_auto_cal_channel;
+
+	/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
+	u32 emc_pmacro_auto_cal_cfg0;
+	u32 emc_pmacro_auto_cal_cfg1;
+	u32 emc_pmacro_auto_cal_cfg2;
+
+	u32 emc_pmacro_rx_term;
+	u32 emc_pmacro_dq_tx_drive;
+	u32 emc_pmacro_ca_tx_drive;
+	u32 emc_pmacro_cmd_tx_drive;
+	u32 emc_pmacro_auto_cal_common;
+	u32 emc_pmacro_zcrtl;
+
+	/*
+	 * Specifies the time for the calibration
+	 * to stabilize (in microseconds)
+	 */
+	u32 emc_auto_cal_wait;
+
+	u32 emc_xm2_comp_pad_ctrl;
+	u32 emc_xm2_comp_pad_ctrl2;
+	u32 emc_xm2_comp_pad_ctrl3;
+
+	/*
+	 * DRAM size information
+	 * Specifies the value for EMC_ADR_CFG
+	 */
+	u32 emc_adr_cfg;
+
+	/*
+	 * Specifies the time to wait after asserting pin
+	 * CKE (in microseconds)
+	 */
+	u32 emc_pin_program_wait;
+	/* Specifies the extra delay before/after pin RESET/CKE command */
+	u32 emc_pin_extra_wait;
+
+	u32 emc_pin_gpio_enable;
+	u32 emc_pin_gpio;
+
+	/*
+	 * Specifies the extra delay after the first writing
+	 * of EMC_TIMING_CONTROL
+	 */
+	u32 emc_timing_control_wait;
+
+	/* Timing parameters required for the SDRAM */
+
+	/* Specifies the value for EMC_RC */
+	u32 emc_rc;
+	/* Specifies the value for EMC_RFC */
+	u32 emc_rfc;
+
+	u32 emc_rfc_pb;
+	u32 emc_ref_ctrl2;
+
+	/* Specifies the value for EMC_RFC_SLR */
+	u32 emc_rfc_slr;
+	/* Specifies the value for EMC_RAS */
+	u32 emc_ras;
+	/* Specifies the value for EMC_RP */
+	u32 emc_rp;
+	/* Specifies the value for EMC_R2R */
+	u32 emc_r2r;
+	/* Specifies the value for EMC_W2W */
+	u32 emc_w2w;
+	/* Specifies the value for EMC_R2W */
+	u32 emc_r2w;
+	/* Specifies the value for EMC_W2R */
+	u32 emc_w2r;
+	/* Specifies the value for EMC_R2P */
+	u32 emc_r2p;
+	/* Specifies the value for EMC_W2P */
+	u32 emc_w2p;
+	/* Specifies the value for EMC_RD_RCD */
+
+	u32 emc_tppd;
+	u32 emc_trtm;
+	u32 emc_twtm;
+	u32 emc_tratm;
+	u32 emc_twatm;
+	u32 emc_tr2ref;
+	u32 emc_ccdmw;
+
+	u32 emc_rd_rcd;
+	/* Specifies the value for EMC_WR_RCD */
+	u32 emc_wr_rcd;
+	/* Specifies the value for EMC_RRD */
+	u32 emc_rrd;
+	/* Specifies the value for EMC_REXT */
+	u32 emc_rext;
+	/* Specifies the value for EMC_WEXT */
+	u32 emc_wext;
+	/* Specifies the value for EMC_WDV */
+	u32 emc_wdv;
+
+	u32 emc_wdv_chk;
+	u32 emc_wsv;
+	u32 emc_wev;
+
+	/* Specifies the value for EMC_WDV_MASK */
+	u32 emc_wdv_mask;
+
+	u32 emc_ws_duration;
+	u32 emc_we_duration;
+
+	/* Specifies the value for EMC_QUSE */
+	u32 emc_quse;
+	/* Specifies the value for EMC_QUSE_WIDTH */
+	u32 emc_quse_width;
+	/* Specifies the value for EMC_IBDLY */
+	u32 emc_ibdly;
+
+	u32 emc_obdly;
+
+	/* Specifies the value for EMC_EINPUT */
+	u32 emc_einput;
+	/* Specifies the value for EMC_EINPUT_DURATION */
+	u32 emc_einput_duration;
+	/* Specifies the value for EMC_PUTERM_EXTRA */
+	u32 emc_puterm_extra;
+	/* Specifies the value for EMC_PUTERM_WIDTH */
+	u32 emc_puterm_width;
+
+	u32 emc_qrst;
+	u32 emc_qsafe;
+	u32 emc_rdv;
+	u32 emc_rdv_mask;
+
+	u32 emc_rdv_early;
+	u32 emc_rdv_early_mask;
+
+	/* Specifies the value for EMC_QPOP */
+	u32 emc_qpop;
+
+	/* Specifies the value for EMC_REFRESH */
+	u32 emc_refresh;
+	/* Specifies the value for EMC_BURST_REFRESH_NUM */
+	u32 emc_burst_refresh_num;
+	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
+	u32 emc_prerefresh_req_cnt;
+	/* Specifies the value for EMC_PDEX2WR */
+	u32 emc_pdex2wr;
+	/* Specifies the value for EMC_PDEX2RD */
+	u32 emc_pdex2rd;
+	/* Specifies the value for EMC_PCHG2PDEN */
+	u32 emc_pchg2pden;
+	/* Specifies the value for EMC_ACT2PDEN */
+	u32 emc_act2pden;
+	/* Specifies the value for EMC_AR2PDEN */
+	u32 emc_ar2pden;
+	/* Specifies the value for EMC_RW2PDEN */
+	u32 emc_rw2pden;
+
+	u32 emc_cke2pden;
+	u32 emc_pdex2che;
+	u32 emc_pdex2mrr;
+
+	/* Specifies the value for EMC_TXSR */
+	u32 emc_txsr;
+	/* Specifies the value for EMC_TXSRDLL */
+	u32 emc_txsr_dll;
+	/* Specifies the value for EMC_TCKE */
+	u32 emc_tcke;
+	/* Specifies the value for EMC_TCKESR */
+	u32 emc_tckesr;
+	/* Specifies the value for EMC_TPD */
+	u32 emc_tpd;
+	/* Specifies the value for EMC_TFAW */
+	u32 emc_tfaw;
+	/* Specifies the value for EMC_TRPAB */
+	u32 emc_trpab;
+	/* Specifies the value for EMC_TCLKSTABLE */
+	u32 emc_tclkstable;
+	/* Specifies the value for EMC_TCLKSTOP */
+	u32 emc_tclkstop;
+	/* Specifies the value for EMC_TREFBW */
+	u32 emc_trefbw;
+
+	/* FBIO configuration values */
+
+	/* Specifies the value for EMC_FBIO_CFG5 */
+	u32 emc_fbio_cfg5;
+	/* Specifies the value for EMC_FBIO_CFG7 */
+	u32 emc_fbio_cfg7;
+	u32 emc_fbio_cfg8;
+
+	/* Command mapping for CMD brick 0 */
+	u32 emc_cmd_mapping_cmd0_0;
+	u32 emc_cmd_mapping_cmd0_1;
+	u32 emc_cmd_mapping_cmd0_2;
+	u32 emc_cmd_mapping_cmd1_0;
+	u32 emc_cmd_mapping_cmd1_1;
+	u32 emc_cmd_mapping_cmd1_2;
+	u32 emc_cmd_mapping_cmd2_0;
+	u32 emc_cmd_mapping_cmd2_1;
+	u32 emc_cmd_mapping_cmd2_2;
+	u32 emc_cmd_mapping_cmd3_0;
+	u32 emc_cmd_mapping_cmd3_1;
+	u32 emc_cmd_mapping_cmd3_2;
+	u32 emc_cmd_mapping_byte;
+
+	/* Specifies the value for EMC_FBIO_SPARE */
+	u32 emc_fbio_spare;
+
+	/* Specifies the value for EMC_CFG_RSV */
+	u32 emc_cfg_rsv;
+
+	/* MRS command values */
+
+	/* Specifies the value for EMC_MRS */
+	u32 emc_mrs;
+	/* Specifies the MP0 command to initialize mode registers */
+	u32 emc_emrs;
+	/* Specifies the MP2 command to initialize mode registers */
+	u32 emc_emrs2;
+	/* Specifies the MP3 command to initialize mode registers */
+	u32 emc_emrs3;
+	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
+	u32 emc_mrw1;
+	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
+	u32 emc_mrw2;
+	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
+	u32 emc_mrw3;
+	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
+	u32 emc_mrw4;
+
+	/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
+	u32 emc_mrw6;
+	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
+	u32 emc_mrw8;
+	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
+	u32 emc_mrw9;
+	/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
+	u32 emc_mrw10;
+	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
+	u32 emc_mrw12;
+	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
+	u32 emc_mrw13;
+	/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
+	u32 emc_mrw14;
+
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at cold boot
+	 */
+	u32 emc_mrw_extra;
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at warm boot
+	 */
+	u32 emc_warm_boot_mrw_extra;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * warm boot
+	 */
+	u32 emc_warm_boot_extramode_reg_write_enable;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * cold boot
+	 */
+	u32 emc_extramode_reg_write_enable;
+
+	/* Specifies the EMC_MRW reset command value */
+	u32 emc_mrw_reset_command;
+	/* Specifies the EMC Reset wait time (in microseconds) */
+	u32 emc_mrw_reset_ninit_wait;
+	/* Specifies the value for EMC_MRS_WAIT_CNT */
+	u32 emc_mrs_wait_cnt;
+	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
+	u32 emc_mrs_wait_cnt2;
+
+	/* EMC miscellaneous configurations */
+
+	/* Specifies the value for EMC_CFG */
+	u32 emc_cfg;
+	/* Specifies the value for EMC_CFG_2 */
+	u32 emc_cfg2;
+	/* Specifies the pipe bypass controls */
+	u32 emc_cfg_pipe;
+
+	u32 emc_cfg_pipe_clk;
+	u32 emc_fdpd_ctrl_cmd_no_ramp;
+	u32 emc_cfg_update;
+
+	/* Specifies the value for EMC_DBG */
+	u32 emc_dbg;
+
+	u32 emc_dbg_write_mux;
+
+	/* Specifies the value for EMC_CMDQ */
+	u32 emc_cmd_q;
+	/* Specifies the value for EMC_MC2EMCQ */
+	u32 emc_mc2emc_q;
+	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
+	u32 emc_dyn_self_ref_control;
+
+	/* Specifies the value for MEM_INIT_DONE */
+	u32 ahb_arbitration_xbar_ctrl_meminit_done;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL */
+	u32 emc_cfg_dig_dll;
+	u32 emc_cfg_dig_dll_1;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
+	u32 emc_cfg_dig_dll_period;
+	/* Specifies the value of *DEV_SELECTN of various EMC registers */
+	u32 emc_dev_select;
+
+	/* Specifies the value for EMC_SEL_DPD_CTRL */
+	u32 emc_sel_dpd_ctrl;
+
+	/* Pads trimmer delays */
+	u32 emc_fdpd_ctrl_dq;
+	u32 emc_fdpd_ctrl_cmd;
+	u32 emc_pmacro_ib_vref_dq_0;
+	u32 emc_pmacro_ib_vref_dq_1;
+	u32 emc_pmacro_ib_vref_dqs_0;
+	u32 emc_pmacro_ib_vref_dqs_1;
+	u32 emc_pmacro_ib_rxrt;
+	u32 emc_cfg_pipe1;
+	u32 emc_cfg_pipe2;
+
+	/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
+	u32 emc_pmacro_quse_ddll_rank0_0;
+	u32 emc_pmacro_quse_ddll_rank0_1;
+	u32 emc_pmacro_quse_ddll_rank0_2;
+	u32 emc_pmacro_quse_ddll_rank0_3;
+	u32 emc_pmacro_quse_ddll_rank0_4;
+	u32 emc_pmacro_quse_ddll_rank0_5;
+	u32 emc_pmacro_quse_ddll_rank1_0;
+	u32 emc_pmacro_quse_ddll_rank1_1;
+	u32 emc_pmacro_quse_ddll_rank1_2;
+	u32 emc_pmacro_quse_ddll_rank1_3;
+	u32 emc_pmacro_quse_ddll_rank1_4;
+	u32 emc_pmacro_quse_ddll_rank1_5;
+
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
+
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
+
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
+
+	u32 emc_pmacro_ddll_long_cmd_0;
+	u32 emc_pmacro_ddll_long_cmd_1;
+	u32 emc_pmacro_ddll_long_cmd_2;
+	u32 emc_pmacro_ddll_long_cmd_3;
+	u32 emc_pmacro_ddll_long_cmd_4;
+	u32 emc_pmacro_ddll_short_cmd_0;
+	u32 emc_pmacro_ddll_short_cmd_1;
+	u32 emc_pmacro_ddll_short_cmd_2;
+
+	u32 emc_pmacro_ddll_periodic_offset;
+
+	/*
+	 * Specifies the delay after asserting CKE pin during a WarmBoot0
+	 * sequence (in microseconds)
+	 */
+	u32 warm_boot_wait;
+
+	/* Specifies the value for EMC_ODT_WRITE */
+	u32 emc_odt_write;
+
+	/* Periodic ZQ calibration */
+
+	/*
+	 * Specifies the value for EMC_ZCAL_INTERVAL
+	 * Value 0 disables ZQ calibration
+	 */
+	u32 emc_zcal_interval;
+	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
+	u32 emc_zcal_wait_cnt;
+	/* Specifies the value for EMC_ZCAL_MRW_CMD */
+	u32 emc_zcal_mrw_cmd;
+
+	/* DRAM initialization sequence flow control */
+
+	/* Specifies the MRS command value for resetting DLL */
+	u32 emc_mrs_reset_dll;
+	/* Specifies the command for ZQ initialization of device 0 */
+	u32 emc_zcal_init_dev0;
+	/* Specifies the command for ZQ initialization of device 1 */
+	u32 emc_zcal_init_dev1;
+	/*
+	 * Specifies the wait time after programming a ZQ initialization
+	 * command (in microseconds)
+	 */
+	u32 emc_zcal_init_wait;
+	/*
+	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
+	 * and warm boot [bit 1]
+	 */
+	u32 emc_zcal_warm_cold_boot_enables;
+
+	/*
+	 * Specifies the MRW command to LPDDR2 for ZQ calibration
+	 * on warmboot
+	 */
+	/* Is issued to both devices separately */
+	u32 emc_mrw_lpddr2zcal_warm_boot;
+	/*
+	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
+	 * Is issued to both devices separately
+	 */
+	u32 emc_zqcal_ddr3_warm_boot;
+
+	u32 emc_zqcal_lpddr4_warm_boot;
+
+	/*
+	 * Specifies the wait time for ZQ calibration on warmboot
+	 * (in microseconds)
+	 */
+	u32 emc_zcal_warm_boot_wait;
+	/*
+	 * Specifies the enable for DRAM Mode Register programming
+	 * at warm boot
+	 */
+	u32 emc_mrs_warm_boot_enable;
+	/*
+	 * Specifies the wait time after sending an MRS DLL reset command
+	 * in microseconds)
+	 */
+	u32 emc_mrs_reset_dll_wait;
+	/* Specifies the extra MRS command to initialize mode registers */
+	u32 emc_mrs_extra;
+	/* Specifies the extra MRS command at warm boot */
+	u32 emc_warm_boot_mrs_extra;
+	/* Specifies the EMRS command to enable the DDR2 DLL */
+	u32 emc_emrs_ddr2_dll_enable;
+	/* Specifies the MRS command to reset the DDR2 DLL */
+	u32 emc_mrs_ddr2_dll_reset;
+	/* Specifies the EMRS command to set OCD calibration */
+	u32 emc_emrs_ddr2_ocd_calib;
+	/*
+	 * Specifies the wait between initializing DDR and setting OCD
+	 * calibration (in microseconds)
+	 */
+	u32 emc_ddr2_wait;
+	/* Specifies the value for EMC_CLKEN_OVERRIDE */
+	u32 emc_clken_override;
+	/*
+	 * Specifies LOG2 of the extra refresh numbers after booting
+	 * Program 0 to disable
+	 */
+	u32 emc_extra_refresh_num;
+	/* Specifies the master override for all EMC clocks */
+	u32 emc_clken_override_allwarm_boot;
+	/* Specifies the master override for all MC clocks */
+	u32 mc_clken_override_allwarm_boot;
+	/* Specifies digital dll period, choosing between 4 to 64 ms */
+	u32 emc_cfg_dig_dll_period_warm_boot;
+
+	/* Pad controls */
+
+	/* Specifies the value for PMC_VDDP_SEL */
+	u32 pmc_vddp_sel;
+	/* Specifies the wait time after programming PMC_VDDP_SEL */
+	u32 pmc_vddp_sel_wait;
+	/* Specifies the value for PMC_DDR_CFG */
+	u32 pmc_ddr_cfg;
+	/* Specifies the value for PMC_IO_DPD3_REQ */
+	u32 pmc_io_dpd3_req;
+	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
+	u32 pmc_io_dpd3_req_wait;
+
+	u32 pmc_io_dpd4_req_wait;
+
+	/* Specifies the value for PMC_REG_SHORT */
+	u32 pmc_reg_short;
+	/* Specifies the value for PMC_NO_IOPOWER */
+	u32 pmc_no_io_power;
+
+	u32 pmc_ddr_ctrl_wait;
+	u32 pmc_ddr_ctrl;
+
+	/* Specifies the value for EMC_ACPD_CONTROL */
+	u32 emc_acpd_control;
+
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
+	u32 emc_swizzle_rank0_byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
+	u32 emc_swizzle_rank0_byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
+	u32 emc_swizzle_rank0_byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
+	u32 emc_swizzle_rank0_byte3;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
+	u32 emc_swizzle_rank1_byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
+	u32 emc_swizzle_rank1_byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
+	u32 emc_swizzle_rank1_byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
+	u32 emc_swizzle_rank1_byte3;
+
+	/* Specifies the value for EMC_TXDSRVTTGEN */
+	u32 emc_txdsrvttgen;
+
+	/* Specifies the value for EMC_DATA_BRLSHFT_0 */
+	u32 emc_data_brlshft0;
+	u32 emc_data_brlshft1;
+
+	u32 emc_dqs_brlshft0;
+	u32 emc_dqs_brlshft1;
+
+	u32 emc_cmd_brlshft0;
+	u32 emc_cmd_brlshft1;
+	u32 emc_cmd_brlshft2;
+	u32 emc_cmd_brlshft3;
+
+	u32 emc_quse_brlshft0;
+	u32 emc_quse_brlshft1;
+	u32 emc_quse_brlshft2;
+	u32 emc_quse_brlshft3;
+
+	u32 emc_dll_cfg0;
+	u32 emc_dll_cfg1;
+
+	u32 emc_pmc_scratch1;
+	u32 emc_pmc_scratch2;
+	u32 emc_pmc_scratch3;
+
+	u32 emc_pmacro_pad_cfg_ctrl;
+
+	u32 emc_pmacro_vttgen_ctrl0;
+	u32 emc_pmacro_vttgen_ctrl1;
+	u32 emc_pmacro_vttgen_ctrl2;
+	u32 emc_pmacro_dsr_vttgen_ctrl0;
+	u32 emc_pmacro_brick_ctrl_rfu1;
+	u32 emc_pmacro_cmd_brick_ctrl_fdpd;
+	u32 emc_pmacro_brick_ctrl_rfu2;
+	u32 emc_pmacro_data_brick_ctrl_fdpd;
+	u32 emc_pmacro_bg_bias_ctrl0;
+	u32 emc_pmacro_data_pad_rx_ctrl;
+	u32 emc_pmacro_cmd_pad_rx_ctrl;
+	u32 emc_pmacro_data_rx_term_mode;
+	u32 emc_pmacro_cmd_rx_term_mode;
+	u32 emc_pmacro_data_pad_tx_ctrl;
+	u32 emc_pmacro_cmd_pad_tx_ctrl;
+	u32 emc_cfg3;
+
+	u32 emc_pmacro_tx_pwrd0;
+	u32 emc_pmacro_tx_pwrd1;
+	u32 emc_pmacro_tx_pwrd2;
+	u32 emc_pmacro_tx_pwrd3;
+	u32 emc_pmacro_tx_pwrd4;
+	u32 emc_pmacro_tx_pwrd5;
+
+	u32 emc_config_sample_delay;
+
+	u32 emc_pmacro_brick_mapping0;
+	u32 emc_pmacro_brick_mapping1;
+	u32 emc_pmacro_brick_mapping2;
+
+	u32 emc_pmacro_tx_sel_clk_src0;
+	u32 emc_pmacro_tx_sel_clk_src1;
+	u32 emc_pmacro_tx_sel_clk_src2;
+	u32 emc_pmacro_tx_sel_clk_src3;
+	u32 emc_pmacro_tx_sel_clk_src4;
+	u32 emc_pmacro_tx_sel_clk_src5;
+
+	u32 emc_pmacro_perbit_fgcg_ctrl0;
+	u32 emc_pmacro_perbit_fgcg_ctrl1;
+	u32 emc_pmacro_perbit_fgcg_ctrl2;
+	u32 emc_pmacro_perbit_fgcg_ctrl3;
+	u32 emc_pmacro_perbit_fgcg_ctrl4;
+	u32 emc_pmacro_perbit_fgcg_ctrl5;
+	u32 emc_pmacro_perbit_rfu_ctrl0;
+	u32 emc_pmacro_perbit_rfu_ctrl1;
+	u32 emc_pmacro_perbit_rfu_ctrl2;
+	u32 emc_pmacro_perbit_rfu_ctrl3;
+	u32 emc_pmacro_perbit_rfu_ctrl4;
+	u32 emc_pmacro_perbit_rfu_ctrl5;
+	u32 emc_pmacro_perbit_rfu1_ctrl0;
+	u32 emc_pmacro_perbit_rfu1_ctrl1;
+	u32 emc_pmacro_perbit_rfu1_ctrl2;
+	u32 emc_pmacro_perbit_rfu1_ctrl3;
+	u32 emc_pmacro_perbit_rfu1_ctrl4;
+	u32 emc_pmacro_perbit_rfu1_ctrl5;
+
+	u32 emc_pmacro_data_pi_ctrl;
+	u32 emc_pmacro_cmd_pi_ctrl;
+
+	u32 emc_pmacro_ddll_bypass;
+
+	u32 emc_pmacro_ddll_pwrd0;
+	u32 emc_pmacro_ddll_pwrd1;
+	u32 emc_pmacro_ddll_pwrd2;
+
+	u32 emc_pmacro_cmd_ctrl0;
+	u32 emc_pmacro_cmd_ctrl1;
+	u32 emc_pmacro_cmd_ctrl2;
+
+	/* DRAM size information */
+
+	/* Specifies the value for MC_EMEM_ADR_CFG */
+	u32 mc_emem_adr_cfg;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
+	u32 mc_emem_adr_cfg_dev0;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
+	u32 mc_emem_adr_cfg_dev1;
+
+	u32 mc_emem_adr_cfg_channel_mask;
+
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
+	u32 mc_emem_adr_cfg_bank_mask0;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
+	u32 mc_emem_adr_cfg_bank_mask1;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
+	u32 mc_emem_adr_cfg_bank_mask2;
+
+	/*
+	 * Specifies the value for MC_EMEM_CFG which holds the external memory
+	 * size (in KBytes)
+	 */
+	u32 mc_emem_cfg;
+
+	/* MC arbitration configuration */
+
+	/* Specifies the value for MC_EMEM_ARB_CFG */
+	u32 mc_emem_arb_cfg;
+	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
+	u32 mc_emem_arb_outstanding_req;
+
+	u32 emc_emem_arb_refpb_hp_ctrl;
+	u32 emc_emem_arb_refpb_bank_ctrl;
+
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
+	u32 mc_emem_arb_timing_rcd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
+	u32 mc_emem_arb_timing_rp;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
+	u32 mc_emem_arb_timing_rc;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
+	u32 mc_emem_arb_timing_ras;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
+	u32 mc_emem_arb_timing_faw;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
+	u32 mc_emem_arb_timing_rrd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
+	u32 mc_emem_arb_timing_rap2pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
+	u32 mc_emem_arb_timing_wap2pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
+	u32 mc_emem_arb_timing_r2r;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
+	u32 mc_emem_arb_timing_w2w;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
+	u32 mc_emem_arb_timing_r2w;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
+	u32 mc_emem_arb_timing_w2r;
+
+	u32 mc_emem_arb_timing_rfcpb;
+
+	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
+	u32 mc_emem_arb_da_turns;
+	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
+	u32 mc_emem_arb_da_covers;
+	/* Specifies the value for MC_EMEM_ARB_MISC0 */
+	u32 mc_emem_arb_misc0;
+	/* Specifies the value for MC_EMEM_ARB_MISC1 */
+	u32 mc_emem_arb_misc1;
+	u32 mc_emem_arb_misc2;
+
+	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
+	u32 mc_emem_arb_ring1_throttle;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
+	u32 mc_emem_arb_override;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
+	u32 mc_emem_arb_override1;
+	/* Specifies the value for MC_EMEM_ARB_RSV */
+	u32 mc_emem_arb_rsv;
+
+	u32 mc_da_cfg0;
+	u32 mc_emem_arb_timing_ccdmw;
+
+	/* Specifies the value for MC_CLKEN_OVERRIDE */
+	u32 mc_clken_override;
+
+	/* Specifies the value for MC_STAT_CONTROL */
+	u32 mc_stat_control;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
+	u32 mc_video_protect_bom;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
+	u32 mc_video_protect_bom_adr_hi;
+	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
+	u32 mc_video_protect_size_mb;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
+	u32 mc_video_protect_vpr_override;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
+	u32 mc_video_protect_vpr_override1;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
+	u32 mc_video_protect_gpu_override0;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
+	u32 mc_video_protect_gpu_override1;
+	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
+	u32 mc_sec_carveout_bom;
+	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
+	u32 mc_sec_carveout_adr_hi;
+	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
+	u32 mc_sec_carveout_size_mb;
+	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
+	u32 mc_video_protect_write_access;
+	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
+	u32 mc_sec_carveout_protect_write_access;
+
+	u32 mc_generalized_carveout1_bom;
+	u32 mc_generalized_carveout1_bom_hi;
+	u32 mc_generalized_carveout1_size_128kb;
+	u32 mc_generalized_carveout1_access0;
+	u32 mc_generalized_carveout1_access1;
+	u32 mc_generalized_carveout1_access2;
+	u32 mc_generalized_carveout1_access3;
+	u32 mc_generalized_carveout1_access4;
+	u32 mc_generalized_carveout1_force_internal_access0;
+	u32 mc_generalized_carveout1_force_internal_access1;
+	u32 mc_generalized_carveout1_force_internal_access2;
+	u32 mc_generalized_carveout1_force_internal_access3;
+	u32 mc_generalized_carveout1_force_internal_access4;
+	u32 mc_generalized_carveout1_cfg0;
+
+	u32 mc_generalized_carveout2_bom;
+	u32 mc_generalized_carveout2_bom_hi;
+	u32 mc_generalized_carveout2_size_128kb;
+	u32 mc_generalized_carveout2_access0;
+	u32 mc_generalized_carveout2_access1;
+	u32 mc_generalized_carveout2_access2;
+	u32 mc_generalized_carveout2_access3;
+	u32 mc_generalized_carveout2_access4;
+	u32 mc_generalized_carveout2_force_internal_access0;
+	u32 mc_generalized_carveout2_force_internal_access1;
+	u32 mc_generalized_carveout2_force_internal_access2;
+	u32 mc_generalized_carveout2_force_internal_access3;
+	u32 mc_generalized_carveout2_force_internal_access4;
+	u32 mc_generalized_carveout2_cfg0;
+
+	u32 mc_generalized_carveout3_bom;
+	u32 mc_generalized_carveout3_bom_hi;
+	u32 mc_generalized_carveout3_size_128kb;
+	u32 mc_generalized_carveout3_access0;
+	u32 mc_generalized_carveout3_access1;
+	u32 mc_generalized_carveout3_access2;
+	u32 mc_generalized_carveout3_access3;
+	u32 mc_generalized_carveout3_access4;
+	u32 mc_generalized_carveout3_force_internal_access0;
+	u32 mc_generalized_carveout3_force_internal_access1;
+	u32 mc_generalized_carveout3_force_internal_access2;
+	u32 mc_generalized_carveout3_force_internal_access3;
+	u32 mc_generalized_carveout3_force_internal_access4;
+	u32 mc_generalized_carveout3_cfg0;
+
+	u32 mc_generalized_carveout4_bom;
+	u32 mc_generalized_carveout4_bom_hi;
+	u32 mc_generalized_carveout4_size_128kb;
+	u32 mc_generalized_carveout4_access0;
+	u32 mc_generalized_carveout4_access1;
+	u32 mc_generalized_carveout4_access2;
+	u32 mc_generalized_carveout4_access3;
+	u32 mc_generalized_carveout4_access4;
+	u32 mc_generalized_carveout4_force_internal_access0;
+	u32 mc_generalized_carveout4_force_internal_access1;
+	u32 mc_generalized_carveout4_force_internal_access2;
+	u32 mc_generalized_carveout4_force_internal_access3;
+	u32 mc_generalized_carveout4_force_internal_access4;
+	u32 mc_generalized_carveout4_cfg0;
+
+	u32 mc_generalized_carveout5_bom;
+	u32 mc_generalized_carveout5_bom_hi;
+	u32 mc_generalized_carveout5_size_128kb;
+	u32 mc_generalized_carveout5_access0;
+	u32 mc_generalized_carveout5_access1;
+	u32 mc_generalized_carveout5_access2;
+	u32 mc_generalized_carveout5_access3;
+	u32 mc_generalized_carveout5_access4;
+	u32 mc_generalized_carveout5_force_internal_access0;
+	u32 mc_generalized_carveout5_force_internal_access1;
+	u32 mc_generalized_carveout5_force_internal_access2;
+	u32 mc_generalized_carveout5_force_internal_access3;
+	u32 mc_generalized_carveout5_force_internal_access4;
+	u32 mc_generalized_carveout5_cfg0;
+
+	/* Specifies enable for CA training */
+	u32 emc_ca_training_enable;
+	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
+	u32 swizzle_rank_byte_encode;
+	/* Specifies enable and offset for patched boot rom write */
+	u32 boot_rom_patch_control;
+	/* Specifies data for patched boot rom write */
+	u32 boot_rom_patch_data;
+
+	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
+	u32 mc_mts_carveout_bom;
+	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
+	u32 mc_mts_carveout_adr_hi;
+	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
+	u32 mc_mts_carveout_size_mb;
+	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
+	u32 mc_mts_carveout_reg_ctrl;
+
+	/* Specifies the clients that are allowed to access untranslated memory */
+	u32 mc_untranslated_region_check;
+
+	/* Just a place holder for special usage when there is no BCT for certain registers */
+	u32 bct_na;
+} sdram_params_t210b01_t;
+
+#endif

bdk/mem/smmu.c

@@ -48,8 +48,8 @@ u8 smmu_payload[] __attribute__((aligned(16))) = {
 void *page_alloc(u32 num)
 {
 	u8 *res = _pageheap;
-	_pageheap += 0x1000 * num;
+	_pageheap += SZ_PAGE * num;
-	memset(res, 0, 0x1000 * num);
+	memset(res, 0, SZ_PAGE * num);
 	return res;
 }
 
@@ -150,8 +150,8 @@ void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
 	{
 		u32 *pte = smmu_get_pte(pdir, addr);
 		*pte = SMMU_ADDR_TO_PFN(page) | attr;
-		addr += 0x1000;
+		addr += SZ_PAGE;
-		page += 0x1000;
+		page += SZ_PAGE;
 	}
 	smmu_flush_all();
 }

bdk/memory_map.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -19,50 +19,67 @@
 
 //#define IPL_STACK_TOP  0x4003FF00
 /* --- BIT/BCT: 0x40000000 - 0x40003000 --- */
-/* ---     IPL: 0x40003000 - 0x40028000 --- */
+/* ---     IPL: 0x40008000 - 0x40028000 --- */
-#define IPL_LOAD_ADDR     0x40003000
+#define LDR_LOAD_ADDR     0x40007000
-#define  IPL_SZ_MAX          0x20000 // 128KB.
+
-//#define IRAM_LIB_ADDR     0x4002B000
+#define IPL_LOAD_ADDR     0x40008000
+#define  IPL_SZ_MAX          SZ_128K
+
+/* --- XUSB EP context and TRB ring buffers --- */
+#define XUSB_RING_ADDR    0x40020000
+
+#define SECMON_MIN_START  0x4002B000
+
 #define SDRAM_PARAMS_ADDR 0x40030000 // SDRAM extraction buffer during sdram init.
 #define CBFS_DRAM_EN_ADDR 0x4003e000 // u32.
 
 /* --- DRAM START --- */
 #define DRAM_START     0x80000000
-#define  HOS_RSVD       0x1000000 // Do not write anything in this area.
+#define  HOS_RSVD          SZ_16M // Do not write anything in this area.
 
 #define NYX_LOAD_ADDR  0x81000000
-#define  NYX_SZ_MAX     0x1000000 // 16MB
+#define  NYX_SZ_MAX        SZ_16M
 /* --- Gap: 0x82000000 - 0x82FFFFFF --- */
 
 /* Stack theoretical max: 33MB */
 #define IPL_STACK_TOP  0x83100000
 #define IPL_HEAP_START 0x84000000
-#define  IPL_HEAP_SZ   0x20000000 // 512MB.
+#define  IPL_HEAP_SZ      SZ_512M
 /* --- Gap: 1040MB 0xA4000000 - 0xE4FFFFFF --- */
 
 // Virtual disk / Chainloader buffers.
 #define RAM_DISK_ADDR     0xA4000000
-#define NX_BIS_CACHE_ADDR RAM_DISK_ADDR
 #define  RAM_DISK_SZ      0x41000000 // 1040MB.
+#define  RAM_DISK2_SZ 0x21000000 //  528MB.
+
+// NX BIS driver sector cache.
+#define NX_BIS_CACHE_ADDR  0xC5000000
+#define  NX_BIS_CACHE_SZ   0x10020000 // 256MB.
+#define NX_BIS_LOOKUP_ADDR 0xD6000000
+#define  NX_BIS_LOOKUP_SZ   0xF000000 // 240MB.
+
+// L4T Kernel Panic Storage (PSTORE).
+#define PSTORE_ADDR   0xB0000000
+#define  PSTORE_SZ         SZ_2M
 
 //#define DRAM_LIB_ADDR    0xE0000000
 /* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading.
 
 // SDMMC DMA buffers 1
 #define SDMMC_UPPER_BUFFER 0xE5000000
-#define  SDMMC_UP_BUF_SZ    0x8000000 // 128MB.
+#define  SDMMC_UP_BUF_SZ      SZ_128M
 
 // Nyx buffers.
 #define NYX_STORAGE_ADDR 0xED000000
 #define NYX_RES_ADDR     0xEE000000
-#define  NYX_RES_SZ       0x1000000 // 16MB.
+#define  NYX_RES_SZ          SZ_16M
 
 // SDMMC DMA buffers 2
 #define SDXC_BUF_ALIGNED   0xEF000000
 #define MIXD_BUF_ALIGNED   0xF0000000
 #define TITLEKEY_BUF_ADR   MIXD_BUF_ALIGNED
 #define EMMC_BUF_ALIGNED   MIXD_BUF_ALIGNED
-#define  SDMMC_DMA_BUF_SZ   0x1000000 // 16MB (4MB currently used).
+#define  SDMMC_DMA_BUF_SZ      SZ_16M // 4MB currently used.
 
 // Nyx LvGL buffers.
 #define NYX_LV_VDB_ADR   0xF1000000
@@ -80,22 +97,17 @@
 #define  NYX_FB_SZ         0x384000 // 1280 x 720 x 4.
 
 #define DRAM_MEM_HOLE_ADR 0xF6A00000
-#define NX_BIS_LOOKUP_ADR DRAM_MEM_HOLE_ADR
 #define DRAM_MEM_HOLE_SZ   0x8140000
 /* ---   Hole: 129MB 0xF6A00000 - 0xFEB3FFFF --- */
 #define DRAM_START2       0xFEB40000
 
-// NX BIS driver sector cache.
-// #define NX_BIS_CACHE_ADDR 0xFEE00000
-// #define  NX_BIS_CACHE_SZ    0x100000
-
 // USB buffers.
 #define USBD_ADDR                 0xFEF00000
 #define USB_DESCRIPTOR_ADDR       0xFEF40000
 #define USB_EP_CONTROL_BUF_ADDR   0xFEF80000
 #define USB_EP_BULK_IN_BUF_ADDR   0xFF000000
 #define USB_EP_BULK_OUT_BUF_ADDR  0xFF800000
-#define  USB_EP_BULK_OUT_MAX_XFER   0x800000
+#define  USB_EP_BULK_OUT_MAX_XFER      SZ_8M
 
 // #define EXT_PAYLOAD_ADDR    0xC0000000
 // #define RCM_PAYLOAD_ADDR    (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))

bdk/module.h

@@ -21,10 +21,13 @@
 #include <stddef.h>
 #include <mem/heap.h>
 
+#define IANOS_EXT0 0x304E4149
+
 // Module Callback
 typedef void (*cbMainModule_t)(const char *s);
 typedef void (*memcpy_t)(void *, void *, size_t);
 typedef void (*memset_t)(void *, int, size_t);
+typedef int  (*reg_voltage_set_t)(u32, u32);
 
 typedef struct _bdkParams_t
 {
@@ -33,6 +36,8 @@ typedef struct _bdkParams_t
 	heap_t *sharedHeap;
 	memcpy_t memcpy;
 	memset_t memset;
+	u32 extension_magic;
+	reg_voltage_set_t reg_voltage_set;
 } *bdkParams_t;
 
 // Module Entrypoint

bdk/power/bm92t36.c

@@ -0,0 +1,99 @@
+/*
+ * USB-PD driver for Nintendo Switch's TI BM92T36
+ *
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "bm92t36.h"
+#include <soc/i2c.h>
+#include <utils/util.h>
+
+#define ALERT_STATUS_REG    0x2
+#define STATUS1_REG         0x3
+#define STATUS2_REG         0x4
+#define COMMAND_REG         0x5
+#define CONFIG1_REG         0x6
+#define DEV_CAPS_REG        0x7
+#define READ_PDOS_SRC_REG   0x8
+#define CONFIG2_REG         0x17
+#define DP_STATUS_REG       0x18
+#define DP_ALERT_EN_REG     0x19
+#define VENDOR_CONFIG_REG   0x1A
+#define AUTO_NGT_FIXED_REG  0x20
+#define AUTO_NGT_BATT_REG   0x23
+#define SYS_CONFIG1_REG     0x26
+#define SYS_CONFIG2_REG     0x27
+#define CURRENT_PDO_REG     0x28
+#define CURRENT_RDO_REG     0x2B
+#define ALERT_ENABLE_REG    0x2E
+#define SYS_CONFIG3_REG     0x2F
+#define SET_RDO_REG         0x30
+#define PDOS_SNK_REG        0x33
+#define PDOS_SRC_PROV_REG   0x3C
+#define FW_TYPE_REG         0x4B
+#define FW_REVISION_REG     0x4C
+#define MAN_ID_REG          0x4D
+#define DEV_ID_REG          0x4E
+#define REV_ID_REG          0x4F
+#define INCOMING_VDM_REG    0x50
+#define OUTGOING_VDM_REG    0x60
+
+#define STATUS1_INSERT      BIT(7)  // Cable inserted.
+
+typedef struct _pd_object_t {
+	unsigned int amp:10;
+	unsigned int volt:10;
+	unsigned int info:10;
+	unsigned int type:2;
+} __attribute__((packed)) pd_object_t;
+
+static int _bm92t36_read_reg(u8 *buf, u32 size, u32 reg)
+{
+	return i2c_recv_buf_big(buf, size, I2C_1, BM92T36_I2C_ADDR, reg);
+}
+
+void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd)
+{
+	u8 buf[32];
+	pd_object_t pdos[7];
+
+	if (inserted)
+	{
+		_bm92t36_read_reg(buf, 2, STATUS1_REG);
+		*inserted = buf[0] & STATUS1_INSERT ? true : false;
+	}
+
+	if (usb_pd)
+	{
+		_bm92t36_read_reg(buf, 29, READ_PDOS_SRC_REG);
+		memcpy(pdos, &buf[1], 28);
+
+		memset(usb_pd, 0, sizeof(usb_pd_objects_t));
+		usb_pd->pdo_no = buf[0] / sizeof(pd_object_t);
+
+		for (u32 i = 0; i < usb_pd->pdo_no; i++)
+		{
+			usb_pd->pdos[i].amperage = pdos[i].amp * 10;
+			usb_pd->pdos[i].voltage = (pdos[i].volt * 50) / 1000;
+		}
+
+		_bm92t36_read_reg(buf, 5, CURRENT_PDO_REG);
+		memcpy(pdos, &buf[1], 4);
+		usb_pd->selected_pdo.amperage = pdos[0].amp * 10;
+		usb_pd->selected_pdo.voltage = (pdos[0].volt * 50) / 1000;
+	}
+}

bdk/power/bm92t36.h

@@ -1,5 +1,7 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * USB-PD driver for Nintendo Switch's TI BM92T36
+ *
+ * Copyright (c) 2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,21 +16,26 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef _FSS_H_
+#ifndef __BM92T36_H_
-#define _FSS_H_
+#define __BM92T36_H_
 
-#include "hos.h"
+#include <utils/types.h>
 
-typedef struct _fss0_sept_t
+#define BM92T36_I2C_ADDR 0x18
+
+typedef struct _usb_pd_object_t
 {
-	u32 kb;
+	u32 amperage;
-	ini_sec_t *cfg_sec;
+	u32 voltage;
-	void *sept_primary;
+} usb_pd_object_t;
-	void *sept_secondary;
 
-} fss0_sept_t;
+typedef struct _usb_pd_objects_t
+{
+	u32 pdo_no;
+	usb_pd_object_t pdos[7];
+	usb_pd_object_t selected_pdo;
+} usb_pd_objects_t;
 
-int parse_fss(launch_ctxt_t *ctxt, const char *path, fss0_sept_t *sept_ctxt);
+void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd);
-int load_sept_from_ffs0(fss0_sept_t *sept_ctxt);
 
 #endif

bdk/power/max17050.c

@@ -26,17 +26,19 @@
 #include <soc/i2c.h>
 #include <utils/util.h>
 
+#define BASE_SNS_UOHM 5000
+
 /* Status register bits */
-#define STATUS_POR_BIT (1 << 1)
+#define STATUS_POR_BIT BIT(1)
-#define STATUS_BST_BIT (1 << 3)
+#define STATUS_BST_BIT BIT(3)
-#define STATUS_VMN_BIT (1 << 8)
+#define STATUS_VMN_BIT BIT(8)
-#define STATUS_TMN_BIT (1 << 9)
+#define STATUS_TMN_BIT BIT(9)
-#define STATUS_SMN_BIT (1 << 10)
+#define STATUS_SMN_BIT BIT(10)
-#define STATUS_BI_BIT  (1 << 11)
+#define STATUS_BI_BIT  BIT(11)
-#define STATUS_VMX_BIT (1 << 12)
+#define STATUS_VMX_BIT BIT(12)
-#define STATUS_TMX_BIT (1 << 13)
+#define STATUS_TMX_BIT BIT(13)
-#define STATUS_SMX_BIT (1 << 14)
+#define STATUS_SMX_BIT BIT(14)
-#define STATUS_BR_BIT  (1 << 15)
+#define STATUS_BR_BIT  BIT(15)
 
 #define VFSOC0_LOCK   0x0000
 #define VFSOC0_UNLOCK 0x0080
@@ -85,31 +87,31 @@ int max17050_get_property(enum MAX17050_reg reg, int *value)
 		break;
 	case MAX17050_VCELL: // Voltage now.
 		data = max17050_get_reg(MAX17050_VCELL);
-		*value = data * 625 / 8 / 1000;
+		*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
 		battery_voltage = *value;
 		break;
 	case MAX17050_AvgVCELL: // Voltage avg.
 		data = max17050_get_reg(MAX17050_AvgVCELL);
-		*value = data * 625 / 8 / 1000;
+		*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
 		break;
 	case MAX17050_OCVInternal: // Voltage ocv.
 		data = max17050_get_reg(MAX17050_OCVInternal);
-		*value = data * 625 / 8 / 1000;
+		*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
 		break;
 	case MAX17050_RepSOC: // Capacity %.
 		*value = max17050_get_reg(MAX17050_RepSOC);
 		break;
 	case MAX17050_DesignCap: // Charge full design.
 		data = max17050_get_reg(MAX17050_DesignCap);
-		*value = data * 5 / 10;
+		*value = data * (BASE_SNS_UOHM / MAX17050_BOARD_SNS_RESISTOR_UOHM) / MAX17050_BOARD_CGAIN;
 		break;
 	case MAX17050_FullCAP: // Charge full.
 		data = max17050_get_reg(MAX17050_FullCAP);
-		*value = data * 5 / 10;
+		*value = data * (BASE_SNS_UOHM / MAX17050_BOARD_SNS_RESISTOR_UOHM) / MAX17050_BOARD_CGAIN;
 		break;
 	case MAX17050_RepCap: // Charge now.
 		data = max17050_get_reg(MAX17050_RepCap);
-		*value = data * 5 / 10;
+		*value = data * (BASE_SNS_UOHM / MAX17050_BOARD_SNS_RESISTOR_UOHM) / MAX17050_BOARD_CGAIN;
 		break;
 	case MAX17050_TEMP: // Temp.
 		data = max17050_get_reg(MAX17050_TEMP);
@@ -119,12 +121,12 @@ int max17050_get_property(enum MAX17050_reg reg, int *value)
 	case MAX17050_Current: // Current now.
 		data = max17050_get_reg(MAX17050_Current);
 		*value = (s16)data;
-		*value *= 1562500 / MAX17050_DEFAULT_SNS_RESISTOR;
+		*value *= 1562500 / (MAX17050_BOARD_SNS_RESISTOR_UOHM * MAX17050_BOARD_CGAIN);
 		break;
 	case MAX17050_AvgCurrent: // Current avg.
 		data = max17050_get_reg(MAX17050_AvgCurrent);
 		*value = (s16)data;
-		*value *= 1562500 / MAX17050_DEFAULT_SNS_RESISTOR;
+		*value *= 1562500 / (MAX17050_BOARD_SNS_RESISTOR_UOHM * MAX17050_BOARD_CGAIN);
 		break;
 	default:
 		return -1;

bdk/power/max17050.h

@@ -1,6 +1,5 @@
 /*
  * Fuel gauge driver for Nintendo Switch's Maxim 17050
- *  Note that Maxim 8966 and 8997 are mfd and this is its subdevice.
  *
  * Copyright (c) 2011 Samsung Electronics
  * MyungJoo Ham <myungjoo.ham@samsung.com>
@@ -26,8 +25,11 @@
 
 #include <utils/types.h>
 
-#define MAX17050_STATUS_BattAbsent    (1 << 3)
+/* Board default values */
-#define MAX17050_DEFAULT_SNS_RESISTOR 10000
+#define MAX17050_BOARD_CGAIN 2 /* Actual: 1.99993 */
+#define MAX17050_BOARD_SNS_RESISTOR_UOHM 5000 /* 0.005 Ohm */
+
+#define MAX17050_STATUS_BattAbsent BIT(3)
 
 /* Consider RepCap which is less then 10 units below FullCAP full */
 #define MAX17050_FULL_THRESHOLD 10

bdk/power/max77620.h

@@ -1,8 +1,7 @@
 /*
  * Defining registers address and its bit definitions of MAX77620 and MAX20024
  *
- * Copyright (c) 2016 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020 CTCaer
- * Copyright (c) 2019 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,13 +15,7 @@
 
 /* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
 #define MAX77620_REG_CNFGGLBL1      0x00
-#define  MAX77620_CNFGGLBL1_LBDAC_EN          (1 << 7)
+#define  MAX77620_CNFGGLBL1_LBRSTEN           BIT(0)
-#define  MAX77620_CNFGGLBL1_MPPLD             (1 << 6)
-#define  MAX77620_CNFGGLBL1_LBHYST            ((1 << 5) | (1 << 4))
-#define  MAX77620_CNFGGLBL1_LBHYST_100        (0 << 4)
-#define  MAX77620_CNFGGLBL1_LBHYST_200        (1 << 4)
-#define  MAX77620_CNFGGLBL1_LBHYST_300        (2 << 4)
-#define  MAX77620_CNFGGLBL1_LBHYST_400        (3 << 4)
 #define  MAX77620_CNFGGLBL1_LBDAC_MASK        0x0E
 #define  MAX77620_CNFGGLBL1_LBDAC_2700        (0 << 1)
 #define  MAX77620_CNFGGLBL1_LBDAC_2800        (1 << 1)
@@ -32,30 +25,45 @@
 #define  MAX77620_CNFGGLBL1_LBDAC_3200        (5 << 1)
 #define  MAX77620_CNFGGLBL1_LBDAC_3300        (6 << 1)
 #define  MAX77620_CNFGGLBL1_LBDAC_3400        (7 << 1)
-#define  MAX77620_CNFGGLBL1_LBRSTEN           (1 << 0)
+#define  MAX77620_CNFGGLBL1_LBHYST_100        (0 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_200        (1 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_300        (2 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_400        (3 << 4)
+#define  MAX77620_CNFGGLBL1_MPPLD             BIT(6)
+#define  MAX77620_CNFGGLBL1_LBDAC_EN          BIT(7)
 
 #define MAX77620_REG_CNFGGLBL2      0x01
-#define MAX77620_REG_CNFGGLBL3      0x02
-#define  MAX77620_WDTC_MASK                   0x3
-#define  MAX77620_WDTOFFC                     (1 << 4)
-#define  MAX77620_WDTSLPC                     (1 << 3)
-#define  MAX77620_WDTEN                       (1 << 2)
 #define  MAX77620_TWD_MASK                    0x3
 #define  MAX77620_TWD_2s                      0x0
 #define  MAX77620_TWD_16s                     0x1
 #define  MAX77620_TWD_64s                     0x2
 #define  MAX77620_TWD_128s                    0x3
+#define  MAX77620_WDTEN                       BIT(2)
+#define  MAX77620_WDTSLPC                     BIT(3)
+#define  MAX77620_WDTOFFC                     BIT(4)
+#define  MAX77620_GLBL_LPM                    BIT(5)
+#define  MAX77620_I2CTWD_MASK                 0xC0
+#define  MAX77620_I2CTWD_DISABLED             0x00
+#define  MAX77620_I2CTWD_1_33ms               0x40
+#define  MAX77620_I2CTWD_35_7ms               0x80
+#define  MAX77620_I2CTWD_41_7ms               0xC0
+
+#define MAX77620_REG_CNFGGLBL3      0x02
+#define  MAX77620_WDTC_MASK                   0x3
 
 #define MAX77620_REG_CNFG1_32K      0x03
-#define  MAX77620_CNFG1_32K_OUT0_EN           (1 << 2)
+#define  MAX77620_CNFG1_PWR_MD_32K_MASK       0x3
+#define  MAX77620_CNFG1_32K_OUT0_EN           BIT(2)
+#define  MAX77620_CNFG1_32KLOAD_MASK          0x30
+#define  MAX77620_CNFG1_32K_OK                BIT(7)
 
 #define MAX77620_REG_CNFGBBC        0x04
-#define  MAX77620_CNFGBBC_ENABLE              (1 << 0)
+#define  MAX77620_CNFGBBC_ENABLE              BIT(0)
 #define  MAX77620_CNFGBBC_CURRENT_MASK        0x06
 #define  MAX77620_CNFGBBC_CURRENT_SHIFT       1
 #define  MAX77620_CNFGBBC_VOLTAGE_MASK        0x18
 #define  MAX77620_CNFGBBC_VOLTAGE_SHIFT       3
-#define  MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5)
+#define  MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
 #define  MAX77620_CNFGBBC_RESISTOR_MASK       0xC0
 #define  MAX77620_CNFGBBC_RESISTOR_SHIFT      6
 #define  MAX77620_CNFGBBC_RESISTOR_100        (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
@@ -64,37 +72,63 @@
 #define  MAX77620_CNFGBBC_RESISTOR_6K         (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
 
 #define MAX77620_REG_IRQTOP         0x05
-#define  MAX77620_IRQ_TOP_GLBL_MASK           (1 << 7)
+#define MAX77620_REG_IRQTOPM        0x0D
-#define  MAX77620_IRQ_TOP_SD_MASK             (1 << 6)
+#define  MAX77620_IRQ_TOP_ONOFF_MASK          BIT(1)
-#define  MAX77620_IRQ_TOP_LDO_MASK            (1 << 5)
+#define  MAX77620_IRQ_TOP_32K_MASK            BIT(2)
-#define  MAX77620_IRQ_TOP_GPIO_MASK           (1 << 4)
+#define  MAX77620_IRQ_TOP_RTC_MASK            BIT(3)
-#define  MAX77620_IRQ_TOP_RTC_MASK            (1 << 3)
+#define  MAX77620_IRQ_TOP_GPIO_MASK           BIT(4)
-#define  MAX77620_IRQ_TOP_32K_MASK            (1 << 2)
+#define  MAX77620_IRQ_TOP_LDO_MASK            BIT(5)
-#define  MAX77620_IRQ_TOP_ONOFF_MASK          (1 << 1)
+#define  MAX77620_IRQ_TOP_SD_MASK             BIT(6)
+#define  MAX77620_IRQ_TOP_GLBL_MASK           BIT(7)
 
 #define MAX77620_REG_INTLBT         0x06
-#define MAX77620_REG_IRQTOPM        0x0D
+#define MAX77620_REG_INTENLBT       0x0E
-#define  MAX77620_IRQ_LBM_MASK                (1 << 3)
+#define  MAX77620_IRQ_GLBLM_MASK              BIT(0)
-#define  MAX77620_IRQ_TJALRM1_MASK            (1 << 2)
+#define  MAX77620_IRQ_TJALRM2_MASK            BIT(1)
-#define  MAX77620_IRQ_TJALRM2_MASK            (1 << 1)
+#define  MAX77620_IRQ_TJALRM1_MASK            BIT(2)
+#define  MAX77620_IRQ_LBM_MASK                BIT(3)
 
 #define MAX77620_REG_IRQSD          0x07
-#define MAX77620_REG_IRQ_LVL2_L0_7  0x08
-#define MAX77620_REG_IRQ_LVL2_L8    0x09
-#define MAX77620_REG_IRQ_LVL2_GPIO  0x0A
-#define MAX77620_REG_ONOFFIRQ       0x0B
-#define MAX77620_REG_NVERC          0x0C
-
-#define MAX77620_REG_INTENLBT       0x0E
-#define  MAX77620_GLBLM_MASK                  (1 << 0)
-
 #define MAX77620_REG_IRQMASKSD      0x0F
+#define  MAX77620_IRQSD_PFI_SD3               BIT(4)
+#define  MAX77620_IRQSD_PFI_SD2               BIT(5)
+#define  MAX77620_IRQSD_PFI_SD1               BIT(6)
+#define  MAX77620_IRQSD_PFI_SD0               BIT(7)
+
+#define MAX77620_REG_IRQ_LVL2_L0_7  0x08 // LDO number that irq occured.
 #define MAX77620_REG_IRQ_MSK_L0_7   0x10
+#define MAX77620_REG_IRQ_LVL2_L8    0x09 // LDO number that irq occured. Only bit0: LDO8 is valid.
 #define MAX77620_REG_IRQ_MSK_L8     0x11
+#define MAX77620_REG_IRQ_LVL2_GPIO  0x0A // Edge detection interrupt.
+
+#define MAX77620_REG_ONOFFIRQ       0x0B
 #define MAX77620_REG_ONOFFIRQM      0x12
+#define  MAX77620_ONOFFIRQ_MRWRN              BIT(0)
+#define  MAX77620_ONOFFIRQ_EN0_1SEC           BIT(1)
+#define  MAX77620_ONOFFIRQ_EN0_F              BIT(2)
+#define  MAX77620_ONOFFIRQ_EN0_R              BIT(3)
+#define  MAX77620_ONOFFIRQ_LID_F              BIT(4)
+#define  MAX77620_ONOFFIRQ_LID_R              BIT(5)
+#define  MAX77620_ONOFFIRQ_ACOK_F             BIT(6)
+#define  MAX77620_ONOFFIRQ_ACOK_R             BIT(7)
+
+#define MAX77620_REG_NVERC          0x0C // Shutdown reason (non-volatile).
+#define  MAX77620_NVERC_SHDN                  BIT(0)
+#define  MAX77620_NVERC_WTCHDG                BIT(1)
+#define  MAX77620_NVERC_HDRST                 BIT(2)
+#define  MAX77620_NVERC_TOVLD                 BIT(3)
+#define  MAX77620_NVERC_MBLSD                 BIT(4)
+#define  MAX77620_NVERC_MBO                   BIT(5)
+#define  MAX77620_NVERC_MBU                   BIT(6)
+#define  MAX77620_NVERC_RSTIN                 BIT(7)
+
 #define MAX77620_REG_STATLBT        0x13
 #define MAX77620_REG_STATSD         0x14
+
 #define MAX77620_REG_ONOFFSTAT      0x15
+#define  MAX77620_ONOFFSTAT_LID     BIT(0)
+#define  MAX77620_ONOFFSTAT_ACOK    BIT(1)
+#define  MAX77620_ONOFFSTAT_EN0     BIT(2)
 
 /* SD and LDO Registers */
 #define MAX77620_REG_SD0            0x16
@@ -102,18 +136,42 @@
 #define MAX77620_REG_SD2            0x18
 #define MAX77620_REG_SD3            0x19
 #define MAX77620_REG_SD4            0x1A
+#define MAX77620_REG_DVSSD0         0x1B
+#define MAX77620_REG_DVSSD1         0x1C
 #define  MAX77620_SDX_VOLT_MASK               0xFF
 #define  MAX77620_SD0_VOLT_MASK               0x3F
 #define  MAX77620_SD1_VOLT_MASK               0x7F
 #define  MAX77620_LDO_VOLT_MASK               0x3F
-#define MAX77620_REG_DVSSD0         0x1B
+
-#define MAX77620_REG_DVSSD1         0x1C
 #define MAX77620_REG_SD0_CFG        0x1D
 #define MAX77620_REG_SD1_CFG        0x1E
 #define MAX77620_REG_SD2_CFG        0x1F
 #define MAX77620_REG_SD3_CFG        0x20
 #define MAX77620_REG_SD4_CFG        0x21
+#define  MAX77620_SD_SR_MASK                  0xC0
+#define  MAX77620_SD_SR_SHIFT                 6
+#define  MAX77620_SD_POWER_MODE_MASK          0x30
+#define  MAX77620_SD_POWER_MODE_SHIFT         4
+#define  MAX77620_SD_CFG1_ADE_MASK            BIT(3)
+#define  MAX77620_SD_CFG1_ADE_DISABLE         0
+#define  MAX77620_SD_CFG1_ADE_ENABLE          BIT(3)
+#define  MAX77620_SD_FPWM_MASK                0x04
+#define  MAX77620_SD_FPWM_SHIFT               2
+#define  MAX77620_SD_FSRADE_MASK              0x01
+#define  MAX77620_SD_FSRADE_SHIFT             0
+#define  MAX77620_SD_CFG1_FPWM_SD_MASK        BIT(2)
+#define  MAX77620_SD_CFG1_FPWM_SD_SKIP        0
+#define  MAX77620_SD_CFG1_FPWM_SD_FPWM        BIT(2)
+#define  MAX77620_SD_CFG1_MPOK_MASK           BIT(1)
+#define  MAX77620_SD_CFG1_FSRADE_SD_MASK      BIT(0)
+#define  MAX77620_SD_CFG1_FSRADE_SD_DISABLE   0
+#define  MAX77620_SD_CFG1_FSRADE_SD_ENABLE    BIT(0)
+
 #define MAX77620_REG_SD_CFG2        0x22
+#define  MAX77620_SD_CNF2_RSVD                BIT(0)
+#define  MAX77620_SD_CNF2_ROVS_EN_SD1         BIT(1)
+#define  MAX77620_SD_CNF2_ROVS_EN_SD0         BIT(2)
+
 #define MAX77620_REG_LDO0_CFG       0x23
 #define MAX77620_REG_LDO0_CFG2      0x24
 #define MAX77620_REG_LDO1_CFG       0x25
@@ -132,25 +190,35 @@
 #define MAX77620_REG_LDO7_CFG2      0x32
 #define MAX77620_REG_LDO8_CFG       0x33
 #define MAX77620_REG_LDO8_CFG2      0x34
-#define  MAX77620_LDO_POWER_MODE_MASK         0xC0
+/*! LDO CFG */
 #define  MAX77620_LDO_POWER_MODE_SHIFT        6
+#define  MAX77620_LDO_POWER_MODE_MASK         (3 << MAX77620_LDO_POWER_MODE_SHIFT)
 #define  MAX77620_POWER_MODE_NORMAL	          3
 #define  MAX77620_POWER_MODE_LPM              2
 #define  MAX77620_POWER_MODE_GLPM             1
 #define  MAX77620_POWER_MODE_DISABLE          0
-#define  MAX20024_LDO_CFG2_MPOK_MASK          (1 << 2)
+/*! LDO CFG2 */
+#define  MAX77620_LDO_CFG2_SS_MASK            (1 << 0)
+#define  MAX77620_LDO_CFG2_SS_FAST            (0 << 0)
+#define  MAX77620_LDO_CFG2_SS_SLOW            (1 << 0)
 #define  MAX77620_LDO_CFG2_ADE_MASK           (1 << 1)
 #define  MAX77620_LDO_CFG2_ADE_DISABLE        (0 << 1)
 #define  MAX77620_LDO_CFG2_ADE_ENABLE         (1 << 1)
-#define  MAX77620_LDO_CFG2_SS_MASK            (1 << 0)
+#define  MAX77620_LDO_CFG2_MPOK_MASK          BIT(2)
-#define  MAX77620_LDO_CFG2_SS_FAST            (1 << 0)
+#define  MAX77620_LDO_CFG2_POK_MASK           BIT(3)
-#define  MAX77620_LDO_CFG2_SS_SLOW            0
+#define  MAX77620_LDO_CFG2_COMP_SHIFT         4
+#define  MAX77620_LDO_CFG2_COMP_MASK          (3 << MAX77620_LDO_COMP_SHIFT)
+#define  MAX77620_LDO_CFG2_COMP_SLOW 	      3
+#define  MAX77620_LDO_CFG2_COMP_MID_SLOW      2
+#define  MAX77620_LDO_CFG2_COMP_MID_FAST      1
+#define  MAX77620_LDO_CFG2_COMP_FAST          0
+#define  MAX77620_LDO_CFG2_ALPM_EN_MASK       BIT(6)
+#define  MAX77620_LDO_CFG2_OVCLMP_MASK        BIT(7)
 
 #define MAX77620_REG_LDO_CFG3       0x35
-#define  MAX77620_TRACK4_MASK                 (1 << 5)
+#define  MAX77620_LDO_BIAS_EN                 BIT(0)
 #define  MAX77620_TRACK4_SHIFT                5
-
+#define  MAX77620_TRACK4_MASK                 (1 << MAX77620_TRACK4_SHIFT)
-#define MAX77620_LDO_SLEW_RATE_MASK 0x1
 
 #define MAX77620_REG_GPIO0          0x36
 #define MAX77620_REG_GPIO1          0x37
@@ -160,9 +228,6 @@
 #define MAX77620_REG_GPIO5          0x3B
 #define MAX77620_REG_GPIO6          0x3C
 #define MAX77620_REG_GPIO7          0x3D
-#define MAX77620_REG_PUE_GPIO       0x3E
-#define MAX77620_REG_PDE_GPIO       0x3F
-#define MAX77620_REG_AME_GPIO       0x40
 #define  MAX77620_CNFG_GPIO_DRV_MASK          (1 << 0)
 #define  MAX77620_CNFG_GPIO_DRV_PUSHPULL      (1 << 0)
 #define  MAX77620_CNFG_GPIO_DRV_OPENDRAIN     (0 << 0)
@@ -181,26 +246,44 @@
 #define  MAX77620_CNFG_GPIO_DBNC_8ms          (0x1 << 6)
 #define  MAX77620_CNFG_GPIO_DBNC_16ms         (0x2 << 6)
 #define  MAX77620_CNFG_GPIO_DBNC_32ms         (0x3 << 6)
+#define  MAX77620_GPIO_OUTPUT_DISABLE         0
+#define  MAX77620_GPIO_OUTPUT_ENABLE          1
+
+#define MAX77620_REG_PUE_GPIO       0x3E // Gpio Pullup resistor enable.
+#define MAX77620_REG_PDE_GPIO       0x3F // Gpio Pulldown resistor enable.
+
+#define MAX77620_REG_AME_GPIO       0x40 // Gpio pinmuxing. Clear bits are Standard GPIO.
 
 #define MAX77620_REG_ONOFFCNFG1     0x41
-#define  MAX77620_ONOFFCNFG1_SFT_RST          (1 << 7)
-#define  MAX77620_ONOFFCNFG1_MRT_MASK         0x38
-#define  MAX77620_ONOFFCNFG1_MRT_SHIFT        0x3
-#define  MAX77620_ONOFFCNFG1_SLPEN            (1 << 2)
-#define  MAX77620_ONOFFCNFG1_PWR_OFF          (1 << 1)
 #define  MAX20024_ONOFFCNFG1_CLRSE            0x18
+#define  MAX77620_ONOFFCNFG1_PWR_OFF          BIT(1)
+#define  MAX77620_ONOFFCNFG1_SLPEN            BIT(2)
+#define  MAX77620_ONOFFCNFG1_MRT_SHIFT        0x3
+#define  MAX77620_ONOFFCNFG1_MRT_MASK         0x38
+#define  MAX77620_ONOFFCNFG1_RSVD             BIT(6)
+#define  MAX77620_ONOFFCNFG1_SFT_RST          BIT(7)
 
 #define MAX77620_REG_ONOFFCNFG2     0x42
-#define  MAX77620_ONOFFCNFG2_SFT_RST_WK       (1 << 7)
+#define  MAX77620_ONOFFCNFG2_WK_EN0           BIT(0)
-#define  MAX77620_ONOFFCNFG2_WD_RST_WK        (1 << 6)
+#define  MAX77620_ONOFFCNFG2_WK_ALARM2        BIT(1)
-#define  MAX77620_ONOFFCNFG2_SLP_LPM_MSK      (1 << 5)
+#define  MAX77620_ONOFFCNFG2_WK_ALARM1        BIT(2)
-#define  MAX77620_ONOFFCNFG2_WK_ALARM1        (1 << 2)
+#define  MAX77620_ONOFFCNFG2_WK_MBATT         BIT(3) // MBATT event generates a wakeup signal. use it in android/l4t?
-#define  MAX77620_ONOFFCNFG2_WK_EN0           (1 << 0)
+#define  MAX77620_ONOFFCNFG2_WK_ACOK          BIT(4)
+#define  MAX77620_ONOFFCNFG2_SLP_LPM_MSK      BIT(5)
+#define  MAX77620_ONOFFCNFG2_WD_RST_WK        BIT(6)
+#define  MAX77620_ONOFFCNFG2_SFT_RST_WK       BIT(7)
 
 /* FPS Registers */
-#define MAX77620_REG_FPS_CFG0       0x43
+#define MAX77620_REG_FPS_CFG0       0x43 // FPS0.
-#define MAX77620_REG_FPS_CFG1       0x44
+#define MAX77620_REG_FPS_CFG1       0x44 // FPS1.
-#define MAX77620_REG_FPS_CFG2       0x45
+#define MAX77620_REG_FPS_CFG2       0x45 // FPS2.
+#define  MAX77620_FPS_ENFPS_SW_MASK           0x01
+#define  MAX77620_FPS_ENFPS_SW                0x01
+#define  MAX77620_FPS_EN_SRC_SHIFT            1
+#define  MAX77620_FPS_EN_SRC_MASK             0x06
+#define  MAX77620_FPS_TIME_PERIOD_SHIFT       3
+#define  MAX77620_FPS_TIME_PERIOD_MASK        0x38
+
 #define MAX77620_REG_FPS_LDO0       0x46
 #define MAX77620_REG_FPS_LDO1       0x47
 #define MAX77620_REG_FPS_LDO2       0x48
@@ -215,86 +298,48 @@
 #define MAX77620_REG_FPS_SD2        0x51
 #define MAX77620_REG_FPS_SD3        0x52
 #define MAX77620_REG_FPS_SD4        0x53
-#define MAX77620_REG_FPS_NONE       0
-#define  MAX77620_FPS_SRC_MASK                0xC0
-#define  MAX77620_FPS_SRC_SHIFT               6
-#define  MAX77620_FPS_PU_PERIOD_MASK          0x38
-#define  MAX77620_FPS_PU_PERIOD_SHIFT         3
-#define  MAX77620_FPS_PD_PERIOD_MASK          0x07
-#define  MAX77620_FPS_PD_PERIOD_SHIFT         0
-
-/* Minimum and maximum FPS period time (in microseconds) are
- * different for MAX77620 and Max20024.
- */
-#define MAX77620_FPS_COUNT 3
-
-#define MAX77620_FPS_PERIOD_MIN_US 40
-#define MAX20024_FPS_PERIOD_MIN_US 20
-
-#define MAX77620_FPS_PERIOD_MAX_US 2560
-#define MAX20024_FPS_PERIOD_MAX_US 5120
-
 #define MAX77620_REG_FPS_GPIO1      0x54
 #define MAX77620_REG_FPS_GPIO2      0x55
 #define MAX77620_REG_FPS_GPIO3      0x56
-#define  MAX77620_FPS_TIME_PERIOD_MASK        0x38
-#define  MAX77620_FPS_TIME_PERIOD_SHIFT       3
-#define  MAX77620_FPS_EN_SRC_MASK             0x06
-#define  MAX77620_FPS_EN_SRC_SHIFT            1
-#define  MAX77620_FPS_ENFPS_SW_MASK           0x01
-#define  MAX77620_FPS_ENFPS_SW                0x01
-
 #define MAX77620_REG_FPS_RSO        0x57
+#define  MAX77620_FPS_PD_PERIOD_SHIFT         0
+#define  MAX77620_FPS_PD_PERIOD_MASK          0x07
+#define  MAX77620_FPS_PU_PERIOD_SHIFT         3
+#define  MAX77620_FPS_PU_PERIOD_MASK          0x38
+#define  MAX77620_FPS_SRC_SHIFT               6
+#define  MAX77620_FPS_SRC_MASK                0xC0
+
+#define MAX77620_FPS_COUNT 3
+#define MAX77620_FPS_PERIOD_MIN_US 40
+#define MAX77620_FPS_PERIOD_MAX_US 2560
+
 #define MAX77620_REG_CID0           0x58
 #define MAX77620_REG_CID1           0x59
 #define MAX77620_REG_CID2           0x5A
 #define MAX77620_REG_CID3           0x5B
-#define MAX77620_REG_CID4           0x5C
+#define MAX77620_REG_CID4           0x5C // OTP version.
 #define MAX77620_REG_CID5           0x5D
-
+#define  MAX77620_CID_DIDO_MASK               0xF
-#define MAX77620_REG_DVSSD4         0x5E
+#define  MAX77620_CID_DIDO_SHIFT              0
-#define MAX20024_REG_MAX_ADD        0x70
-
 #define  MAX77620_CID_DIDM_MASK               0xF0
 #define  MAX77620_CID_DIDM_SHIFT              4
 
-/* CNCG2SD */
-#define MAX77620_SD_CNF2_ROVS_EN_SD1          (1 << 1)
-#define MAX77620_SD_CNF2_ROVS_EN_SD0          (1 << 2)
-
 /* Device Identification Metal */
 #define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
 /* Device Indentification OTP */
 #define MAX77620_CID5_DIDO(n) ((n) & 0xF)
 
-/* SD CNFG1 */
+#define MAX77620_REG_DVSSD4         0x5E
-#define MAX77620_SD_SR_MASK                   0xC0
+#define MAX20024_REG_MAX_ADD        0x70
-#define MAX77620_SD_SR_SHIFT                  6
-#define MAX77620_SD_POWER_MODE_MASK           0x30
-#define MAX77620_SD_POWER_MODE_SHIFT          4
-#define MAX77620_SD_CFG1_ADE_MASK             (1 << 3)
-#define MAX77620_SD_CFG1_ADE_DISABLE          0
-#define MAX77620_SD_CFG1_ADE_ENABLE           (1 << 3)
-#define MAX77620_SD_FPWM_MASK                 0x04
-#define MAX77620_SD_FPWM_SHIFT                2
-#define MAX77620_SD_FSRADE_MASK               0x01
-#define MAX77620_SD_FSRADE_SHIFT              0
-#define MAX77620_SD_CFG1_FPWM_SD_MASK         (1 << 2)
-#define MAX77620_SD_CFG1_FPWM_SD_SKIP         0
-#define MAX77620_SD_CFG1_FPWM_SD_FPWM         (1 << 2)
-#define MAX20024_SD_CFG1_MPOK_MASK            (1 << 1)
-#define MAX77620_SD_CFG1_FSRADE_SD_MASK       (1 << 0)
-#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE    0
-#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE     (1 << 0)
 
-#define MAX77620_IRQ_LVL2_GPIO_EDGE0          (1 << 0)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE0          BIT(0)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE1          (1 << 1)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE1          BIT(1)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE2          (1 << 2)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE2          BIT(2)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE3          (1 << 3)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE3          BIT(3)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE4          (1 << 4)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE4          BIT(4)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE5          (1 << 5)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE5          BIT(5)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE6          (1 << 6)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE6          BIT(6)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE7          (1 << 7)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE7          BIT(7)
 
 /* Interrupts */
 enum {
@@ -332,9 +377,4 @@ enum max77620_fps_src {
 	MAX77620_FPS_SRC_DEF,
 };
 
-enum max77620_chip_id {
-	MAX77620,
-	MAX20024,
-};
-
 #endif /* _MFD_MAX77620_H_ */

bdk/power/max7762x.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -17,161 +17,323 @@
 
 #include <power/max7762x.h>
 #include <power/max77620.h>
+#include <power/max77812.h>
+#include <soc/fuse.h>
 #include <soc/i2c.h>
+#include <soc/t210.h>
 #include <utils/util.h>
 
 #define REGULATOR_SD  0
 #define REGULATOR_LDO 1
+#define REGULATOR_BC0 2
+#define REGULATOR_BC1 3
 
-typedef struct _max77620_regulator_t
+typedef struct _max77620_fps_t
 {
-	u8 type;
-	const char *name;
-	u8 reg_sd;
-
-	u32 mv_step;
-	u32 mv_min;
-	u32 mv_default;
-	u32 mv_max;
-
-	u8 volt_addr;
-	u8 cfg_addr;
-
-	u8 volt_mask;
-	u8 enable_mask;
-	u8 enable_shift;
-	u8 status_mask;
-
 	u8 fps_addr;
 	u8 fps_src;
 	u8 pd_period;
 	u8 pu_period;
+} max77620_fps_t;
+
+typedef struct _max77621_ctrl_t
+{
+	u8 ctrl1_por;
+	u8 ctrl1_hos;
+	u8 ctrl2_por;
+	u8 ctrl2_hos;
+} max77621_ctrl_t;
+
+typedef struct _max77812_ctrl_t
+{
+	u8 mask;
+	u8 shift;
+	u8 rsvd0;
+	u8 rsvd1;
+} max77812_en_t;
+
+typedef struct _max77620_regulator_t
+{
+	const char *name;
+
+	u32 uv_step;
+	u32 uv_min;
+	u32 uv_default;
+	u32 uv_max;
+
+	u8 type;
+	u8 volt_addr;
+	u8 cfg_addr;
+	u8 volt_mask;
+
+	union {
+		max77620_fps_t fps;
+		max77621_ctrl_t ctrl;
+		max77812_en_t enable;
+	};
 } max77620_regulator_t;
 
 static const max77620_regulator_t _pmic_regulators[] = {
-	{  REGULATOR_SD,  "sd0", 0x16,  12500, 600000,  625000, 1400000,      MAX77620_REG_SD0,   MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x80,  MAX77620_REG_FPS_SD0,  1, 7, 1 },
+	{  "sd0",  12500, 600000,  625000, 1400000,  REGULATOR_SD,  MAX77620_REG_SD0,      MAX77620_REG_SD0_CFG,    MAX77620_SD0_VOLT_MASK,  {{ MAX77620_REG_FPS_SD0,  1, 7, 1 }} },
-	{  REGULATOR_SD,  "sd1", 0x17,  12500, 600000, 1125000, 1125000,      MAX77620_REG_SD1,   MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x40,  MAX77620_REG_FPS_SD1,  0, 1, 5 },
+	{  "sd1",  12500, 600000, 1125000, 1250000,  REGULATOR_SD,  MAX77620_REG_SD1,      MAX77620_REG_SD1_CFG,    MAX77620_SD1_VOLT_MASK,  {{ MAX77620_REG_FPS_SD1,  0, 1, 5 }} },
-	{  REGULATOR_SD,  "sd2", 0x18,  12500, 600000, 1325000, 1350000,      MAX77620_REG_SD2,   MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x20,  MAX77620_REG_FPS_SD2,  1, 5, 2 },
+	{  "sd2",  12500, 600000, 1325000, 1350000,  REGULATOR_SD,  MAX77620_REG_SD2,      MAX77620_REG_SD2_CFG,    MAX77620_SDX_VOLT_MASK,  {{ MAX77620_REG_FPS_SD2,  1, 5, 2 }} },
-	{  REGULATOR_SD,  "sd3", 0x19,  12500, 600000, 1800000, 1800000,      MAX77620_REG_SD3,   MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x10,  MAX77620_REG_FPS_SD3,  0, 3, 3 },
+	{  "sd3",  12500, 600000, 1800000, 1800000,  REGULATOR_SD,  MAX77620_REG_SD3,      MAX77620_REG_SD3_CFG,    MAX77620_SDX_VOLT_MASK,  {{ MAX77620_REG_FPS_SD3,  0, 3, 3 }} },
-	{ REGULATOR_LDO, "ldo0", 0x00,  25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO0, 3, 7, 0 },
+	{ "ldo0",  25000, 800000, 1200000, 1200000,  REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} },
-	{ REGULATOR_LDO, "ldo1", 0x00,  25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO1, 3, 7, 0 },
+	{ "ldo1",  25000, 800000, 1050000, 1050000,  REGULATOR_LDO, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO1, 3, 7, 0 }} },
-	{ REGULATOR_LDO, "ldo2", 0x00,  50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO2, 3, 7, 0 },
+	{ "ldo2",  50000, 800000, 1800000, 3300000,  REGULATOR_LDO, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO2, 3, 7, 0 }} },
-	{ REGULATOR_LDO, "ldo3", 0x00,  50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO3, 3, 7, 0 },
+	{ "ldo3",  50000, 800000, 3100000, 3100000,  REGULATOR_LDO, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO3, 3, 7, 0 }} },
-	{ REGULATOR_LDO, "ldo4", 0x00,  12500, 800000,  850000,  850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO4, 0, 7, 1 },
+	{ "ldo4",  12500, 800000,  850000, 1000000,  REGULATOR_LDO, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO4, 0, 7, 1 }} },
-	{ REGULATOR_LDO, "ldo5", 0x00,  50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO5, 3, 7, 0 },
+	{ "ldo5",  50000, 800000, 1800000, 1800000,  REGULATOR_LDO, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO5, 3, 7, 0 }} },
-	{ REGULATOR_LDO, "ldo6", 0x00,  50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO6, 3, 7, 0 },
+	{ "ldo6",  50000, 800000, 2900000, 2900000,  REGULATOR_LDO, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO6, 3, 7, 0 }} },
-	{ REGULATOR_LDO, "ldo7", 0x00,  50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO7, 1, 4, 3 },
+	{ "ldo7",  50000, 800000, 1050000, 1050000,  REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} },
-	{ REGULATOR_LDO, "ldo8", 0x00,  50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO8, 3, 7, 0 }
+	{ "ldo8",  50000, 800000, 1050000, 2800000,  REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} },
+
+	{ "max77621_CPU", 6250, 606250, 1000000, 1400000,  REGULATOR_BC0, MAX77621_VOUT_REG,    MAX77621_VOUT_DVS_REG,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
+	{ "max77621_GPU", 6250, 606250, 1200000, 1400000,  REGULATOR_BC0, MAX77621_VOUT_REG,    MAX77621_VOUT_DVS_REG,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
+	{ "max77812_CPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
+	//{ "max77812_GPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
+	//{ "max77812_RAM", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
 };
 
-static void _max77620_try_set_reg(u8 reg, u8 val)
+static u8 _max77812_get_address()
 {
-	u8 tmp;
+	static u8 max77812_i2c_addr = 0;
-	do
+
+	if (max77812_i2c_addr)
+		return max77812_i2c_addr;
+
+	max77812_i2c_addr =
+		!(FUSE(FUSE_RESERVED_ODM28_T210B01) & 1) ? MAX77812_PHASE31_CPU_I2C_ADDR : MAX77812_PHASE211_CPU_I2C_ADDR;
+
+	return max77812_i2c_addr;
+}
+
+static u8 _max7762x_get_i2c_address(u32 id)
 {
-		i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg, val);
+	const max77620_regulator_t *reg = &_pmic_regulators[id];
-		tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg);
+
-	} while (val != tmp);
+	// Choose the correct i2c address.
+	switch (reg->type)
+	{
+	case REGULATOR_SD:
+	case REGULATOR_LDO:
+		return MAX77620_I2C_ADDR;
+	case REGULATOR_BC0:
+		return (id == REGULATOR_CPU0 ? MAX77621_CPU_I2C_ADDR : MAX77621_GPU_I2C_ADDR);
+	case REGULATOR_BC1:
+		return _max77812_get_address();
+	default:
+		return 0;
+	}
+}
+
+static void _max7762x_set_reg(u8 addr, u8 reg, u8 val)
+{
+	u32 retries = 100;
+	while (retries)
+	{
+		if (i2c_send_byte(I2C_5, addr, reg, val))
+			break;
+
+		usleep(50);
+		retries--;
+	}
 }
 
 int max77620_regulator_get_status(u32 id)
 {
-	if (id > REGULATOR_MAX)
+	if (id > REGULATOR_LDO8)
 		return 0;
 
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
+	// SD power OK status.
 	if (reg->type == REGULATOR_SD)
-		return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & reg->status_mask) ? 0 : 1;
+	{
-	return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & 8) ? 1 : 0;
+		u8 mask = 1u << (7 - id);
+		return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & mask) ? 0 : 1;
+	}
+
+	// LDO power OK status.
+	return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & MAX77620_LDO_CFG2_POK_MASK) ? 1 : 0;
 }
 
 int max77620_regulator_config_fps(u32 id)
 {
-	if (id > REGULATOR_MAX)
+	if (id > REGULATOR_LDO8)
 		return 0;
 
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
-	_max77620_try_set_reg(reg->fps_addr,
+	// Set FPS configuration.
-		(reg->fps_src << MAX77620_FPS_SRC_SHIFT) | (reg->pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) | (reg->pd_period));
+	_max7762x_set_reg(MAX77620_I2C_ADDR,
+		reg->fps.fps_addr,
+		(reg->fps.fps_src   << MAX77620_FPS_SRC_SHIFT)       |
+		(reg->fps.pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) |
+		(reg->fps.pd_period << MAX77620_FPS_PD_PERIOD_SHIFT));
 
 	return 1;
 }
 
-int max77620_regulator_set_voltage(u32 id, u32 mv)
+int max7762x_regulator_set_voltage(u32 id, u32 mv)
 {
 	if (id > REGULATOR_MAX)
 		return 0;
 
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
-	if (mv < reg->mv_min || mv > reg->mv_max)
+	if (mv < reg->uv_min || mv > reg->uv_max)
 		return 0;
 
-	u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
+	u8 addr = _max7762x_get_i2c_address(id);
-	u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr);
+
+	// Calculate voltage multiplier.
+	u32 mult = (mv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
+	u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr);
 	val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
-	_max77620_try_set_reg(reg->volt_addr, val);
+
+	// Set voltage.
+	_max7762x_set_reg(addr, reg->volt_addr, val);
+
+	// If max77621 set DVS voltage also.
+	if (reg->type == REGULATOR_BC0)
+		_max7762x_set_reg(addr, reg->cfg_addr, MAX77621_VOUT_ENABLE_MASK | val);
+
+	// Wait for ramp up/down delay.
 	usleep(1000);
 
 	return 1;
 }
 
-int max77620_regulator_enable(u32 id, int enable)
+int max7762x_regulator_enable(u32 id, bool enable)
 {
+	u8 reg_addr;
+	u8 enable_val;
+	u8 enable_mask;
+	u8 enable_shift;
+
 	if (id > REGULATOR_MAX)
 		return 0;
 
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
-	u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr;
+	// Choose the correct i2c and register addresses and mask/shift for each type.
-	u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, addr);
+	switch (reg->type)
+	{
+	case REGULATOR_SD:
+		reg_addr     = reg->cfg_addr;
+		enable_val   = MAX77620_POWER_MODE_NORMAL;
+		enable_mask  = MAX77620_SD_POWER_MODE_MASK;
+		enable_shift = MAX77620_SD_POWER_MODE_SHIFT;
+		break;
+	case REGULATOR_LDO:
+		reg_addr     = reg->volt_addr;
+		enable_val   = MAX77620_POWER_MODE_NORMAL;
+		enable_mask  = MAX77620_LDO_POWER_MODE_MASK;
+		enable_shift = MAX77620_LDO_POWER_MODE_SHIFT;
+		break;
+	case REGULATOR_BC0:
+		reg_addr     = reg->volt_addr;
+		enable_val   = MAX77621_VOUT_ENABLE;
+		enable_mask  = MAX77621_DVC_DVS_ENABLE_MASK;
+		enable_shift = MAX77621_DVC_DVS_ENABLE_SHIFT;
+		break;
+	case REGULATOR_BC1:
+		reg_addr     = reg->cfg_addr;
+		enable_val   = MAX77812_EN_CTRL_ENABLE;
+		enable_mask  = reg->enable.mask;
+		enable_shift = reg->enable.shift;
+		break;
+	default:
+		return 0;
+	}
+
+	u8 addr = _max7762x_get_i2c_address(id);
+
+	// Read and enable/disable.
+	u8 val = i2c_recv_byte(I2C_5, addr, reg_addr);
+	val &= ~enable_mask;
+
 	if (enable)
-		val = (val & ~reg->enable_mask) | ((MAX77620_POWER_MODE_NORMAL << reg->enable_shift) & reg->enable_mask);
+		val |= (enable_val << enable_shift);
-	else
+
-		val &= ~reg->enable_mask;
+	// Set enable.
-	_max77620_try_set_reg(addr, val);
+	_max7762x_set_reg(addr, reg_addr, val);
+
+	// Wait for enable/disable ramp delay.
 	usleep(1000);
 
 	return 1;
 }
 
-// LDO only.
+void max77620_config_gpio(u32 gpio_id, bool enable)
-int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags)
 {
-	if (id > REGULATOR_MAX)
+	if (gpio_id > 7)
-		return 0;
+		return;
 
+	// Configure as standard GPIO.
+	u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO);
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, val & ~BIT(gpio_id));
+
+	// Set GPIO configuration.
+	if (enable)
+		val = MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DIR_OUTPUT | MAX77620_CNFG_GPIO_DRV_PUSHPULL;
+	else
+		val = MAX77620_CNFG_GPIO_DIR_INPUT | MAX77620_CNFG_GPIO_DRV_OPENDRAIN;
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO0 + gpio_id, val);
+}
+
+void max77621_config_default(u32 id, bool por)
+{
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
-	if (mv < reg->mv_min || mv > reg->mv_max)
+	if (reg->type != REGULATOR_BC0)
-		return 0;
+		return;
 
-	u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
+	u8 addr = _max7762x_get_i2c_address(id);
-	u8 val = ((flags << reg->enable_shift) & ~reg->volt_mask) | (mult & reg->volt_mask);
-	_max77620_try_set_reg(reg->volt_addr, val);
-	usleep(1000);
 
-	return 1;
+	if (por)
+	{
+		// Set voltage and disable power before changing the inductor.
+		max7762x_regulator_set_voltage(id, 1000000);
+		max7762x_regulator_enable(id, false);
+
+		// Configure to default.
+		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_por);
+		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_por);
+	}
+	else
+	{
+		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_hos);
+		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_hos);
+	}
 }
 
 void max77620_config_default()
 {
-	for (u32 i = 1; i <= REGULATOR_MAX; i++)
+	// Check if Erista OTP.
+	if (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4) != 0x35)
+		return;
+
+	// Set default voltages and enable regulators.
+	for (u32 i = 1; i <= REGULATOR_LDO8; i++)
 	{
-		i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4);
 		max77620_regulator_config_fps(i);
-		max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
+		max7762x_regulator_set_voltage(i, _pmic_regulators[i].uv_default);
-		if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE)
+		if (_pmic_regulators[i].fps.fps_src != MAX77620_FPS_SRC_NONE)
-			max77620_regulator_enable(i, 1);
+			max7762x_regulator_enable(i, true);
-	}
-	_max77620_try_set_reg(MAX77620_REG_SD_CFG2, 4);
 	}
 
+	// Enable SD0 output voltage sense and disable for SD1. Additionally disable the reserved bit.
+	_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, MAX77620_SD_CNF2_ROVS_EN_SD0);
+}
+
+// Stock HOS: disabled.
 void max77620_low_battery_monitor_config(bool enable)
 {
-	_max77620_try_set_reg(MAX77620_REG_CNFGGLBL1,
+	_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_CNFGGLBL1,
-		MAX77620_CNFGGLBL1_LBDAC_EN | (enable ? MAX77620_CNFGGLBL1_MPPLD : 0) |
+		MAX77620_CNFGGLBL1_LBDAC_EN             |
-		MAX77620_CNFGGLBL1_LBHYST_200 | MAX77620_CNFGGLBL1_LBDAC_2800);
+		(enable ? MAX77620_CNFGGLBL1_MPPLD : 0) |
+		MAX77620_CNFGGLBL1_LBHYST_200           |
+		MAX77620_CNFGGLBL1_LBDAC_2800);
 }

bdk/power/max7762x.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -32,11 +32,11 @@
 *  ldo1 | XUSB, PCIE    | 25000   | 800000 | 1050000    | 1050000 | 1.05V  (pcv)
 *  ldo2 | SDMMC1        | 50000   | 800000 | 1800000    | 3300000 |
 *  ldo3 | GC ASIC       | 50000   | 800000 | 3100000    | 3100000 | 3.1V   (pcv)
-*  ldo4 | RTC           | 12500   | 800000 |  850000    |  850000 |
+*  ldo4 | RTC           | 12500   | 800000 |  850000    |  850000 | 0.85V  (AO, pcv)
 *  ldo5 | GC Card       | 50000   | 800000 | 1800000    | 1800000 | 1.8V   (pcv)
-*  ldo6 | Touch, ALS    | 50000   | 800000 | 2900000    | 2900000 | 2.9V
+*  ldo6 | Touch, ALS    | 50000   | 800000 | 2900000    | 2900000 | 2.9V   (pcv)
-*  ldo7 | XUSB          | 50000   | 800000 | 1050000    | 1050000 |
+*  ldo7 | XUSB          | 50000   | 800000 | 1050000    | 1050000 | 1.05V  (pcv)
-*  ldo8 | XUSB, DC      | 50000   | 800000 | 1050000    | 1050000 |
+*  ldo8 | XUSB, DP, MCU | 50000   | 800000 | 1050000    | 2800000 | 1.05V/2.8V (pcv)
 */
 
 /*
@@ -58,61 +58,91 @@
 #define REGULATOR_LDO6 10
 #define REGULATOR_LDO7 11
 #define REGULATOR_LDO8 12
-#define REGULATOR_MAX 12
+#define REGULATOR_CPU0 13
+#define REGULATOR_GPU0 14
+#define REGULATOR_CPU1 15
+//#define REGULATOR_GPU1 16
+//#define REGULATOR_GPU1 17
+#define REGULATOR_MAX  15
 
 #define MAX77621_CPU_I2C_ADDR 0x1B
 #define MAX77621_GPU_I2C_ADDR 0x1C
 
-#define MAX77621_VOUT_REG 0
+#define MAX77621_VOUT_REG     0x00
-#define MAX77621_VOUT_DVS_REG 1
+#define MAX77621_VOUT_DVS_REG 0x01
-#define MAX77621_CONTROL1_REG 2
+#define MAX77621_CONTROL1_REG 0x02
-#define MAX77621_CONTROL2_REG 3
+#define MAX77621_CONTROL2_REG 0x03
-
+#define MAX77621_CHIPID1_REG  0x04
-/* MAX77621_VOUT */
+#define MAX77621_CHIPID2_REG  0x05
-#define MAX77621_VOUT_ENABLE  (1 << 7)
-#define MAX77621_VOUT_MASK    0x7F
-#define  MAX77621_VOUT_0_95V  0x37
-#define  MAX77621_VOUT_1_09V  0x4F
 
 /* MAX77621_VOUT_DVC_DVS */
-#define MAX77621_DVS_VOUT_MASK 0x7F
+#define MAX77621_DVC_DVS_VOLT_MASK    0x7F
+#define MAX77621_DVC_DVS_ENABLE_SHIFT 7
+#define MAX77621_DVC_DVS_ENABLE_MASK  (1 << MAX77621_DVC_DVS_ENABLE_SHIFT)
+
+/* MAX77621_VOUT */
+#define MAX77621_VOUT_DISABLE     0
+#define MAX77621_VOUT_ENABLE      1
+#define MAX77621_VOUT_ENABLE_MASK (MAX77621_VOUT_ENABLE << MAX77621_DVC_DVS_ENABLE_SHIFT)
 
 /* MAX77621_CONTROL1 */
-#define MAX77621_SNS_ENABLE        (1 << 7)
-#define MAX77621_FPWM_EN_M         (1 << 6)
-#define MAX77621_NFSR_ENABLE       (1 << 5)
-#define MAX77621_AD_ENABLE         (1 << 4)
-#define MAX77621_BIAS_ENABLE       (1 << 3)
-#define MAX77621_FREQSHIFT_9PER    (1 << 2)
-
 #define MAX77621_RAMP_12mV_PER_US  0x0
 #define MAX77621_RAMP_25mV_PER_US  0x1
 #define MAX77621_RAMP_50mV_PER_US  0x2
 #define MAX77621_RAMP_200mV_PER_US 0x3
 #define MAX77621_RAMP_MASK         0x3
 
+#define MAX77621_FREQSHIFT_9PER    BIT(2)
+#define MAX77621_BIAS_ENABLE       BIT(3)
+#define MAX77621_AD_ENABLE         BIT(4)
+#define MAX77621_NFSR_ENABLE       BIT(5)
+#define MAX77621_FPWM_EN_M         BIT(6)
+#define MAX77621_SNS_ENABLE        BIT(7)
+
 /* MAX77621_CONTROL2 */
-#define MAX77621_WDTMR_ENABLE    (1 << 6)
+#define MAX77621_INDUCTOR_MIN_30_PER  0
-#define MAX77621_DISCH_ENBABLE   (1 << 5)
+#define MAX77621_INDUCTOR_NOMINAL     1
-#define MAX77621_FT_ENABLE		 (1 << 4)
+#define MAX77621_INDUCTOR_PLUS_30_PER 2
-#define MAX77621_T_JUNCTION_120	 (1 << 7)
+#define MAX77621_INDUCTOR_PLUS_60_PER 3
+#define MAX77621_INDUCTOR_MASK        3
 
-#define MAX77621_CKKADV_TRIP_DISABLE              0xC
 #define MAX77621_CKKADV_TRIP_75mV_PER_US          0x0
-#define MAX77621_CKKADV_TRIP_150mV_PER_US         0x4
+#define MAX77621_CKKADV_TRIP_150mV_PER_US         BIT(2)
-#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8
+#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS BIT(3)
+#define MAX77621_CKKADV_TRIP_DISABLE              (BIT(2) | BIT(3))
+#define MAX77621_CKKADV_TRIP_MASK                 (BIT(2) | BIT(3))
 
-#define MAX77621_INDUCTOR_MIN_30_PER  0x0
+#define MAX77621_FT_ENABLE       BIT(4)
-#define MAX77621_INDUCTOR_NOMINAL     0x1
+#define MAX77621_DISCH_ENABLE    BIT(5)
-#define MAX77621_INDUCTOR_PLUS_30_PER 0x2
+#define MAX77621_WDTMR_ENABLE    BIT(6)
-#define MAX77621_INDUCTOR_PLUS_60_PER 0x3
+#define MAX77621_T_JUNCTION_120  BIT(7)
+
+#define MAX77621_CPU_CTRL1_POR_DEFAULT  (MAX77621_RAMP_50mV_PER_US)
+#define MAX77621_CPU_CTRL1_HOS_DEFAULT  (MAX77621_AD_ENABLE                        | \
+										 MAX77621_NFSR_ENABLE                      | \
+										 MAX77621_SNS_ENABLE                       | \
+										 MAX77621_RAMP_12mV_PER_US)
+#define MAX77621_CPU_CTRL2_POR_DEFAULT  (MAX77621_T_JUNCTION_120                   | \
+										 MAX77621_FT_ENABLE                        | \
+										 MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS | \
+										 MAX77621_CKKADV_TRIP_150mV_PER_US         | \
+										 MAX77621_INDUCTOR_NOMINAL)
+#define MAX77621_CPU_CTRL2_HOS_DEFAULT  (MAX77621_T_JUNCTION_120                   | \
+										 MAX77621_WDTMR_ENABLE                     | \
+										 MAX77621_CKKADV_TRIP_75mV_PER_US          | \
+										 MAX77621_INDUCTOR_NOMINAL)
+
+#define MAX77621_CTRL_HOS_CFG 0
+#define MAX77621_CTRL_POR_CFG 1
 
 int  max77620_regulator_get_status(u32 id);
 int  max77620_regulator_config_fps(u32 id);
-int max77620_regulator_set_voltage(u32 id, u32 mv);
+int  max7762x_regulator_set_voltage(u32 id, u32 mv);
-int max77620_regulator_enable(u32 id, int enable);
+int  max7762x_regulator_enable(u32 id, bool enable);
-int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags);
+void max77620_config_gpio(u32 id, bool enable);
 void max77620_config_default();
 void max77620_low_battery_monitor_config(bool enable);
 
+void max77621_config_default(u32 id, bool por);
+
 #endif

bdk/power/max77812.h

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MAX77812_H_
+#define _MAX77812_H_
+
+#define MAX77812_PHASE31_CPU_I2C_ADDR  0x31 // 2 Outputs: 3-phase M1 + 1-phase M4.
+#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
+
+#define MAX77812_REG_RSET			0x00
+#define MAX77812_REG_INT_SRC		0x01
+#define MAX77812_REG_INT_SRC_M		0x02
+#define MAX77812_REG_TOPSYS_INT		0x03
+#define MAX77812_REG_TOPSYS_INT_M	0x04
+#define MAX77812_REG_TOPSYS_STAT	0x05
+#define MAX77812_REG_EN_CTRL		0x06
+#define  MAX77812_EN_CTRL_ENABLE      1
+#define  MAX77812_EN_CTRL_EN_M1_SHIFT 0
+#define  MAX77812_EN_CTRL_EN_M1_MASK  (1 << MAX77812_EN_CTRL_EN_M1_SHIFT)
+#define  MAX77812_EN_CTRL_EN_M2_SHIFT 2
+#define  MAX77812_EN_CTRL_EN_M2_MASK  (1 << MAX77812_EN_CTRL_EN_M2_SHIFT)
+#define  MAX77812_EN_CTRL_EN_M3_SHIFT 4
+#define  MAX77812_EN_CTRL_EN_M3_MASK  (1 << MAX77812_EN_CTRL_EN_M3_SHIFT)
+#define  MAX77812_EN_CTRL_EN_M4_SHIFT 6
+#define  MAX77812_EN_CTRL_EN_M4_MASK  (1 << MAX77812_EN_CTRL_EN_M4_SHIFT)
+#define MAX77812_REG_STUP_DLY2		0x07
+#define MAX77812_REG_STUP_DLY3		0x08
+#define MAX77812_REG_STUP_DLY4		0x09
+#define MAX77812_REG_SHDN_DLY1		0x0A
+#define MAX77812_REG_SHDN_DLY2		0x0B
+#define MAX77812_REG_SHDN_DLY3		0x0C
+#define MAX77812_REG_SHDN_DLY4		0x0D
+#define MAX77812_REG_WDTRSTB_DEB	0x0E
+#define MAX77812_REG_GPI_FUNC		0x0F
+#define MAX77812_REG_GPI_DEB1		0x10
+#define MAX77812_REG_GPI_DEB2		0x11
+#define MAX77812_REG_GPI_PD_CTRL	0x12
+#define MAX77812_REG_PROT_CFG		0x13
+#define MAX77812_REG_VERSION		0x14
+#define MAX77812_REG_I2C_CFG		0x15
+#define MAX77812_REG_BUCK_INT		0x20
+#define MAX77812_REG_BUCK_INT_M		0x21
+#define MAX77812_REG_BUCK_STAT		0x22
+#define MAX77812_REG_M1_VOUT		0x23 // GPU.
+#define MAX77812_REG_M2_VOUT		0x24
+#define MAX77812_REG_M3_VOUT		0x25 // DRAM on PHASE211.
+#define MAX77812_REG_M4_VOUT		0x26 // CPU.
+#define MAX77812_REG_M1_VOUT_D		0x27
+#define MAX77812_REG_M2_VOUT_D		0x28
+#define MAX77812_REG_M3_VOUT_D		0x29
+#define MAX77812_REG_M4_VOUT_D		0x2A
+#define MAX77812_REG_M1_VOUT_S		0x2B
+#define MAX77812_REG_M2_VOUT_S		0x2C
+#define MAX77812_REG_M3_VOUT_S		0x2D
+#define MAX77812_REG_M4_VOUT_S		0x2E
+#define MAX77812_REG_M1_CFG			0x2F
+#define MAX77812_REG_M2_CFG			0x30
+#define MAX77812_REG_M3_CFG			0x31
+#define MAX77812_REG_M4_CFG			0x32
+#define MAX77812_REG_GLB_CFG1		0x33
+#define MAX77812_REG_GLB_CFG2		0x34
+#define MAX77812_REG_GLB_CFG3		0x35
+
+/*! Protected area and settings only for MAX77812_REG_VERSION 4 */
+#define MAX77812_REG_GLB_CFG4		0x36
+#define MAX77812_REG_GLB_CFG5		0x37
+#define MAX77812_REG_GLB_CFG6		0x38
+#define MAX77812_REG_GLB_CFG7		0x39
+#define MAX77812_REG_GLB_CFG8		0x3A
+#define MAX77812_REG_PROT_ACCESS	0xFD
+#define MAX77812_REG_MAX			0xFE
+
+#define MAX77812_REG_EN_CTRL_MASK(n)		BIT(n)
+#define MAX77812_START_SLEW_RATE_MASK		0x07
+#define MAX77812_SHDN_SLEW_RATE_MASK		0x70
+#define MAX77812_RAMPUP_SLEW_RATE_MASK		0x07
+#define MAX77812_RAMPDOWN_SLEW_RATE_MASK	0x70
+#define MAX77812_SLEW_RATE_SHIFT			4
+
+#define MAX77812_OP_ACTIVE_DISCHARGE_MASK	BIT(7)
+#define MAX77812_PEAK_CURRENT_LMT_MASK		0x70
+#define MAX77812_SWITCH_FREQ_MASK			0x0C
+#define MAX77812_FORCED_PWM_MASK			BIT(1)
+#define MAX77812_SLEW_RATE_CNTRL_MASK		BIT(0)
+#define MAX77812_START_SHD_DELAY_MASK		0x1F
+#define MAX77812_VERSION_MASK				0x07
+#define MAX77812_ES2_VERSION				0x04
+#define MAX77812_QS_VERSION					0x05
+
+#define MAX77812_BUCK_VOLT_MASK				0xFF
+
+#endif

bdk/power/regulator_5v.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,63 +14,112 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <soc/fuse.h>
 #include <soc/gpio.h>
+#include <soc/hw_init.h>
 #include <soc/pinmux.h>
 #include <soc/pmc.h>
 #include <soc/t210.h>
 #include <utils/types.h>
 
 static u8 reg_5v_dev = 0;
+static bool usb_src = false;
 
-void regulator_enable_5v(u8 dev)
+void regulator_5v_enable(u8 dev)
 {
 	// The power supply selection from battery or USB is automatic.
 	if (!reg_5v_dev)
 	{
-		// Fan and Rail power from internal 5V regulator (battery).
+		// Fan and Rail power from battery 5V regulator.
 		PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = 1;
 		gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_GPIO);
 		gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_ENABLE);
 		gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH);
 
-		// Fan and Rail power from USB 5V VDD.
+		// Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula.
+		u32 hw_type = fuse_read_hw_type();
+		if (hw_type == FUSE_NX_HW_TYPE_ICOSA ||
+			hw_type == FUSE_NX_HW_TYPE_IOWA)
+		{
+			// Fan and Rail power from USB 5V VBUS.
 			PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1;
 			gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_GPIO);
 			gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_ENABLE);
-		gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_HIGH);
+			gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
+		}
 
+		// Enable GPIO AO IO rail for T210.
+		if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
+		{
 			// Make sure GPIO power is enabled.
 			PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN;
+			(void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write.
+
 			// Override power detect for GPIO AO IO rails.
 			PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN;
+			(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
+		}
+		usb_src = false;
 	}
 	reg_5v_dev |= dev;
 }
 
-void regulator_disable_5v(u8 dev)
+void regulator_5v_disable(u8 dev)
 {
 	reg_5v_dev &= ~dev;
 
 	if (!reg_5v_dev)
 	{
-		// Rail power from internal 5V regulator (battery).
+		// Rail power from battery 5V regulator.
 		gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_LOW);
 		gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_DISABLE);
 		gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_SPIO);
 		PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = PINMUX_PARKED | PINMUX_INPUT_ENABLE;
 
-		// Rail power from USB 5V VDD.
+		// Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula.
+		u32 hw_type = fuse_read_hw_type();
+		if (hw_type == FUSE_NX_HW_TYPE_ICOSA ||
+			hw_type == FUSE_NX_HW_TYPE_IOWA)
+		{
+			// Rail power from USB 5V VBUS.
 			gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
 			gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
 			gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_SPIO);
 			PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_PARKED | PINMUX_INPUT_ENABLE;
+			usb_src = false;
+
+		}
 
 		// GPIO AO IO rails.
+		if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
+		{
 			PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_GPIO_IO_EN;
+			(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
+		}
 	}
 }
 
-bool regulator_get_5v_dev_enabled(u8 dev)
+bool regulator_5v_get_dev_enabled(u8 dev)
 {
 	return (reg_5v_dev & dev);
 }
+
+void regulator_5v_usb_src_enable(bool enable)
+{
+	// Only for Icosa/Iowa. Skip on Hoag/Aula.
+	u32 hw_type = fuse_read_hw_type();
+	if (hw_type != FUSE_NX_HW_TYPE_ICOSA &&
+		hw_type != FUSE_NX_HW_TYPE_IOWA)
+		return;
+
+	if (enable && !usb_src)
+	{
+		gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_HIGH);
+		usb_src = true;
+	}
+	else if (!enable && usb_src)
+	{
+		gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
+		usb_src = false;
+	}
+}

bdk/power/regulator_5v.h

@@ -21,14 +21,15 @@
 
 enum
 {
-	REGULATOR_5V_FAN  = (1 << 0),
+	REGULATOR_5V_FAN  = BIT(0),
-	REGULATOR_5V_JC_R = (1 << 1),
+	REGULATOR_5V_JC_R = BIT(1),
-	REGULATOR_5V_JC_L = (1 << 2),
+	REGULATOR_5V_JC_L = BIT(2),
 	REGULATOR_5V_ALL  = 0xFF
 };
 
-void regulator_enable_5v(u8 dev);
+void regulator_5v_enable(u8 dev);
-void regulator_disable_5v(u8 dev);
+void regulator_5v_disable(u8 dev);
-bool regulator_get_5v_dev_enabled(u8 dev);
+bool regulator_5v_get_dev_enabled(u8 dev);
+void regulator_5v_usb_src_enable(bool enable);
 
 #endif

bdk/rtc/max77620-rtc.h

@@ -27,17 +27,17 @@
 
 #define MAX77620_RTC_CONTROLM_REG   0x02
 #define MAX77620_RTC_CONTROL_REG    0x03
-#define  MAX77620_RTC_BIN_FORMAT (1 << 0)
+#define  MAX77620_RTC_BIN_FORMAT    BIT(0)
-#define  MAX77620_RTC_24H        (1 << 1)
+#define  MAX77620_RTC_24H           BIT(1)
 
 #define MAX77620_RTC_UPDATE0_REG    0x04
-#define  MAX77620_RTC_WRITE_UPDATE  (1 << 0)
+#define  MAX77620_RTC_WRITE_UPDATE  BIT(0)
-#define  MAX77620_RTC_READ_UPDATE   (1 << 4)
+#define  MAX77620_RTC_READ_UPDATE   BIT(4)
 
 #define MAX77620_RTC_SEC_REG        0x07
 #define MAX77620_RTC_MIN_REG        0x08
 #define MAX77620_RTC_HOUR_REG       0x09
-#define  MAX77620_RTC_HOUR_PM_MASK  (1 << 6)
+#define  MAX77620_RTC_HOUR_PM_MASK  BIT(6)
 #define MAX77620_RTC_WEEKDAY_REG    0x0A
 #define MAX77620_RTC_MONTH_REG      0x0B
 #define MAX77620_RTC_YEAR_REG       0x0C
@@ -57,7 +57,7 @@
 #define MAX77620_ALARM2_MONTH_REG   0x19
 #define MAX77620_ALARM2_YEAR_REG    0x1A
 #define MAX77620_ALARM2_DATE_REG    0x1B
-#define  MAX77620_RTC_ALARM_EN_MASK	(1 << 7)
+#define  MAX77620_RTC_ALARM_EN_MASK	BIT(7)
 
 typedef struct _rtc_time_t {
 	u8  weekday;

bdk/sec/se.c

@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  * Copyright (c) 2018 Atmosphère-NX
- * Copyright (c) 2019-2020 shchmue
+ * Copyright (c) 2019-2021 shchmue
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -24,6 +24,7 @@
 #include <memory_map.h>
 #include <mem/heap.h>
 #include <soc/bpmp.h>
+#include <soc/pmc.h>
 #include <soc/t210.h>
 #include <utils/util.h>
 
@@ -34,8 +35,8 @@ typedef struct _se_ll_t
 	vu32 size;
 } se_ll_t;
 
-static u32 _se_rsa_mod_sizes[TEGRA_SE_RSA_KEYSLOT_COUNT];
+static u32 _se_rsa_mod_sizes[SE_RSA_KEYSLOT_COUNT];
-static u32 _se_rsa_exp_sizes[TEGRA_SE_RSA_KEYSLOT_COUNT];
+static u32 _se_rsa_exp_sizes[SE_RSA_KEYSLOT_COUNT];
 
 static void _gf256_mul_x(void *block)
 {
@@ -78,88 +79,125 @@ static void _se_ll_init(se_ll_t *ll, u32 addr, u32 size)
 
 static void _se_ll_set(se_ll_t *dst, se_ll_t *src)
 {
-	SE(SE_IN_LL_ADDR_REG_OFFSET) = (u32)src;
+	SE(SE_IN_LL_ADDR_REG) = (u32)src;
-	SE(SE_OUT_LL_ADDR_REG_OFFSET) = (u32)dst;
+	SE(SE_OUT_LL_ADDR_REG) = (u32)dst;
 }
 
 static int _se_wait()
 {
-	while (!(SE(SE_INT_STATUS_REG_OFFSET) & SE_INT_OP_DONE(INT_SET)))
+	while (!(SE(SE_INT_STATUS_REG) & SE_INT_OP_DONE))
 		;
-	if (SE(SE_INT_STATUS_REG_OFFSET) & SE_INT_ERROR(INT_SET) ||
+	if (SE(SE_INT_STATUS_REG) & SE_INT_ERR_STAT ||
-		SE(SE_STATUS_0) & SE_STATUS_0_STATE_WAIT_IN ||
+	   (SE(SE_STATUS_REG) & SE_STATUS_STATE_MASK) != SE_STATUS_STATE_IDLE ||
-		SE(SE_ERR_STATUS_0) != SE_ERR_STATUS_0_SE_NS_ACCESS_CLEAR)
+		SE(SE_ERR_STATUS_REG) != 0)
 		return 0;
 	return 1;
 }
 
-static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size)
+se_ll_t *ll_dst, *ll_src;
+static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size, bool is_oneshot)
 {
-	static se_ll_t *ll_dst = NULL, *ll_src = NULL;
+	ll_dst = NULL;
-	if (!ll_dst)
+	ll_src = NULL;
-	{
-		ll_dst = (se_ll_t *)malloc(sizeof(se_ll_t));
-		ll_src = (se_ll_t *)malloc(sizeof(se_ll_t));
-	}
 
 	if (dst)
 	{
+		ll_dst = (se_ll_t *)malloc(sizeof(se_ll_t));
 		_se_ll_init(ll_dst, (u32)dst, dst_size);
 	}
 
 	if (src)
 	{
+		ll_src = (se_ll_t *)malloc(sizeof(se_ll_t));
 		_se_ll_init(ll_src, (u32)src, src_size);
 	}
 
 	_se_ll_set(ll_dst, ll_src);
 
-	SE(SE_ERR_STATUS_0) = SE(SE_ERR_STATUS_0);
+	SE(SE_ERR_STATUS_REG) = SE(SE_ERR_STATUS_REG);
-	SE(SE_INT_STATUS_REG_OFFSET) = SE(SE_INT_STATUS_REG_OFFSET);
+	SE(SE_INT_STATUS_REG) = SE(SE_INT_STATUS_REG);
 
 	bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
 
-	SE(SE_OPERATION_REG_OFFSET) = SE_OPERATION(op);
+	SE(SE_OPERATION_REG) = op;
+
+	if (is_oneshot)
+	{
 		int res = _se_wait();
 
 		bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
 
+		if (src)
+			free(ll_src);
+		if (dst)
+			free(ll_dst);
+
 		return res;
 	}
 
+	return 1;
+}
+
+static int _se_execute_finalize()
+{
+	int res = _se_wait();
+
+	bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
+
+	if (ll_src)
+	{
+		free(ll_src);
+		ll_src = NULL;
+	}
+	if (ll_dst)
+	{
+		free(ll_dst);
+		ll_dst = NULL;
+	}
+
+	return res;
+}
+
+static int _se_execute_oneshot(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size)
+{
+	return _se_execute(op, dst, dst_size, src, src_size, true);
+}
+
 static int _se_execute_one_block(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size)
 {
 	if (!src || !dst)
 		return 0;
 
-	u8 *block = (u8 *)malloc(0x10);
+	u8 *block = (u8 *)malloc(SE_AES_BLOCK_SIZE);
-	memset(block, 0, 0x10);
+	memset(block, 0, SE_AES_BLOCK_SIZE);
 
-	SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1;
 
 	memcpy(block, src, src_size);
-	int res = _se_execute(op, block, 0x10, block, 0x10);
+	int res = _se_execute_oneshot(op, block, SE_AES_BLOCK_SIZE, block, SE_AES_BLOCK_SIZE);
 	memcpy(dst, block, dst_size);
 
 	free(block);
 	return res;
 }
 
-static void _se_aes_ctr_set(void *ctr)
+static void _se_aes_ctr_set(const void *ctr)
 {
-	u32 *data = (u32 *)ctr;
+	u32 data[SE_AES_IV_SIZE / 4];
-	for (u32 i = 0; i < 4; i++)
+	memcpy(data, ctr, SE_AES_IV_SIZE);
-		SE(SE_CRYPTO_CTR_REG_OFFSET + 4 * i) = data[i];
+
+	for (u32 i = 0; i < SE_CRYPTO_LINEAR_CTR_REG_COUNT; i++)
+		SE(SE_CRYPTO_LINEAR_CTR_REG + (4 * i)) = data[i];
 }
 
 void se_rsa_acc_ctrl(u32 rs, u32 flags)
 {
-	if (flags & SE_RSA_KEY_TBL_DIS_KEY_ALL_FLAG)
+	if (flags & SE_RSA_KEY_TBL_DIS_KEY_ACCESS_FLAG)
-		SE(SE_RSA_KEYTABLE_ACCESS_REG_OFFSET + 4 * rs) =
+		SE(SE_RSA_KEYTABLE_ACCESS_REG + 4 * rs) =
-			((flags >> SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) |
+			(((flags >> 4) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) |(flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG)) ^
-			((flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG) ^ SE_RSA_KEY_TBL_DIS_KEY_ALL_COMMON_FLAG);
+				SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_USE_FLAG;
-	if (flags & SE_RSA_KEY_TBL_DIS_KEY_LOCK_FLAG)
+	if (flags & SE_RSA_KEY_LOCK_FLAG)
-		SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) &= ~(1 << rs);
+		SE(SE_RSA_SECURITY_PERKEY_REG) &= ~BIT(rs);
 }
 
 // se_rsa_key_set() was derived from Atmosphère's set_rsa_keyslot
@@ -168,15 +206,15 @@ void se_rsa_key_set(u32 ks, const void *mod, u32 mod_size, const void *exp, u32
 	u32 *data = (u32 *)mod;
 	for (u32 i = 0; i < mod_size / 4; i++)
 	{
-		SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_MOD) | i;
+		SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_MOD) | i;
-		SE(SE_RSA_KEYTABLE_DATA) = byte_swap_32(data[mod_size / 4 - i - 1]);
+		SE(SE_RSA_KEYTABLE_DATA_REG) = byte_swap_32(data[mod_size / 4 - i - 1]);
 	}
 
 	data = (u32 *)exp;
 	for (u32 i = 0; i < exp_size / 4; i++)
 	{
-		SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_EXP) | i;
+		SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_EXP) | i;
-		SE(SE_RSA_KEYTABLE_DATA) = byte_swap_32(data[exp_size / 4 - i - 1]);
+		SE(SE_RSA_KEYTABLE_DATA_REG) = byte_swap_32(data[exp_size / 4 - i - 1]);
 	}
 
 	_se_rsa_mod_sizes[ks] = mod_size;
@@ -186,15 +224,15 @@ void se_rsa_key_set(u32 ks, const void *mod, u32 mod_size, const void *exp, u32
 // se_rsa_key_clear() was derived from Atmosphère's clear_rsa_keyslot
 void se_rsa_key_clear(u32 ks)
 {
-	for (u32 i = 0; i < TEGRA_SE_RSA2048_DIGEST_SIZE / 4; i++)
+	for (u32 i = 0; i < SE_RSA2048_DIGEST_SIZE / 4; i++)
 	{
-		SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_MOD) | i;
+		SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_MOD) | i;
-		SE(SE_RSA_KEYTABLE_DATA) = 0;
+		SE(SE_RSA_KEYTABLE_DATA_REG) = 0;
 	}
-	for (u32 i = 0; i < TEGRA_SE_RSA2048_DIGEST_SIZE / 4; i++)
+	for (u32 i = 0; i < SE_RSA2048_DIGEST_SIZE / 4; i++)
 	{
-		SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_EXP) | i;
+		SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_EXP) | i;
-		SE(SE_RSA_KEYTABLE_DATA) = 0;
+		SE(SE_RSA_KEYTABLE_DATA_REG) = 0;
 	}
 }
 
@@ -202,22 +240,22 @@ void se_rsa_key_clear(u32 ks)
 int se_rsa_exp_mod(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
 {
 	int res;
-	u8 stack_buf[TEGRA_SE_RSA2048_DIGEST_SIZE];
+	u8 stack_buf[SE_RSA2048_DIGEST_SIZE];
 
 	for (u32 i = 0; i < src_size; i++)
 		stack_buf[i] = *((u8 *)src + src_size - i - 1);
 
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RSA) | SE_CONFIG_DST(DST_RSAREG);
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RSA) | SE_CONFIG_DST(DST_RSAREG);
 	SE(SE_RSA_CONFIG) = RSA_KEY_SLOT(ks);
-	SE(SE_RSA_KEY_SIZE_REG_OFFSET) = (_se_rsa_mod_sizes[ks] >> 6) - 1;
+	SE(SE_RSA_KEY_SIZE_REG) = (_se_rsa_mod_sizes[ks] >> 6) - 1;
-	SE(SE_RSA_EXP_SIZE_REG_OFFSET) = _se_rsa_exp_sizes[ks] >> 2;
+	SE(SE_RSA_EXP_SIZE_REG) = _se_rsa_exp_sizes[ks] >> 2;
 
-	res = _se_execute(OP_START, NULL, 0, stack_buf, src_size);
+	res = _se_execute_oneshot(SE_OP_START, NULL, 0, stack_buf, src_size);
 
 	// Copy output hash.
 	u32 *dst32 = (u32 *)dst;
 	for (u32 i = 0; i < dst_size / 4; i++)
-		dst32[dst_size / 4 - i - 1] = byte_swap_32(SE(SE_RSA_OUTPUT + (i << 2)));
+		dst32[dst_size / 4 - i - 1] = byte_swap_32(SE(SE_RSA_OUTPUT_REG + (i * 4)));
 
 	return res;
 }
@@ -225,116 +263,146 @@ int se_rsa_exp_mod(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_siz
 void se_key_acc_ctrl(u32 ks, u32 flags)
 {
 	if (flags & SE_KEY_TBL_DIS_KEY_ACCESS_FLAG)
-		SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 4 * ks) = ~flags;
+		SE(SE_CRYPTO_KEYTABLE_ACCESS_REG + 4 * ks) = ~flags;
-	if (flags & SE_KEY_TBL_DIS_KEY_LOCK_FLAG)
+	if (flags & SE_KEY_LOCK_FLAG)
-		SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) &= ~(1 << ks);
+		SE(SE_CRYPTO_SECURITY_PERKEY_REG) &= ~BIT(ks);
 }
 
 u32 se_key_acc_ctrl_get(u32 ks)
 {
-	return SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 4 * ks);
+	return SE(SE_CRYPTO_KEYTABLE_ACCESS_REG + 4 * ks);
 }
 
 void se_aes_key_set(u32 ks, const void *key, u32 size)
 {
-	u32 *data = (u32 *)key;
+	u32 data[SE_AES_MAX_KEY_SIZE / 4];
-	for (u32 i = 0; i < size / 4; i++)
+	memcpy(data, key, size);
+
+	for (u32 i = 0; i < (size / 4); i++)
 	{
-		SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
+		SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_PKT(i); // QUAD is automatically set by PKT.
-		SE(SE_KEYTABLE_DATA0_REG_OFFSET) = data[i];
+		SE(SE_CRYPTO_KEYTABLE_DATA_REG) = data[i];
 	}
 }
 
-void se_aes_iv_set(u32 ks, const void *iv, u32 size)
+void se_aes_key_partial_set(u32 ks, u32 index, u32 data)
 {
-	u32 *data = (u32 *)iv;
+	SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | index;
-	for (u32 i = 0; i < size / 4; i++)
+	SE(SE_CRYPTO_KEYTABLE_DATA_REG) = data;
+}
+
+void se_aes_iv_set(u32 ks, const void *iv)
 {
-		SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | 8 | i;
+	u32 data[SE_AES_IV_SIZE / 4];
-		SE(SE_KEYTABLE_DATA0_REG_OFFSET) = data[i];
+	memcpy(data, iv, SE_AES_IV_SIZE);
+
+	for (u32 i = 0; i < (SE_AES_IV_SIZE / 4); i++)
+	{
+		SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(ORIGINAL_IV) | SE_KEYTABLE_PKT(i);
+		SE(SE_CRYPTO_KEYTABLE_DATA_REG) = data[i];
 	}
 }
 
-void se_aes_key_read(u32 ks, void *key, u32 size)
+void se_aes_key_get(u32 ks, void *key, u32 size)
 {
-	u32 *data = (u32 *)key;
+	u32 data[SE_AES_MAX_KEY_SIZE / 4];
-	for (u32 i = 0; i < size / 4; i++)
+
+	for (u32 i = 0; i < (size / 4); i++)
 	{
-		SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
+		SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_PKT(i); // QUAD is automatically set by PKT.
-		data[i] = SE(SE_KEYTABLE_DATA0_REG_OFFSET);
+		data[i] = SE(SE_CRYPTO_KEYTABLE_DATA_REG);
 	}
+
+	memcpy(key, data, size);
 }
 
 void se_aes_key_clear(u32 ks)
 {
-	for (u32 i = 0; i < TEGRA_SE_AES_MAX_KEY_SIZE / 4; i++)
+	for (u32 i = 0; i < (SE_AES_MAX_KEY_SIZE / 4); i++)
 	{
-		SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
+		SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_PKT(i); // QUAD is automatically set by PKT.
-		SE(SE_KEYTABLE_DATA0_REG_OFFSET) = 0;
+		SE(SE_CRYPTO_KEYTABLE_DATA_REG) = 0;
 	}
 }
 
-void se_aes_key_iv_clear(u32 ks)
+void se_aes_iv_clear(u32 ks)
 {
-	for (u32 i = 0; i < TEGRA_SE_AES_MAX_KEY_SIZE / 4; i++)
+	for (u32 i = 0; i < (SE_AES_IV_SIZE / 4); i++)
 	{
-		SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | 8 | i;
+		SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(ORIGINAL_IV) | SE_KEYTABLE_PKT(i);
-		SE(SE_KEYTABLE_DATA0_REG_OFFSET) = 0;
+		SE(SE_CRYPTO_KEYTABLE_DATA_REG) = 0;
 	}
 }
 
 int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input)
 {
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTAB);
+	SE(SE_CONFIG_REG)        = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTABLE);
-	SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
-	SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
+	SE(SE_CRYPTO_BLOCK_COUNT_REG)  = 1 - 1;
-	SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst);
+	SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst) | SE_KEYTABLE_DST_WORD_QUAD(KEYS_0_3);
 
-	return _se_execute(OP_START, NULL, 0, input, 0x10);
+	return _se_execute_oneshot(SE_OP_START, NULL, 0, input, SE_KEY_128_SIZE);
 }
 
 int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
 {
 	if (enc)
 	{
-		SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
+		SE(SE_CONFIG_REG)        = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
-		SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
+		SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
 	}
 	else
 	{
-		SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
+		SE(SE_CONFIG_REG)        = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
-		SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
+		SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
 	}
-	SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1;
-	return _se_execute(OP_START, dst, dst_size, src, src_size);
+	return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size);
+}
+
+int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
+{
+	if (enc)
+	{
+		SE(SE_CONFIG_REG)        = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
+		SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) |
+			SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP);
+	}
+	else
+	{
+		SE(SE_CONFIG_REG)        = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
+		SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) |
+			SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM);
+	}
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1;
+	return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size);
 }
 
 int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src)
 {
-	return se_aes_crypt_ecb(ks, enc, dst, 0x10, src, 0x10);
+	return se_aes_crypt_ecb(ks, enc, dst, SE_AES_BLOCK_SIZE, src, SE_AES_BLOCK_SIZE);
 }
 
-int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr)
+int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, const void *ctr)
 {
-	SE(SE_SPARE_0_REG_OFFSET) = 1;
+	SE(SE_SPARE_REG)         = SE_ECO(SE_ERRATA_FIX_ENABLE);
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
+	SE(SE_CONFIG_REG)        = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
-	SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
-		SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | SE_CRYPTO_CTR_VAL(1) |
+		SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | SE_CRYPTO_CTR_CNTN(1);
-		SE_CRYPTO_VCTRAM_SEL(VCTRAM_AHB);
 	_se_aes_ctr_set(ctr);
 
-	u32 src_size_aligned = src_size & 0xFFFFFFF0;
+	u32 src_size_aligned = ALIGN_DOWN(src_size, 0x10);
 	u32 src_size_delta = src_size & 0xF;
 
 	if (src_size_aligned)
 	{
-		SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
+		SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1;
-		if (!_se_execute(OP_START, dst, dst_size, src, src_size_aligned))
+		if (!_se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size_aligned))
 			return 0;
 	}
 
 	if (src_size - src_size_aligned && src_size_aligned < dst_size)
-		return _se_execute_one_block(OP_START, dst + src_size_aligned,
+		return _se_execute_one_block(SE_OP_START, dst + src_size_aligned,
 			MIN(src_size_delta, dst_size - src_size_aligned),
 			src + src_size_aligned, src_size_delta);
 
@@ -351,15 +419,15 @@ int se_initialize_rng()
 
 	u8 *output_buf = (u8 *)malloc(0x10);
 
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
-	SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
-	SE(SE_RNG_CONFIG_REG_OFFSET) = SE_RNG_CONFIG_MODE(RNG_MODE_FORCE_INSTANTION) | SE_RNG_CONFIG_SRC(RNG_SRC_ENTROPY);
+	SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_MODE(MODE_FORCE_INSTANTION) | SE_RNG_CONFIG_SRC(SRC_ENTROPY);
-	SE(SE_RNG_RESEED_INTERVAL_REG_OFFSET) = 70001;
+	SE(SE_RNG_RESEED_INTERVAL_REG) = 70001;
-	SE(SE_RNG_SRC_CONFIG_REG_OFFSET) = SE_RNG_SRC_CONFIG_ENT_SRC(RNG_SRC_RO_ENT_ENABLE) |
+	SE(SE_RNG_SRC_CONFIG_REG) = SE_RNG_SRC_CONFIG_ENTR_SRC(RO_ENTR_ENABLE) |
-		SE_RNG_SRC_CONFIG_ENT_SRC_LOCK(RNG_SRC_RO_ENT_LOCK_ENABLE);
+		SE_RNG_SRC_CONFIG_ENTR_SRC_LOCK(RO_ENTR_LOCK_ENABLE);
-	SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = 0;
 
-	int res =_se_execute(OP_START, output_buf, 0x10, NULL, 0);
+	int res =_se_execute_oneshot(SE_OP_START, output_buf, 0x10, NULL, 0);
 
 	free(output_buf);
 	if (res)
@@ -369,60 +437,40 @@ int se_initialize_rng()
 
 int se_generate_random(void *dst, u32 size)
 {
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
-	SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
-	SE(SE_RNG_CONFIG_REG_OFFSET) = SE_RNG_CONFIG_MODE(RNG_MODE_NORMAL) | SE_RNG_CONFIG_SRC(RNG_SRC_ENTROPY);
+	SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_MODE(MODE_NORMAL) | SE_RNG_CONFIG_SRC(SRC_ENTROPY);
 
 	u32 num_blocks = size >> 4;
 	u32 aligned_size = num_blocks << 4;
 	if (num_blocks)
 	{
-		SE(SE_BLOCK_COUNT_REG_OFFSET) = num_blocks - 1;
+		SE(SE_CRYPTO_BLOCK_COUNT_REG) = num_blocks - 1;
-		if (!_se_execute(OP_START, dst, aligned_size, NULL, 0))
+		if (!_se_execute_oneshot(SE_OP_START, dst, aligned_size, NULL, 0))
 			return 0;
 	}
 	if (size > aligned_size)
-		return _se_execute_one_block(OP_START, dst + aligned_size, size - aligned_size, NULL, 0);
+		return _se_execute_one_block(SE_OP_START, dst + aligned_size, size - aligned_size, NULL, 0);
 	return 1;
 }
 
 int se_generate_random_key(u32 ks_dst, u32 ks_src)
 {
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
-	SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
 		SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
-	SE(SE_RNG_CONFIG_REG_OFFSET) = SE_RNG_CONFIG_MODE(RNG_MODE_NORMAL) | SE_RNG_CONFIG_SRC(RNG_SRC_ENTROPY);
+	SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_MODE(MODE_NORMAL) | SE_RNG_CONFIG_SRC(SRC_ENTROPY);
 
-	SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst);
+	SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst);
-	if (!_se_execute(OP_START, NULL, 0, NULL, 0))
+	if (!_se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0))
 		return 0;
-	SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst) | 1;
+	SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst) | 1;
-	if (!_se_execute(OP_START, NULL, 0, NULL, 0))
+	if (!_se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0))
 		return 0;
 
 	return 1;
 }
 
-int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
-{
-	if (enc)
-	{
-		SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
-		SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) |
-			SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP) | SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
-			SE_CRYPTO_IV_SEL(IV_ORIGINAL);
-	}
-	else
-	{
-		SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
-		SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVAHB) |
-			SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
-			SE_CRYPTO_IV_SEL(IV_ORIGINAL);
-	}
-	SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
-	return _se_execute(OP_START, dst, dst_size, src, src_size);
-}
-
 int se_aes_xts_crypt_sec(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, const void *src, u32 sec_size)
 {
 	u8 tweak[0x10];
@@ -437,7 +485,7 @@ int se_aes_xts_crypt_sec(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst
 		tweak[i] = sec & 0xFF;
 		sec >>= 8;
 	}
-	if (!se_aes_crypt_block_ecb(tweak_ks, 1, tweak, tweak))
+	if (!se_aes_crypt_block_ecb(tweak_ks, ENCRYPT, tweak, tweak))
 		return 0;
 
 	memcpy(orig_tweak, tweak, 0x10);
@@ -490,25 +538,25 @@ int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
 	u8 *last_block = (u8 *)calloc(0x10, 1);
 
 	// generate derived key
-	if (!se_aes_crypt_block_ecb(ks, 1, key, key))
+	if (!se_aes_crypt_block_ecb(ks, ENCRYPT, key, key))
 		goto out;
 	_gf256_mul_x(key);
 	if (src_size & 0xF)
 		_gf256_mul_x(key);
 
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_HASHREG);
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_HASHREG);
-	SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_INPUT_SEL(INPUT_MEMORY) |
 		SE_CRYPTO_XOR_POS(XOR_TOP) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | SE_CRYPTO_HASH(HASH_ENABLE) |
 		SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
-	se_aes_key_iv_clear(ks);
+	se_aes_iv_clear(ks);
 
 	u32 num_blocks = (src_size + 0xf) >> 4;
 	if (num_blocks > 1)
 	{
-		SE(SE_BLOCK_COUNT_REG_OFFSET) = num_blocks - 2;
+		SE(SE_CRYPTO_BLOCK_COUNT_REG) = num_blocks - 2;
-		if (!_se_execute(OP_START, NULL, 0, src, src_size))
+		if (!_se_execute_oneshot(SE_OP_START, NULL, 0, src, src_size))
 			goto out;
-		SE(SE_CRYPTO_REG_OFFSET) |= SE_CRYPTO_IV_SEL(IV_UPDATED);
+		SE(SE_CRYPTO_CONFIG_REG) |= SE_CRYPTO_IV_SEL(IV_UPDATED);
 	}
 
 	if (src_size & 0xf)
@@ -524,12 +572,12 @@ int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
 	for (u32 i = 0; i < 0x10; i++)
 		last_block[i] ^= key[i];
 
-	SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = 0;
-	res = _se_execute(OP_START, NULL, 0, last_block, 0x10);
+	res = _se_execute_oneshot(SE_OP_START, NULL, 0, last_block, 0x10);
 
 	u32 *dst32 = (u32 *)dst;
 	for (u32 i = 0; i < (dst_size >> 2); i++)
-		dst32[i] = SE(SE_HASH_RESULT_REG_OFFSET + (i << 2));
+		dst32[i] = SE(SE_HASH_RESULT_REG + (i << 2));
 
 out:;
 	free(key);
@@ -537,29 +585,91 @@ out:;
 	return res;
 }
 
-// se_calc_sha256() was derived from Atmosphère's se_calculate_sha256.
+int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 total_size, u32 sha_cfg, bool is_oneshot)
-int se_calc_sha256(void *dst, const void *src, u32 src_size)
 {
 	int res;
-	// Setup config for SHA256, size = BITS(src_size).
+	u32 hash32[SE_SHA_256_SIZE / 4];
-	SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_MODE(MODE_SHA256) | SE_CONFIG_ENC_ALG(ALG_SHA) | SE_CONFIG_DST(DST_HASHREG);
+
-	SE(SE_SHA_CONFIG_REG_OFFSET) = SHA_INIT_HASH;
+	//! TODO: src_size must be 512 bit aligned if continuing and not last block for SHA256.
-	SE(SE_SHA_MSG_LENGTH_0_REG_OFFSET) = (u32)(src_size << 3);
+	if (src_size > 0xFFFFFF || !hash) // Max 16MB - 1 chunks and aligned x4 hash buffer.
-	SE(SE_SHA_MSG_LENGTH_1_REG_OFFSET) = 0;
+		return 0;
-	SE(SE_SHA_MSG_LENGTH_2_REG_OFFSET) = 0;
+
-	SE(SE_SHA_MSG_LENGTH_3_REG_OFFSET) = 0;
+	// Setup config for SHA256.
-	SE(SE_SHA_MSG_LEFT_0_REG_OFFSET) = (u32)(src_size << 3);
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_SHA256) | SE_CONFIG_ENC_ALG(ALG_SHA) | SE_CONFIG_DST(DST_HASHREG);
-	SE(SE_SHA_MSG_LEFT_1_REG_OFFSET) = 0;
+	SE(SE_SHA_CONFIG_REG) = sha_cfg;
-	SE(SE_SHA_MSG_LEFT_2_REG_OFFSET) = 0;
+	SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1;
-	SE(SE_SHA_MSG_LEFT_3_REG_OFFSET) = 0;
+
+	// Set total size to current buffer size if empty.
+	if (!total_size)
+		total_size = src_size;
+
+	// Set total size: BITS(src_size), up to 2 EB.
+	SE(SE_SHA_MSG_LENGTH_0_REG) = (u32)(total_size << 3);
+	SE(SE_SHA_MSG_LENGTH_1_REG) = (u32)(total_size >> 29);
+	SE(SE_SHA_MSG_LENGTH_2_REG) = 0;
+	SE(SE_SHA_MSG_LENGTH_3_REG) = 0;
+
+	// Set size left to hash.
+	SE(SE_SHA_MSG_LEFT_0_REG) = (u32)(total_size << 3);
+	SE(SE_SHA_MSG_LEFT_1_REG) = (u32)(total_size >> 29);
+	SE(SE_SHA_MSG_LEFT_2_REG) = 0;
+	SE(SE_SHA_MSG_LEFT_3_REG) = 0;
+
+	// If we hash in chunks, copy over the intermediate.
+	if (sha_cfg == SHA_CONTINUE && msg_left)
+	{
+		// Restore message left to process.
+		SE(SE_SHA_MSG_LEFT_0_REG) = msg_left[0];
+		SE(SE_SHA_MSG_LEFT_1_REG) = msg_left[1];
+
+		// Restore hash reg.
+		memcpy(hash32, hash, SE_SHA_256_SIZE);
+		for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
+			SE(SE_HASH_RESULT_REG + (i * 4)) = byte_swap_32(hash32[i]);
+	}
 
 	// Trigger the operation.
-	res = _se_execute(OP_START, NULL, 0, src, src_size);
+	res = _se_execute(SE_OP_START, NULL, 0, src, src_size, is_oneshot);
+
+	if (is_oneshot)
+	{
+		// Backup message left.
+		if (msg_left)
+		{
+			msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG);
+			msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG);
+		}
 
 		// Copy output hash.
-	u32 *dst32 = (u32 *)dst;
+		for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
-	for (u32 i = 0; i < 8; i++)
+			hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4)));
-		dst32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG_OFFSET + (i << 2)));
+		memcpy(hash, hash32, SE_SHA_256_SIZE);
+	}
+
+	return res;
+}
+
+int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size)
+{
+	return se_calc_sha256(hash, NULL, src, src_size, 0, SHA_INIT_HASH, true);
+}
+
+int se_calc_sha256_finalize(void *hash, u32 *msg_left)
+{
+	u32 hash32[SE_SHA_256_SIZE / 4];
+	int res = _se_execute_finalize();
+
+	// Backup message left.
+	if (msg_left)
+	{
+		msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG);
+		msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG);
+	}
+
+	// Copy output hash.
+	for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
+		hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4)));
+	memcpy(hash, hash32, SE_SHA_256_SIZE);
 
 	return res;
 }
@@ -573,7 +683,7 @@ int se_calc_hmac_sha256(void *dst, const void *src, u32 src_size, const void *ke
 
 	if (key_size > 0x40)
 	{
-		if (!se_calc_sha256(secret, key, key_size))
+		if (!se_calc_sha256_oneshot(secret, key, key_size))
 			goto out;
 		memset(secret + 0x20, 0, 0x20);
 	}
@@ -593,10 +703,10 @@ int se_calc_hmac_sha256(void *dst, const void *src, u32 src_size, const void *ke
 	}
 
 	memcpy(ipad + 0x40, src, src_size);
-	if (!se_calc_sha256(dst, ipad, 0x40 + src_size))
+	if (!se_calc_sha256_oneshot(dst, ipad, 0x40 + src_size))
 		goto out;
 	memcpy(opad + 0x40, dst, 0x20);
-	if (!se_calc_sha256(dst, opad, 0x60))
+	if (!se_calc_sha256_oneshot(dst, opad, 0x60))
 		goto out;
 
 	res = 1;
@@ -608,73 +718,59 @@ out:;
 	return res;
 }
 
-// _mgf1_xor() and rsa_oaep_decode were derived from Atmosphère
+void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize)
-static void _mgf1_xor(void *masked, u32 masked_size, const void *seed, u32 seed_size)
 {
-    u8 cur_hash[0x20];
+	u8 *aligned_buf = (u8 *)ALIGN((u32)buf, 0x40);
-    u8 hash_buf[0xe4];
 
-    u32 hash_buf_size = seed_size + 4;
+	// Set Secure Random Key.
-    memcpy(hash_buf, seed, seed_size);
+	SE(SE_CONFIG_REG)        = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_SRK);
-    u32 round_num = 0;
+	SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(0) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
+	SE(SE_RNG_CONFIG_REG)    = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_FORCE_RESEED);
+	SE(SE_CRYPTO_LAST_BLOCK) = 0;
+	_se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0);
 
-    u8 *p_out = (u8 *)masked;
+	// Save AES keys.
+	SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
 
-    while (masked_size) {
+	for (u32 i = 0; i < SE_AES_KEYSLOT_COUNT; i++)
-        u32 cur_size = MIN(masked_size, 0x20);
-
-        for (u32 i = 0; i < 4; i++)
-            hash_buf[seed_size + 3 - i] = (round_num >> (8 * i)) & 0xff;
-        round_num++;
-
-        se_calc_sha256(cur_hash, hash_buf, hash_buf_size);
-
-        for (unsigned int i = 0; i < cur_size; i++) {
-            *p_out ^= cur_hash[i];
-            p_out++;
-        }
-
-        masked_size -= cur_size;
-    }
-}
-
-u32 se_rsa_oaep_decode(void *dst, u32 dst_size, const void *label_digest, u32 label_digest_size, u8 *buf, u32 buf_size)
 	{
-	if (dst_size <= 0 || buf_size < 0x43 || label_digest_size != 0x20)
+		SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) |
-		return 0;
+			SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_0_3);
 
-	bool is_valid = buf[0] == 0;
+		SE(SE_CRYPTO_LAST_BLOCK) = 0;
+		_se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0);
+		memcpy(keys + i * keysize, aligned_buf, SE_AES_BLOCK_SIZE);
 
-	u32 db_len = buf_size - 0x21;
+		if (keysize > SE_KEY_128_SIZE)
-	u8 *seed = buf + 1;
-	u8 *db = seed + 0x20;
-	_mgf1_xor(seed, 0x20, db, db_len);
-	_mgf1_xor(db, db_len, seed, 0x20);
-
-	is_valid &= memcmp(label_digest, db, 0x20) ? 0 : 1;
-
-	db += 0x20;
-	db_len -= 0x20;
-
-	int msg_ofs = 0;
-	int looking_for_one = 1;
-	int invalid_db_padding = 0;
-	int is_zero;
-	int is_one;
-	for (int i = 0; i < db_len; )
 		{
-		is_zero = (db[i] == 0);
+			SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) |
-		is_one  = (db[i] == 1);
+				SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_4_7);
-		msg_ofs += (looking_for_one & is_one) * (++i);
+
-		looking_for_one &= ~is_one;
+			SE(SE_CRYPTO_LAST_BLOCK) = 0;
-		invalid_db_padding |= (looking_for_one & ~is_zero);
+			_se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0);
+			memcpy(keys + i * keysize + SE_AES_BLOCK_SIZE, aligned_buf, SE_AES_BLOCK_SIZE);
+		}
 	}
 
-	is_valid &= (invalid_db_padding == 0);
+	// Save SRK to PMC secure scratches.
+	SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(SRK);
+	SE(SE_CRYPTO_LAST_BLOCK)       = 0;
+	_se_execute_oneshot(SE_OP_CTX_SAVE, NULL, 0, NULL, 0);
 
-	const u32 msg_size = MIN(dst_size, is_valid * (db_len - msg_ofs));
+	// End context save.
-	memcpy(dst, db + msg_ofs, msg_size);
+	SE(SE_CONFIG_REG) = 0;
+	_se_execute_oneshot(SE_OP_CTX_SAVE, NULL, 0, NULL, 0);
 
-	return msg_size;
+	// Get SRK.
+	u32 srk[4];
+	srk[0] = PMC(APBDEV_PMC_SECURE_SCRATCH4);
+	srk[1] = PMC(APBDEV_PMC_SECURE_SCRATCH5);
+	srk[2] = PMC(APBDEV_PMC_SECURE_SCRATCH6);
+	srk[3] = PMC(APBDEV_PMC_SECURE_SCRATCH7);
+
+	// Decrypt context.
+	se_aes_key_clear(3);
+	se_aes_key_set(3, srk, SE_KEY_128_SIZE);
+	se_aes_crypt_cbc(3, DECRYPT, keys, SE_AES_KEYSLOT_COUNT * keysize, keys, SE_AES_KEYSLOT_COUNT * keysize);
+	se_aes_key_clear(3);
 }
-

bdk/sec/se.h

@@ -1,5 +1,7 @@
 /*
 * Copyright (c) 2018 naehrwert
+* Copyright (c) 2019-2021 CTCaer
+* Copyright (c) 2019-2021 shchmue
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -25,23 +27,27 @@ void se_rsa_key_clear(u32 ks);
 int se_rsa_exp_mod(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size);
 void se_key_acc_ctrl(u32 ks, u32 flags);
 u32  se_key_acc_ctrl_get(u32 ks);
+void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize);
 void se_aes_key_set(u32 ks, const void *key, u32 size);
-void se_aes_iv_set(u32 ks, const void *iv, u32 size);
+void se_aes_iv_set(u32 ks, const void *iv);
-void se_aes_key_read(u32 ks, void *key, u32 size);
+void se_aes_key_partial_set(u32 ks, u32 index, u32 data);
+void se_aes_key_get(u32 ks, void *key, u32 size);
 void se_aes_key_clear(u32 ks);
+void se_aes_iv_clear(u32 ks);
 int se_initialize_rng();
 int se_generate_random(void *dst, u32 size);
 int se_generate_random_key(u32 ks_dst, u32 ks_src);
 int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input);
+int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
 int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
 int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src);
-int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr);
+int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, const void *ctr);
-int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
 int se_aes_xts_crypt_sec(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, const void *src, u32 sec_size);
 int se_aes_xts_crypt(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, const void *src, u32 sec_size, u32 num_secs);
 int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size);
-int se_calc_sha256(void *dst, const void *src, u32 src_size);
+int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 total_size, u32 sha_cfg, bool is_oneshot);
+int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size);
+int se_calc_sha256_finalize(void *hash, u32 *msg_left);
 int se_calc_hmac_sha256(void *dst, const void *src, u32 src_size, const void *key, u32 key_size);
-u32 se_rsa_oaep_decode(void *dst, u32 dst_size, const void *label_digest, u32 label_digest_size, u8 *buf, u32 buf_size);
 
 #endif

bdk/sec/se_t210.h

@@ -1,63 +1,102 @@
 /*
-* Driver for Tegra Security Engine
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2021 CTCaer
  *
-* Copyright (c) 2011-2013, NVIDIA Corporation. All Rights Reserved.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
  *
-* This program is free software; you can redistribute it and/or modify
+ * This program is distributed in the hope it will be useful, but WITHOUT
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
-* You should have received a copy of the GNU General Public License along
+ * You should have received a copy of the GNU General Public License
-* with this program; if not, write to the Free Software Foundation, Inc.,
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-* 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#ifndef _CRYPTO_TEGRA_SE_H
+#ifndef _SE_T210_H
-#define _CRYPTO_TEGRA_SE_H
+#define _SE_T210_H
 
 #include <utils/types.h>
 
-#define TEGRA_SE_CRA_PRIORITY	300
+#define SE_CRYPTO_QUEUE_LENGTH 50
-#define TEGRA_SE_COMPOSITE_PRIORITY 400
-#define TEGRA_SE_CRYPTO_QUEUE_LENGTH 50
 #define SE_MAX_SRC_SG_COUNT    50
 #define SE_MAX_DST_SG_COUNT    50
 
-#define TEGRA_SE_KEYSLOT_COUNT		16
+#define SE_AES_KEYSLOT_COUNT   16
+#define SE_RSA_KEYSLOT_COUNT   2
 #define SE_MAX_LAST_BLOCK_SIZE 0xFFFFF
 
+#define SE_AES_BLOCK_SIZE   16
+#define SE_AES_IV_SIZE      16
+#define SE_AES_MIN_KEY_SIZE 16
+#define SE_AES_MAX_KEY_SIZE 32
+#define SE_KEY_128_SIZE     16
+#define SE_KEY_192_SIZE     24
+#define SE_KEY_256_SIZE     32
+#define SE_SHA_192_SIZE     24
+#define SE_SHA_256_SIZE     32
+#define SE_SHA_384_SIZE     48
+#define SE_SHA_512_SIZE     64
+#define SE_RNG_IV_SIZE		16
+#define SE_RNG_DT_SIZE		16
+#define SE_RNG_KEY_SIZE		16
+#define SE_RNG_SEED_SIZE (SE_RNG_IV_SIZE + SE_RNG_KEY_SIZE + SE_RNG_DT_SIZE)
+
+#define SE_AES_CMAC_DIGEST_SIZE 16
+#define SE_RSA512_DIGEST_SIZE   64
+#define SE_RSA1024_DIGEST_SIZE  128
+#define SE_RSA1536_DIGEST_SIZE  192
+#define SE_RSA2048_DIGEST_SIZE  256
+
+#define  DECRYPT   0
+#define  ENCRYPT   1
+
 /* SE register definitions */
-#define SE_SECURITY_0 0x000
+#define SE_SE_SECURITY_REG 0x000
-#define SE_KEY_SCHED_READ_SHIFT 3
+#define  SE_HARD_SETTING   BIT(0)
+#define  SE_ENG_DIS        BIT(1)
+#define  SE_PERKEY_SETTING BIT(2)
+#define  SE_SOFT_SETTING   BIT(16)
 
-#define SE_TZRAM_SECURITY_0 0x004
+#define SE_TZRAM_SECURITY_REG 0x004
+#define  SE_TZRAM_HARD_SETTING BIT(0)
+#define  SE_TZRAM_ENG_DIS      BIT(1)
 
-#define SE_CONFIG_REG_OFFSET		0x014
+#define SE_OPERATION_REG 0x008
-#define SE_CONFIG_ENC_ALG_SHIFT		12
+#define  SE_OP_ABORT       0
-#define SE_CONFIG_DEC_ALG_SHIFT		8
+#define  SE_OP_START       1
+#define  SE_OP_RESTART_OUT 2
+#define  SE_OP_CTX_SAVE    3
+#define  SE_OP_RESTART_IN  4
+
+#define SE_INT_ENABLE_REG	0x00C
+#define SE_INT_STATUS_REG	0x010
+#define  SE_INT_IN_LL_BUF_RD  BIT(0)
+#define  SE_INT_IN_DONE       BIT(1)
+#define  SE_INT_OUT_LL_BUF_WR BIT(2)
+#define  SE_INT_OUT_DONE      BIT(3)
+#define  SE_INT_OP_DONE       BIT(4)
+#define  SE_INT_RESEED_NEEDED BIT(5)
+#define  SE_INT_ERR_STAT      BIT(16)
+
+#define SE_CONFIG_REG 0x014
+#define  DST_MEMORY      0
+#define  DST_HASHREG     1
+#define  DST_KEYTABLE    2
+#define  DST_SRK         3
+#define  DST_RSAREG      4
+#define  SE_CONFIG_DST(x)      ((x) << 2)
+#define  ALG_NOP         0
+#define  ALG_AES_DEC     1
+#define  SE_CONFIG_DEC_ALG(x)  ((x) << 8)
+#define  ALG_NOP         0
 #define  ALG_AES_ENC     1
 #define  ALG_RNG         2
 #define  ALG_SHA         3
 #define  ALG_RSA         4
-#define ALG_NOP			0
+#define  SE_CONFIG_ENC_ALG(x)  ((x) << 12)
-#define ALG_AES_DEC		1
-#define SE_CONFIG_ENC_ALG(x)		(x << SE_CONFIG_ENC_ALG_SHIFT)
-#define SE_CONFIG_DEC_ALG(x)		(x << SE_CONFIG_DEC_ALG_SHIFT)
-#define SE_CONFIG_DST_SHIFT			2
-#define DST_MEMORY		0
-#define DST_HASHREG		1
-#define DST_KEYTAB		2
-#define DST_SRK			3
-#define DST_RSAREG		4
-#define SE_CONFIG_DST(x)			(x << SE_CONFIG_DST_SHIFT)
-#define SE_CONFIG_ENC_MODE_SHIFT	24
-#define SE_CONFIG_DEC_MODE_SHIFT	16
 #define  MODE_KEY128     0
 #define  MODE_KEY192     1
 #define  MODE_KEY256     2
@@ -66,326 +105,222 @@
 #define  MODE_SHA256     5
 #define  MODE_SHA384     6
 #define  MODE_SHA512     7
-#define SE_CONFIG_ENC_MODE(x)		(x << SE_CONFIG_ENC_MODE_SHIFT)
+#define  SE_CONFIG_DEC_MODE(x) ((x) << 16)
-#define SE_CONFIG_DEC_MODE(x)		(x << SE_CONFIG_DEC_MODE_SHIFT)
+#define  SE_CONFIG_ENC_MODE(x) ((x) << 24)
 
-#define SE_RNG_CONFIG_REG_OFFSET		0x340
+#define SE_IN_LL_ADDR_REG        0x018
-#define RNG_MODE_SHIFT	0
+#define SE_IN_CUR_BYTE_ADDR_REG  0x01C
-#define RNG_MODE_NORMAL	0
+#define SE_IN_CUR_LL_ID_REG      0x020
-#define RNG_MODE_FORCE_INSTANTION	1
+#define SE_OUT_LL_ADDR_REG       0x024
-#define RNG_MODE_FORCE_RESEED		2
+#define SE_OUT_CUR_BYTE_ADDR_REG 0x028
-#define SE_RNG_CONFIG_MODE(x)		(x << RNG_MODE_SHIFT)
+#define SE_OUT_CUR_LL_ID_REG     0x02C
-#define RNG_SRC_SHIFT	2
-#define RNG_SRC_NONE	0
-#define RNG_SRC_ENTROPY	1
-#define RNG_SRC_LFSR	2
-#define SE_RNG_CONFIG_SRC(x)		(x << RNG_SRC_SHIFT)
 
-#define SE_RNG_SRC_CONFIG_REG_OFFSET	0x344
+#define SE_HASH_RESULT_REG 0x030
-#define RNG_SRC_RO_ENT_SHIFT	1
+#define  SE_HASH_RESULT_REG_COUNT 16
-#define RNG_SRC_RO_ENT_ENABLE	1
-#define RNG_SRC_RO_ENT_DISABLE	0
-#define SE_RNG_SRC_CONFIG_ENT_SRC(x)	(x << RNG_SRC_RO_ENT_SHIFT)
-#define RNG_SRC_RO_ENT_LOCK_SHIFT	 0
-#define RNG_SRC_RO_ENT_LOCK_ENABLE	 1
-#define RNG_SRC_RO_ENT_LOCK_DISABLE 0
-#define SE_RNG_SRC_CONFIG_ENT_SRC_LOCK(x) (x << RNG_SRC_RO_ENT_LOCK_SHIFT)
 
-#define SE_RNG_RESEED_INTERVAL_REG_OFFSET		0x348
+#define SE_CONTEXT_SAVE_CONFIG_REG 0x070
+#define  KEYS_0_3        0
+#define  KEYS_4_7        1
+#define  ORIGINAL_IV     2
+#define  UPDATED_IV      3
+#define  SE_CONTEXT_AES_WORD_QUAD(x)    ((x) << 0)
+#define  SE_CONTEXT_AES_KEY_INDEX(x)    ((x) << 8)
+#define  KEYS_0_3        0
+#define  KEYS_4_7        1
+#define  KEYS_8_11       2
+#define  KEYS_12_15      3
+#define  SE_CONTEXT_RSA_WORD_QUAD(x)    ((x) << 12)
+#define  SLOT0_EXPONENT  0
+#define  SLOT0_MODULUS   1
+#define  SLOT1_EXPONENT  2
+#define  SLOT1_MODULUS   3
+#define  SE_CONTEXT_RSA_KEY_INDEX(x)    ((x) << 16)
+#define  STICKY_0_3      0
+#define  STICKY_4_7      1
+#define  SE_CONTEXT_STICKY_WORD_QUAD(x) ((x) << 24)
+#define  STICKY_BITS     0
+#define  RSA_KEYTABLE    1
+#define  AES_KEYTABLE    2
+#define  MEM             4
+#define  SRK             6
+#define SE_CONTEXT_SRC(x)               ((x) << 29)
 
-#define SE_KEYTABLE_REG_OFFSET		0x31c
+#define SE_CTX_SAVE_AUTO_T210B01_REG 0x074
-#define SE_KEYTABLE_SLOT_SHIFT		4
+#define  SE_CTX_SAVE_AUTO_ENABLE		BIT(0)
-#define SE_KEYTABLE_SLOT(x)			(x << SE_KEYTABLE_SLOT_SHIFT)
+#define  SE_CTX_SAVE_AUTO_LOCK          BIT(8)
-#define SE_KEYTABLE_QUAD_SHIFT		2
+#define  SE_CTX_SAVE_AUTO_CURR_CNT_MASK (0x3FF << 16)
-#define QUAD_KEYS_128	0
-#define QUAD_KEYS_192	1
-#define QUAD_KEYS_256	1
-#define QUAD_ORG_IV		2
-#define QUAD_UPDTD_IV	3
-#define SE_KEYTABLE_QUAD(x)			(x << SE_KEYTABLE_QUAD_SHIFT)
-#define SE_KEYTABLE_OP_TYPE_SHIFT	9
-#define OP_READ			0
-#define OP_WRITE		1
-#define SE_KEYTABLE_OP_TYPE(x)		(x << SE_KEYTABLE_OP_TYPE_SHIFT)
-#define SE_KEYTABLE_TABLE_SEL_SHIFT		8
-#define TABLE_KEYIV		0
-#define TABLE_SCHEDULE	1
-#define SE_KEYTABLE_TABLE_SEL(x)	(x << SE_KEYTABLE_TABLE_SEL_SHIFT)
-#define SE_KEYTABLE_PKT_SHIFT		0
-#define SE_KEYTABLE_PKT(x)			(x << SE_KEYTABLE_PKT_SHIFT)
-
-#define SE_OP_DONE_SHIFT	4
-#define OP_DONE	1
-#define SE_OP_DONE(x, y)	((x) && (y << SE_OP_DONE_SHIFT))
 
 #define SE_CRYPTO_LAST_BLOCK 0x080
 
-#define SE_CRYPTO_REG_OFFSET		0x304
+#define SE_SHA_CONFIG_REG 0x200
-#define SE_CRYPTO_HASH_SHIFT		0
-#define HASH_DISABLE	0
-#define HASH_ENABLE		1
-#define SE_CRYPTO_HASH(x)			(x << SE_CRYPTO_HASH_SHIFT)
-#define SE_CRYPTO_XOR_POS_SHIFT		1
-#define XOR_BYPASS		0
-#define XOR_TOP			2
-#define XOR_BOTTOM		3
-#define SE_CRYPTO_XOR_POS(x)		(x << SE_CRYPTO_XOR_POS_SHIFT)
-#define SE_CRYPTO_INPUT_SEL_SHIFT	3
-#define INPUT_AHB		0
-#define INPUT_RANDOM	1
-#define INPUT_AESOUT	2
-#define INPUT_LNR_CTR	3
-#define SE_CRYPTO_INPUT_SEL(x)		(x << SE_CRYPTO_INPUT_SEL_SHIFT)
-#define SE_CRYPTO_VCTRAM_SEL_SHIFT	5
-#define VCTRAM_AHB		0
-#define VCTRAM_AESOUT	2
-#define VCTRAM_PREVAHB	3
-#define SE_CRYPTO_VCTRAM_SEL(x)		(x << SE_CRYPTO_VCTRAM_SEL_SHIFT)
-#define SE_CRYPTO_IV_SEL_SHIFT		7
-#define IV_ORIGINAL		0
-#define IV_UPDATED		1
-#define SE_CRYPTO_IV_SEL(x)			(x << SE_CRYPTO_IV_SEL_SHIFT)
-#define SE_CRYPTO_CORE_SEL_SHIFT	8
-#define CORE_DECRYPT	0
-#define CORE_ENCRYPT	1
-#define SE_CRYPTO_CORE_SEL(x)		(x << SE_CRYPTO_CORE_SEL_SHIFT)
-#define SE_CRYPTO_CTR_VAL_SHIFT		11
-#define SE_CRYPTO_CTR_VAL(x)		(x << SE_CRYPTO_CTR_VAL_SHIFT)
-#define SE_CRYPTO_KEY_INDEX_SHIFT	24
-#define SE_CRYPTO_KEY_INDEX(x)		(x << SE_CRYPTO_KEY_INDEX_SHIFT)
-#define SE_CRYPTO_CTR_CNTN_SHIFT	11
-#define SE_CRYPTO_CTR_CNTN(x)		(x << SE_CRYPTO_CTR_CNTN_SHIFT)
-
-#define SE_CRYPTO_CTR_REG_COUNT		4
-#define SE_CRYPTO_CTR_REG_OFFSET	0x308
-
-#define SE_OPERATION_REG_OFFSET		0x008
-#define SE_OPERATION_SHIFT			0
-#define OP_ABORT		0
-#define OP_START		1
-#define OP_RESTART		2
-#define OP_CTX_SAVE		3
-#define OP_RESTART_IN	4
-#define SE_OPERATION(x)				(x << SE_OPERATION_SHIFT)
-
-#define SE_CONTEXT_SAVE_CONFIG_REG_OFFSET		0x070
-#define SE_CONTEXT_SAVE_WORD_QUAD_SHIFT		0
-#define KEYS_0_3		0
-#define KEYS_4_7		1
-#define ORIG_IV		2
-#define UPD_IV		3
-#define SE_CONTEXT_SAVE_WORD_QUAD(x)	(x << SE_CONTEXT_SAVE_WORD_QUAD_SHIFT)
-
-#define SE_CONTEXT_SAVE_KEY_INDEX_SHIFT		8
-#define SE_CONTEXT_SAVE_KEY_INDEX(x)	(x << SE_CONTEXT_SAVE_KEY_INDEX_SHIFT)
-
-#define SE_CONTEXT_SAVAE_STICKY_WORD_QUAD_SHIFT	24
-#define STICKY_0_3		0
-#define STICKY_4_7		1
-#define SE_CONTEXT_SAVE_STICKY_WORD_QUAD(x)		\
-		(x << SE_CONTEXT_SAVAE_STICKY_WORD_QUAD_SHIFT)
-
-#define SE_CONTEXT_SAVE_SRC_SHIFT		29
-#define STICKY_BITS		0
-#define KEYTABLE		2
-#define MEM		4
-#define SRK		6
-
-#define RSA_KEYTABLE	1
-#define AES_KEYTABLE	2
-#define SE_CONTEXT_SAVE_SRC(x)		(x << SE_CONTEXT_SAVE_SRC_SHIFT)
-
-#define SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT	16
-#define SE_CONTEXT_SAVE_RSA_KEY_INDEX(x)		\
-		(x << SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT)
-
-#define SE_CONTEXT_RSA_WORD_QUAD_SHIFT	12
-#define SE_CONTEXT_RSA_WORD_QUAD(x)		\
-		(x << SE_CONTEXT_RSA_WORD_QUAD_SHIFT)
-
-#define SE_INT_ENABLE_REG_OFFSET	0x00c
-#define SE_INT_STATUS_REG_OFFSET	0x010
-#define INT_DISABLE		0
-#define INT_ENABLE		1
-#define INT_UNSET		0
-#define INT_SET			1
-#define SE_INT_OP_DONE_SHIFT		4
-#define SE_INT_OP_DONE(x)			(x << SE_INT_OP_DONE_SHIFT)
-#define SE_INT_ERROR_SHIFT		16
-#define SE_INT_ERROR(x)			(x << SE_INT_ERROR_SHIFT)
-
-#define SE_STATUS_0 0x800
-#define SE_STATUS_0_STATE_WAIT_IN 3
-
-#define SE_ERR_STATUS_0			0x804
-#define SE_ERR_STATUS_0_SE_NS_ACCESS_CLEAR 0
-
-#define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET	0X330
-#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT		0
-#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x)		\
-		(x << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT)
-
-#define SE_KEY_INDEX_SHIFT		8
-#define SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(x)	(x << SE_KEY_INDEX_SHIFT)
-
-#define SE_IN_LL_ADDR_REG_OFFSET	0x018
-#define SE_OUT_LL_ADDR_REG_OFFSET	0x024
-
-#define SE_KEYTABLE_DATA0_REG_OFFSET	0x320
-#define SE_KEYTABLE_REG_MAX_DATA		16
-
-#define SE_BLOCK_COUNT_REG_OFFSET	0x318
-
-#define SE_SPARE_0_REG_OFFSET		0x80c
-
-#define SE_SHA_CONFIG_REG_OFFSET	0x200
 #define  SHA_CONTINUE  0
 #define  SHA_INIT_HASH 1
 
-#define SE_SHA_MSG_LENGTH_0_REG_OFFSET	0x204
+#define SE_SHA_MSG_LENGTH_0_REG 0x204
-#define SE_SHA_MSG_LENGTH_1_REG_OFFSET	0x208
+#define SE_SHA_MSG_LENGTH_1_REG 0x208
-#define SE_SHA_MSG_LENGTH_2_REG_OFFSET	0x20C
+#define SE_SHA_MSG_LENGTH_2_REG 0x20C
-#define SE_SHA_MSG_LENGTH_3_REG_OFFSET	0x210
+#define SE_SHA_MSG_LENGTH_3_REG 0x210
-#define SE_SHA_MSG_LEFT_0_REG_OFFSET	0x214
+#define SE_SHA_MSG_LEFT_0_REG   0x214
-#define SE_SHA_MSG_LEFT_1_REG_OFFSET	0x218
+#define SE_SHA_MSG_LEFT_1_REG   0x218
-#define SE_SHA_MSG_LEFT_2_REG_OFFSET	0x21C
+#define SE_SHA_MSG_LEFT_2_REG   0x21C
-#define SE_SHA_MSG_LEFT_3_REG_OFFSET	0x220
+#define SE_SHA_MSG_LEFT_3_REG   0x220
 
-#define SE_HASH_RESULT_REG_COUNT	16
+#define SE_CRYPTO_SECURITY_PERKEY_REG 0x280
-#define SE_HASH_RESULT_REG_OFFSET	0x030
+#define  SE_KEY_LOCK_FLAG   0x80
-#define TEGRA_SE_KEY_256_SIZE		32
+#define SE_CRYPTO_KEYTABLE_ACCESS_REG 0x284
-#define TEGRA_SE_KEY_192_SIZE		24
+#define  SE_CRYPTO_KEYTABLE_ACCESS_REG_COUNT 16
-#define TEGRA_SE_KEY_128_SIZE		16
+#define  SE_KEY_TBL_DIS_KEYREAD_FLAG    BIT(0)
-#define TEGRA_SE_AES_BLOCK_SIZE		16
+#define  SE_KEY_TBL_DIS_KEYUPDATE_FLAG  BIT(1)
-#define TEGRA_SE_AES_MIN_KEY_SIZE	16
+#define  SE_KEY_TBL_DIS_OIVREAD_FLAG    BIT(2)
-#define TEGRA_SE_AES_MAX_KEY_SIZE	32
+#define  SE_KEY_TBL_DIS_OIVUPDATE_FLAG  BIT(3)
-#define TEGRA_SE_AES_IV_SIZE		16
+#define  SE_KEY_TBL_DIS_UIVREAD_FLAG    BIT(4)
-#define TEGRA_SE_RNG_IV_SIZE		16
+#define  SE_KEY_TBL_DIS_UIVUPDATE_FLAG  BIT(5)
-#define TEGRA_SE_RNG_DT_SIZE		16
+#define  SE_KEY_TBL_DIS_KEYUSE_FLAG     BIT(6)
-#define TEGRA_SE_RNG_KEY_SIZE		16
-#define TEGRA_SE_RNG_SEED_SIZE		(TEGRA_SE_RNG_IV_SIZE + \
-						TEGRA_SE_RNG_KEY_SIZE + \
-						TEGRA_SE_RNG_DT_SIZE)
-
-#define TEGRA_SE_AES_CMAC_DIGEST_SIZE	16
-#define TEGRA_SE_RSA512_DIGEST_SIZE	    64
-#define TEGRA_SE_RSA1024_DIGEST_SIZE	128
-#define TEGRA_SE_RSA1536_DIGEST_SIZE	192
-#define TEGRA_SE_RSA2048_DIGEST_SIZE	256
-
-#define SE_KEY_TABLE_ACCESS_LOCK_OFFSET	0x280
-#define SE_KEY_TBL_DIS_KEY_LOCK_FLAG 0x80
-
-#define SE_KEY_TABLE_ACCESS_REG_OFFSET	0x284
-#define SE_KEY_TBL_DIS_KEYREAD_FLAG    (1 << 0)
-#define SE_KEY_TBL_DIS_KEYUPDATE_FLAG  (1 << 1)
-#define SE_KEY_TBL_DIS_OIVREAD_FLAG    (1 << 2)
-#define SE_KEY_TBL_DIS_OIVUPDATE_FLAG  (1 << 3)
-#define SE_KEY_TBL_DIS_UIVREAD_FLAG    (1 << 4)
-#define SE_KEY_TBL_DIS_UIVUPDATE_FLAG  (1 << 5)
-#define SE_KEY_TBL_DIS_KEYUSE_FLAG     (1 << 6)
 #define  SE_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
 
-#define SE_KEY_READ_DISABLE_SHIFT		0
+#define SE_CRYPTO_CONFIG_REG 0x304
-#define SE_KEY_UPDATE_DISABLE_SHIFT		1
+#define  HASH_DISABLE   0
+#define  HASH_ENABLE    1
+#define  SE_CRYPTO_HASH(x)          ((x) << 0)
+#define  XOR_BYPASS     0
+#define  XOR_TOP        2
+#define  XOR_BOTTOM     3
+#define  SE_CRYPTO_XOR_POS(x)       ((x) << 1)
+#define  INPUT_MEMORY   0
+#define  INPUT_RANDOM   1
+#define  INPUT_AESOUT   2
+#define  INPUT_LNR_CTR  3
+#define  SE_CRYPTO_INPUT_SEL(x)     ((x) << 3)
+#define  VCTRAM_MEM     0
+#define  VCTRAM_AESOUT  2
+#define  VCTRAM_PREVMEM 3
+#define  SE_CRYPTO_VCTRAM_SEL(x)    ((x) << 5)
+#define  IV_ORIGINAL    0
+#define  IV_UPDATED     1
+#define  SE_CRYPTO_IV_SEL(x)        ((x) << 7)
+#define  CORE_DECRYPT   0
+#define  CORE_ENCRYPT   1
+#define  SE_CRYPTO_CORE_SEL(x)      ((x) << 8)
+#define  SE_CRYPTO_KEYSCH_BYPASS BIT(10)
+#define  SE_CRYPTO_CTR_CNTN(x)      ((x) << 11)
+#define  SE_CRYPTO_KEY_INDEX(x)     ((x) << 24)
+#define  MEMIF_AHB      0
+#define  MEMIF_MCCIF    1
+#define  SE_CRYPTO_MEMIF(x)         ((x) << 31)
 
-#define SE_CONTEXT_BUFER_SIZE	1072
+#define SE_CRYPTO_LINEAR_CTR_REG 0x308
-#define SE_CONTEXT_DRBG_BUFER_SIZE	2112
+#define  SE_CRYPTO_LINEAR_CTR_REG_COUNT 4
 
-#define SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET	0
+#define SE_CRYPTO_BLOCK_COUNT_REG 0x318
-#define SE_CONTEXT_SAVE_RANDOM_DATA_SIZE	16
-#define SE_CONTEXT_SAVE_STICKY_BITS_OFFSET	\
-	(SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET + SE_CONTEXT_SAVE_RANDOM_DATA_SIZE)
-#define SE_CONTEXT_SAVE_STICKY_BITS_SIZE	16
 
-#define SE_CONTEXT_SAVE_KEYS_OFFSET	(SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
+#define SE_CRYPTO_KEYTABLE_ADDR_REG 0x31C
-					SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
+#define  SE_KEYTABLE_PKT(x)         ((x) << 0)
-#define SE11_CONTEXT_SAVE_KEYS_OFFSET	(SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
+#define  KEYS_0_3        0
-					SE_CONTEXT_SAVE_STICKY_BITS_SIZE + \
+#define  KEYS_4_7        1
-					SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
+#define  ORIGINAL_IV     2
+#define  UPDATED_IV      3
+#define  SE_KEYTABLE_QUAD(x)        ((x) << 2)
+#define  SE_KEYTABLE_SLOT(x)        ((x) << 4)
 
-#define SE_CONTEXT_SAVE_KEY_LENGTH	512
+#define SE_CRYPTO_KEYTABLE_DATA_REG 0x320
-#define SE_CONTEXT_ORIGINAL_IV_OFFSET	(SE_CONTEXT_SAVE_KEYS_OFFSET + \
-			SE_CONTEXT_SAVE_KEY_LENGTH)
-#define SE11_CONTEXT_ORIGINAL_IV_OFFSET	(SE11_CONTEXT_SAVE_KEYS_OFFSET + \
-			SE_CONTEXT_SAVE_KEY_LENGTH)
 
-#define SE_CONTEXT_ORIGINAL_IV_LENGTH	256
+#define SE_CRYPTO_KEYTABLE_DST_REG 0x330
+#define  KEYS_0_3        0
+#define  KEYS_4_7        1
+#define  ORIGINAL_IV     2
+#define  UPDATED_IV      3
+#define  SE_KEYTABLE_DST_WORD_QUAD(x) ((x) << 0)
+#define  SE_KEYTABLE_DST_KEY_INDEX(x) ((x) << 8)
 
-#define SE_CONTEXT_UPDATED_IV_OFFSET	(SE_CONTEXT_ORIGINAL_IV_OFFSET + \
+#define SE_RNG_CONFIG_REG 0x340
-			SE_CONTEXT_ORIGINAL_IV_LENGTH)
+#define  MODE_NORMAL 0
-#define SE11_CONTEXT_UPDATED_IV_OFFSET	(SE11_CONTEXT_ORIGINAL_IV_OFFSET + \
+#define  MODE_FORCE_INSTANTION 1
-			SE_CONTEXT_ORIGINAL_IV_LENGTH)
+#define  MODE_FORCE_RESEED     2
+#define  SE_RNG_CONFIG_MODE(x)        ((x) << 0)
+#define  SRC_NONE        0
+#define  SRC_ENTROPY     1
+#define  SRC_LFSR        2
+#define  SE_RNG_CONFIG_SRC(x)         ((x) << 2)
 
-#define SE_CONTEXT_UPDATED_IV_LENGTH	256
+#define SE_RNG_SRC_CONFIG_REG	0x344
+#define  RO_ENTR_LOCK_DISABLE  0
+#define  RO_ENTR_LOCK_ENABLE   1
+#define  SE_RNG_SRC_CONFIG_ENTR_SRC_LOCK(x) ((x) << 0)
+#define  RO_ENTR_DISABLE       0
+#define  RO_ENTR_ENABLE        1
+#define  SE_RNG_SRC_CONFIG_ENTR_SRC(x)      ((x) << 1)
+#define  RO_HW_DIS_CYA_DISABLE 0
+#define  RO_HW_DIS_CYA_ENABLE  1
+#define  SE_RNG_SRC_CONFIG_HW_DIS_CYA(x)    ((x) << 2)
+#define  SE_RNG_SRC_CONFIG_ENTR_SUBSMPL(x)  ((x) << 4)
+#define  SE_RNG_SRC_CONFIG_ENTR_DATA_FLUSH  BIT(8)
 
-#define SE_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET (SE_CONTEXT_UPDATED_IV_OFFSET + \
+#define SE_RNG_RESEED_INTERVAL_REG 0x348
-					SE_CONTEXT_UPDATED_IV_LENGTH)
-#define SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET \
-					(SE11_CONTEXT_UPDATED_IV_OFFSET + \
-					SE_CONTEXT_UPDATED_IV_LENGTH)
-
-#define SE_CONTEXT_SAVE_RSA_KEYS_OFFSET	SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET
-
-#define SE_CONTEXT_SAVE_RSA_KEY_LENGTH	1024
-
-#define SE_CONTEXT_SAVE_RSA_KNOWN_PATTERN_OFFSET	\
-	(SE_CONTEXT_SAVE_RSA_KEYS_OFFSET + SE_CONTEXT_SAVE_RSA_KEY_LENGTH)
-
-#define SE_CONTEXT_KNOWN_PATTERN_SIZE	16
-
-#define TEGRA_SE_RSA_KEYSLOT_COUNT		2
-
-#define SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET	0x40C
-#define SE_RSA_KEY_TBL_DIS_KEY_LOCK_FLAG    0x80
-
-#define SE_RSA_KEYTABLE_ACCESS_REG_OFFSET	0x410
-#define SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG         (1 << 0)
-#define SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG       (1 << 1)
-#define SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG)
-#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG          (1 << 2)
-#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT    (1 << 2)
-#define SE_RSA_KEY_TBL_DIS_KEY_ALL_COMMON_FLAG  7
-#define SE_RSA_KEY_TBL_DIS_KEY_ALL_FLAG        0x7F
-
-#define SE_RSA_KEYTABLE_ADDR	0x420
-#define SE_RSA_KEYTABLE_DATA	0x424
-#define SE_RSA_OUTPUT 0x428
-
-#define RSA_KEY_READ	0
-#define RSA_KEY_WRITE	1
-#define SE_RSA_KEY_OP_SHIFT	10
-#define SE_RSA_KEY_OP(x)	(x << SE_RSA_KEY_OP_SHIFT)
-
-#define RSA_KEY_INPUT_MODE_REG	0
-#define RSA_KEY_INPUT_MODE_DMA	1
-#define RSA_KEY_INPUT_MODE_SHIFT	8
-#define RSA_KEY_INPUT_MODE(x)	(x << RSA_KEY_INPUT_MODE_SHIFT)
 
+#define SE_RSA_CONFIG 0x400
 #define  RSA_KEY_SLOT_ONE 0
 #define  RSA_KEY_SLOT_TW0 1
-#define RSA_KEY_NUM_SHIFT	7
+#define  RSA_KEY_SLOT(x)            ((x) << 24)
-#define RSA_KEY_NUM(x)	(x << RSA_KEY_NUM_SHIFT)
 
+#define SE_RSA_KEY_SIZE_REG 0x404
+#define  RSA_KEY_WIDTH_512  0
+#define  RSA_KEY_WIDTH_1024 1
+#define  RSA_KEY_WIDTH_1536 2
+#define  RSA_KEY_WIDTH_2048 3
+
+#define SE_RSA_EXP_SIZE_REG 0x408
+
+#define SE_RSA_SECURITY_PERKEY_REG 0x40C
+#define  SE_RSA_KEY_LOCK_FLAG               0x80
+#define SE_RSA_KEYTABLE_ACCESS_REG 0x410
+#define  SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG    BIT(0)
+#define  SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG  BIT(1)
+#define  SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG     BIT(2)
+#define  SE_RSA_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
+#define  SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG      (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG)
+#define  SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_USE_FLAG  (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG | SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG)
+
+#define SE_RSA_KEYTABLE_ADDR_REG 0x420
+#define  SE_RSA_KEYTABLE_PKT(x)        ((x) << 0)
 #define  RSA_KEY_TYPE_EXP       0
 #define  RSA_KEY_TYPE_MOD       1
-#define RSA_KEY_TYPE_SHIFT	6
+#define  SE_RSA_KEYTABLE_TYPE(x)       ((x) << 6)
-#define RSA_KEY_TYPE(x)	(x << RSA_KEY_TYPE_SHIFT)
+#define  RSA_KEY_NUM(x)                ((x) << 7)
+#define  RSA_KEY_INPUT_MODE_REG 0
+#define  RSA_KEY_INPUT_MODE_DMA 1
+#define  SE_RSA_KEYTABLE_INPUT_MODE(x) ((x) << 8)
+#define  RSA_KEY_READ           0
+#define  RSA_KEY_WRITE          1
+#define  SE_RSA_KEY_OP(x)              ((x) << 10)
 
-#define SE_RSA_KEY_SIZE_REG_OFFSET	0x404
+#define SE_RSA_KEYTABLE_DATA_REG 0x424
-#define SE_RSA_EXP_SIZE_REG_OFFSET	0x408
 
-#define RSA_KEY_SLOT_SHIFT	24
+#define SE_RSA_OUTPUT_REG 0x428
-#define RSA_KEY_SLOT(x)	(x << RSA_KEY_SLOT_SHIFT)
+#define  SE_RSA_OUTPUT_REG_COUNT 64
-#define SE_RSA_CONFIG	0x400
 
-#define RSA_KEY_PKT_WORD_ADDR_SHIFT	0
+#define SE_STATUS_REG 0x800
-#define RSA_KEY_PKT_WORD_ADDR(x)	(x << RSA_KEY_PKT_WORD_ADDR_SHIFT)
+#define  SE_STATUS_STATE_IDLE     0
+#define  SE_STATUS_STATE_BUSY     1
+#define  SE_STATUS_STATE_WAIT_OUT 2
+#define  SE_STATUS_STATE_WAIT_IN  3
+#define  SE_STATUS_STATE_MASK     3
 
-#define RSA_KEY_WORD_ADDR_SHIFT	0
+#define SE_ERR_STATUS_REG 0x804
-#define RSA_KEY_WORD_ADDR(x)	(x << RSA_KEY_WORD_ADDR_SHIFT)
+#define  SE_ERR_STATUS_SE_NS_ACCESS    BIT(0)
+#define  SE_ERR_STATUS_BUSY_REG_WR     BIT(1)
+#define  SE_ERR_STATUS_DST             BIT(2)
+#define  SE_ERR_STATUS_SRK_USAGE_LIMIT BIT(3)
+#define  SE_ERR_STATUS_TZRAM_NS_ACCESS BIT(24)
+#define  SE_ERR_STATUS_TZRAM_ADDRESS   BIT(25)
 
-#define SE_RSA_KEYTABLE_PKT_SHIFT	0
+#define SE_MISC_REG 0x808
-#define SE_RSA_KEYTABLE_PKT(x)	(x << SE_RSA_KEYTABLE_PKT_SHIFT)
+#define  SE_ENTROPY_NEXT_192BIT BIT(0)
+#define  SE_ENTROPY_VN_BYPASS   BIT(1)
+#define  SE_CLK_OVR_ON          BIT(2)
 
-#endif /* _CRYPTO_TEGRA_SE_H */
+#define SE_SPARE_REG 0x80C
+#define  SE_ERRATA_FIX_DISABLE 0
+#define  SE_ERRATA_FIX_ENABLE  1
+#define  SE_ECO(x) ((x) << 0)
+
+#endif

bdk/sec/tsec.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  * Copyright (c) 2018 balika011
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -24,6 +24,7 @@
 #include <soc/bpmp.h>
 #include <soc/clock.h>
 #include <soc/kfuse.h>
+#include <soc/pmc.h>
 #include <soc/t210.h>
 #include <mem/heap.h>
 #include <mem/mc.h>
@@ -33,7 +34,8 @@
 // #include <gfx_utils.h>
 
 #define PKG11_MAGIC 0x31314B50
-#define KB_TSEC_FW_EMU_COMPAT 6 // KB ID for HOS 6.2.0.
+
+#define TSEC_HOS_KB_620 6
 
 static int _tsec_dma_wait_idle()
 {
@@ -62,15 +64,16 @@ static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offse
 	return _tsec_dma_wait_idle();
 }
 
-int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
+int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 {
 	int res = 0;
 	u8 *fwbuf = NULL;
+	u32 type = tsec_ctxt->type;
 	u32 *pdir, *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec;
 	u32 *pkg11_magic_off;
 
 	bpmp_mmu_disable();
-	bpmp_clk_rate_set(BPMP_CLK_NORMAL);
+	bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
 
 	// Enable clocks.
 	clock_enable_host1x();
@@ -83,6 +86,18 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 
 	kfuse_wait_ready();
 
+	if (type == TSEC_FW_TYPE_NEW)
+	{
+		// Disable all CCPLEX core rails.
+		pmc_enable_partition(POWER_RAIL_CE0, DISABLE);
+		pmc_enable_partition(POWER_RAIL_CE1, DISABLE);
+		pmc_enable_partition(POWER_RAIL_CE2, DISABLE);
+		pmc_enable_partition(POWER_RAIL_CE3, DISABLE);
+
+		// Enable AHB aperture and set it to full mmio.
+		mc_enable_ahb_redirect(true);
+	}
+
 	// Configure Falcon.
 	TSEC(TSEC_DMACTL) = 0;
 	TSEC(TSEC_IRQMSET) =
@@ -106,11 +121,11 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 	}
 
 	// Load firmware or emulate memio environment for newer TSEC fw.
-	if (kb == KB_TSEC_FW_EMU_COMPAT)
+	if (type == TSEC_FW_TYPE_EMU)
 		TSEC(TSEC_DMATRFBASE) = (u32)tsec_ctxt->fw >> 8;
 	else
 	{
-		fwbuf = (u8 *)malloc(0x4000);
+		fwbuf = (u8 *)malloc(SZ_16K);
 		u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf, 0x100);
 		memcpy(fwbuf_aligned, tsec_ctxt->fw, tsec_ctxt->size);
 		TSEC(TSEC_DMATRFBASE) = (u32)fwbuf_aligned >> 8;
@@ -125,27 +140,27 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 		}
 	}
 
-	if (kb == KB_TSEC_FW_EMU_COMPAT)
+	if (type == TSEC_FW_TYPE_EMU)
 	{
 		// Init SMMU translation for TSEC.
 		pdir = smmu_init_for_tsec();
-		smmu_init(0x4002B000);
+		smmu_init(tsec_ctxt->secmon_base);
 		// Enable SMMU
 		if (!smmu_is_used())
 			smmu_enable();
 
 		// Clock reset controller.
 		car = page_alloc(1);
-		memcpy(car, (void *)CLOCK_BASE, 0x1000);
+		memcpy(car, (void *)CLOCK_BASE, SZ_PAGE);
 		car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = 2;
 		smmu_map(pdir, CLOCK_BASE, (u32)car, 1, _WRITABLE | _READABLE | _NONSECURE);
 
 		// Fuse driver.
 		fuse = page_alloc(1);
-		memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, 0x400);
+		memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, SZ_1K);
 		fuse[0x82C / 4] = 0;
-		fuse[0x9E0 / 4] = (1 << (kb + 2)) - 1;
+		fuse[0x9E0 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1;
-		fuse[0x9E4 / 4] = (1 << (kb + 2)) - 1;
+		fuse[0x9E4 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1;
 		smmu_map(pdir, (FUSE_BASE - 0x800), (u32)fuse, 1, _READABLE | _NONSECURE);
 
 		// Power management controller.
@@ -158,12 +173,12 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 
 		// Security engine.
 		se = page_alloc(1);
-		memcpy(se, (void *)SE_BASE, 0x1000);
+		memcpy(se, (void *)SE_BASE, SZ_PAGE);
 		smmu_map(pdir, SE_BASE, (u32)se, 1, _READABLE | _WRITABLE | _NONSECURE);
 
 		// Memory controller.
 		mc = page_alloc(1);
-		memcpy(mc, (void *)MC_BASE, 0x1000);
+		memcpy(mc, (void *)MC_BASE, SZ_PAGE);
 		mc[MC_IRAM_BOM / 4] = 0;
 		mc[MC_IRAM_TOM / 4] = 0x80000000;
 		smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE);
@@ -172,7 +187,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 		iram = page_alloc(0x30);
 		memcpy(iram, tsec_ctxt->pkg1, 0x30000);
 		// PKG1.1 magic offset.
-		pkg11_magic_off = (u32 *)(iram + (0x7000 / 4));
+		pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / 4));
 		smmu_map(pdir, 0x40010000, (u32)iram, 0x30, _READABLE | _WRITABLE | _NONSECURE);
 
 		// Exception vectors
@@ -187,10 +202,10 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 	TSEC(TSEC_BOOTVEC) = 0;
 	TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU;
 
-	if (kb == KB_TSEC_FW_EMU_COMPAT)
+	if (type == TSEC_FW_TYPE_EMU)
 	{
 		u32 start = get_tmr_us();
-		u32 k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
+		u32 k = se[SE_CRYPTO_KEYTABLE_DATA_REG / 4];
 		u32 key[16] = {0};
 		u32 kidx = 0;
 
@@ -198,9 +213,9 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 		{
 			smmu_flush_all();
 
-			if (k != se[SE_KEYTABLE_DATA0_REG_OFFSET / 4])
+			if (k != se[SE_CRYPTO_KEYTABLE_DATA_REG / 4])
 			{
-				k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
+				k = se[SE_CRYPTO_KEYTABLE_DATA_REG / 4];
 				key[kidx++] = k;
 			}
 
@@ -269,7 +284,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 		SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0;
 		SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0;
 
-		memcpy(tsec_keys, &buf, 0x10);
+		memcpy(tsec_keys, &buf, SE_KEY_128_SIZE);
 	}
 
 out_free:;
@@ -284,7 +299,11 @@ out:;
 	clock_disable_sor_safe();
 	clock_disable_tsec();
 	bpmp_mmu_enable();
-	bpmp_clk_rate_set(BPMP_CLK_DEFAULT_BOOST);
+	bpmp_clk_rate_set(prev_fid);
+
+	// Disable AHB aperture.
+	if (type == TSEC_FW_TYPE_NEW)
+		mc_disable_ahb_redirect();
 
 	return res;
 }

bdk/sec/tsec.h

@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
-* Copyright (c) 2018 CTCaer
+* Copyright (c) 2018-2021 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -20,32 +20,24 @@
 
 #include <utils/types.h>
 
-#define TSEC_KEY_DATA_OFFSET 0x300
+enum tsec_fw_type
+{
+	// Retail Hovi Keygen.
+	TSEC_FW_TYPE_OLD = 0, // 1.0.0 - 6.1.0.
+	TSEC_FW_TYPE_EMU = 1, // 6.2.0 emulated enviroment.
+	TSEC_FW_TYPE_NEW = 2, // 7.0.0+.
+};
 
 typedef struct _tsec_ctxt_t
 {
-	void *fw;
+	const void *fw;
 	u32 size;
+	u32 type;
 	void *pkg1;
+	u32 pkg11_off;
+	u32 secmon_base;
 } tsec_ctxt_t;
 
-typedef struct _tsec_key_data_t
+int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt);
-{
-	u8 debug_key[0x10];
-	u8 blob0_auth_hash[0x10];
-	u8 blob1_auth_hash[0x10];
-	u8 blob2_auth_hash[0x10];
-	u8 blob2_aes_iv[0x10];
-	u8 hovi_eks_seed[0x10];
-	u8 hovi_common_seed[0x10];
-	u32 blob0_size;
-	u32 blob1_size;
-	u32 blob2_size;
-	u32 blob3_size;
-	u32 blob4_size;
-	u8 reserved[0x7C];
-} tsec_key_data_t;
-
-int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt);
 
 #endif

bdk/sec/tsec_t210.h

@@ -20,30 +20,30 @@
 #define TSEC_BOOTKEYVER    0x1040
 #define TSEC_STATUS        0x1044
 #define TSEC_ITFEN         0x1048
-#define  TSEC_ITFEN_CTXEN         (1 << 0)
+#define  TSEC_ITFEN_CTXEN         BIT(0)
-#define  TSEC_ITFEN_MTHDEN        (1 << 1)
+#define  TSEC_ITFEN_MTHDEN        BIT(1)
 #define TSEC_IRQMSET       0x1010
-#define  TSEC_IRQMSET_WDTMR       (1 << 1)
+#define  TSEC_IRQMSET_WDTMR       BIT(1)
-#define  TSEC_IRQMSET_HALT        (1 << 4)
+#define  TSEC_IRQMSET_HALT        BIT(4)
-#define  TSEC_IRQMSET_EXTERR      (1 << 5)
+#define  TSEC_IRQMSET_EXTERR      BIT(5)
-#define  TSEC_IRQMSET_SWGEN0      (1 << 6)
+#define  TSEC_IRQMSET_SWGEN0      BIT(6)
-#define  TSEC_IRQMSET_SWGEN1      (1 << 7)
+#define  TSEC_IRQMSET_SWGEN1      BIT(7)
 #define  TSEC_IRQMSET_EXT(val)    (((val) & 0xFF) << 8)
 #define TSEC_IRQDEST       0x101C
-#define  TSEC_IRQDEST_HALT        (1 << 4)
+#define  TSEC_IRQDEST_HALT        BIT(4)
-#define  TSEC_IRQDEST_EXTERR      (1 << 5)
+#define  TSEC_IRQDEST_EXTERR      BIT(5)
-#define  TSEC_IRQDEST_SWGEN0      (1 << 6)
+#define  TSEC_IRQDEST_SWGEN0      BIT(6)
-#define  TSEC_IRQDEST_SWGEN1      (1 << 7)
+#define  TSEC_IRQDEST_SWGEN1      BIT(7)
 #define  TSEC_IRQDEST_EXT(val)    (((val) & 0xFF) << 8)
 #define TSEC_CPUCTL       0x1100
-#define  TSEC_CPUCTL_STARTCPU     (1 << 1)
+#define  TSEC_CPUCTL_STARTCPU     BIT(1)
 #define TSEC_BOOTVEC      0x1104
 #define TSEC_DMACTL       0x110C
 #define TSEC_DMATRFBASE   0x1110
 #define TSEC_DMATRFMOFFS  0x1114
 #define TSEC_DMATRFCMD    0x1118
-#define  TSEC_DMATRFCMD_IDLE      (1 << 1)
+#define  TSEC_DMATRFCMD_IDLE      BIT(1)
-#define  TSEC_DMATRFCMD_IMEM      (1 << 4)
+#define  TSEC_DMATRFCMD_IMEM      BIT(4)
 #define  TSEC_DMATRFCMD_SIZE_256B (6 << 8)
 #define TSEC_DMATRFFBOFFS 0x111C
 

bdk/soc/bpmp.c

@@ -1,7 +1,7 @@
 /*
  * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
  *
- * Copyright (c) 2019-2020 CTCaer
+ * Copyright (c) 2019-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -25,38 +25,38 @@
 #define BPMP_MMU_CACHE_LINE_SIZE        0x20
 
 #define BPMP_CACHE_CONFIG               0x0
-#define  CFG_ENABLE_CACHE               (1 << 0)
+#define  CFG_ENABLE_CACHE               BIT(0)
-#define  CFG_ENABLE_SKEW_ASSOC          (1 << 1)
+#define  CFG_ENABLE_SKEW_ASSOC          BIT(1)
-#define  CFG_DISABLE_RANDOM_ALLOC       (1 << 2)
+#define  CFG_DISABLE_RANDOM_ALLOC       BIT(2)
-#define  CFG_FORCE_WRITE_THROUGH        (1 << 3)
+#define  CFG_FORCE_WRITE_THROUGH        BIT(3)
-#define  CFG_NEVER_ALLOCATE             (1 << 6)
+#define  CFG_NEVER_ALLOCATE             BIT(6)
-#define  CFG_ENABLE_INTERRUPT           (1 << 7)
+#define  CFG_ENABLE_INTERRUPT           BIT(7)
-#define  CFG_MMU_TAG_MODE(x)            (x << 8)
+#define  CFG_MMU_TAG_MODE(x)            ((x) << 8)
 #define   TAG_MODE_PARALLEL             0
 #define   TAG_MODE_TAG_FIRST            1
 #define   TAG_MODE_MMU_FIRST            2
-#define  CFG_DISABLE_WRITE_BUFFER       (1 << 10)
+#define  CFG_DISABLE_WRITE_BUFFER       BIT(10)
-#define  CFG_DISABLE_READ_BUFFER        (1 << 11)
+#define  CFG_DISABLE_READ_BUFFER        BIT(11)
-#define  CFG_ENABLE_HANG_DETECT         (1 << 12)
+#define  CFG_ENABLE_HANG_DETECT         BIT(12)
-#define  CFG_FULL_LINE_DIRTY            (1 << 13)
+#define  CFG_FULL_LINE_DIRTY            BIT(13)
-#define  CFG_TAG_CHK_ABRT_ON_ERR        (1 << 14)
+#define  CFG_TAG_CHK_ABRT_ON_ERR        BIT(14)
-#define  CFG_TAG_CHK_CLR_ERR            (1 << 15)
+#define  CFG_TAG_CHK_CLR_ERR            BIT(15)
-#define  CFG_DISABLE_SAMELINE           (1 << 16)
+#define  CFG_DISABLE_SAMELINE           BIT(16)
-#define  CFG_OBS_BUS_EN                 (1 << 31)
+#define  CFG_OBS_BUS_EN                 BIT(31)
 
 #define BPMP_CACHE_LOCK                 0x4
-#define  LOCK_LINE(x)                   (1 << x)
+#define  LOCK_LINE(x)                   BIT((x))
 
 #define BPMP_CACHE_SIZE                 0xC
 #define BPMP_CACHE_LFSR                 0x10
 
 #define BPMP_CACHE_TAG_STATUS           0x14
-#define  TAG_STATUS_TAG_CHECK_ERROR     (1 << 0)
+#define  TAG_STATUS_TAG_CHECK_ERROR     BIT(0)
 #define  TAG_STATUS_CONFLICT_ADDR_MASK  0xFFFFFFE0
 
 #define BPMP_CACHE_CLKEN_OVERRIDE       0x18
-#define  CLKEN_OVERRIDE_WR_MCCIF_CLKEN  (1 << 0)
+#define  CLKEN_OVERRIDE_WR_MCCIF_CLKEN  BIT(0)
-#define  CLKEN_OVERRIDE_RD_MCCIF_CLKEN  (1 << 1)
+#define  CLKEN_OVERRIDE_RD_MCCIF_CLKEN  BIT(1)
 
 #define BPMP_CACHE_MAINT_ADDR           0x20
 #define BPMP_CACHE_MAINT_DATA           0x24
@@ -68,8 +68,8 @@
 #define BPMP_CACHE_INT_CLEAR            0x44
 #define BPMP_CACHE_INT_RAW_EVENT        0x48
 #define BPMP_CACHE_INT_STATUS           0x4C
-#define  INT_MAINT_DONE                 (1 << 0)
+#define  INT_MAINT_DONE                 BIT(0)
-#define  INT_MAINT_ERROR                (1 << 1)
+#define  INT_MAINT_ERROR                BIT(1)
 
 #define BPMP_CACHE_RB_CFG               0x80
 #define BPMP_CACHE_WB_CFG               0x84
@@ -78,12 +78,12 @@
 #define BPMP_CACHE_MMU_SHADOW_COPY_MASK 0xA4
 
 #define BPMP_CACHE_MMU_CFG              0xAC
-#define  MMU_CFG_BLOCK_MAIN_ENTRY_WR    (1 << 0)
+#define  MMU_CFG_BLOCK_MAIN_ENTRY_WR    BIT(0)
-#define  MMU_CFG_SEQ_EN                 (1 << 1)
+#define  MMU_CFG_SEQ_EN                 BIT(1)
-#define  MMU_CFG_TLB_EN                 (1 << 2)
+#define  MMU_CFG_TLB_EN                 BIT(2)
-#define  MMU_CFG_SEG_CHECK_ALL_ENTRIES  (1 << 3)
+#define  MMU_CFG_SEG_CHECK_ALL_ENTRIES  BIT(3)
-#define  MMU_CFG_ABORT_STORE_LAST       (1 << 4)
+#define  MMU_CFG_ABORT_STORE_LAST       BIT(4)
-#define  MMU_CFG_CLR_ABORT              (1 << 5)
+#define  MMU_CFG_CLR_ABORT              BIT(5)
 
 #define BPMP_CACHE_MMU_CMD              0xB0
 #define  MMU_CMD_NOP                    0
@@ -98,25 +98,25 @@
 #define  ABORT_STAT_UNIT_TLB            3
 #define  ABORT_STAT_UNIT_SEG            4
 #define  ABORT_STAT_UNIT_FALLBACK       5
-#define  ABORT_STAT_OVERLAP             (1 << 3)
+#define  ABORT_STAT_OVERLAP             BIT(3)
 #define  ABORT_STAT_ENTRY               (0x1F << 4)
 #define  ABORT_STAT_TYPE_MASK           (3 << 16)
 #define  ABORT_STAT_TYPE_EXE            (0 << 16)
 #define  ABORT_STAT_TYPE_RD             (1 << 16)
 #define  ABORT_STAT_TYPE_WR             (2 << 16)
 #define  ABORT_STAT_SIZE                (3 << 18)
-#define  ABORT_STAT_SEQ                 (1 << 20)
+#define  ABORT_STAT_SEQ                 BIT(20)
-#define  ABORT_STAT_PROT                (1 << 21)
+#define  ABORT_STAT_PROT                BIT(21)
 
 #define BPMP_CACHE_MMU_ABORT_ADDR       0xB8
 #define BPMP_CACHE_MMU_ACTIVE_ENTRIES   0xBC
 
 #define BPMP_MMU_SHADOW_ENTRY_BASE      (BPMP_CACHE_BASE + 0x400)
 #define BPMP_MMU_MAIN_ENTRY_BASE        (BPMP_CACHE_BASE + 0x800)
-#define  MMU_EN_CACHED                  (1 << 0)
+#define  MMU_EN_CACHED                  BIT(0)
-#define  MMU_EN_EXEC                    (1 << 1)
+#define  MMU_EN_EXEC                    BIT(1)
-#define  MMU_EN_READ                    (1 << 2)
+#define  MMU_EN_READ                    BIT(2)
-#define  MMU_EN_WRITE                   (1 << 3)
+#define  MMU_EN_WRITE                   BIT(3)
 
 bpmp_mmu_entry_t mmu_entries[] =
 {
@@ -153,7 +153,7 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
 		mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE);
 		mmu_entry->attr = entry->attr;
 
-		BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= (1 << idx);
+		BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= BIT(idx);
 
 		if (apply)
 			BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
@@ -172,7 +172,7 @@ void bpmp_mmu_enable()
 
 	// Init BPMP MMU entries.
 	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0;
-	for (u32 idx = 0; idx < (sizeof(mmu_entries) / sizeof(bpmp_mmu_entry_t)); idx++)
+	for (u32 idx = 0; idx < ARRAY_SIZE(mmu_entries); idx++)
 		bpmp_mmu_set_entry(idx, &mmu_entries[idx], false);
 
 	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
@@ -212,43 +212,45 @@ const u8 pll_divn[] = {
 	//95   // BPMP_CLK_DEV_BOOST: 608MHz 49% - 152MHz APB.
 };
 
-bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;
+bpmp_freq_t bpmp_fid_current = BPMP_CLK_NORMAL;
 
 void bpmp_clk_rate_get()
 {
 	bool clk_src_is_pllp = ((CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) >> 4) & 7) == 3;
 
 	if (clk_src_is_pllp)
-		bpmp_clock_set = BPMP_CLK_NORMAL;
+		bpmp_fid_current = BPMP_CLK_NORMAL;
 	else
 	{
-		bpmp_clock_set = BPMP_CLK_HIGH_BOOST;
+		bpmp_fid_current = BPMP_CLK_HIGH_BOOST;
 
 		u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
 		for (u32 i = 1; i < sizeof(pll_divn); i++)
 		{
 			if (pll_divn[i] == pll_divn_curr)
 			{
-				bpmp_clock_set = i;
+				bpmp_fid_current = i;
 				break;
 			}
 		}
 	}
 }
 
-void bpmp_clk_rate_set(bpmp_freq_t fid)
+bpmp_freq_t bpmp_clk_rate_set(bpmp_freq_t fid)
 {
+	bpmp_freq_t prev_fid = bpmp_fid_current;
+
 	if (fid > (BPMP_CLK_MAX - 1))
 		fid = BPMP_CLK_MAX - 1;
 
-	if (bpmp_clock_set == fid)
+	if (prev_fid == fid)
-		return;
+		return prev_fid;
 
 	if (fid)
 	{
-		if (bpmp_clock_set)
+		if (prev_fid)
 		{
-			// Restore to PLLP source during PLLC4 configuration.
+			// Restore to PLLP source during PLLC configuration.
 			CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT.
 			msleep(1); // Wait a bit for clock source change.
 		}
@@ -269,7 +271,10 @@ void bpmp_clk_rate_set(bpmp_freq_t fid)
 		// Disable PLLC to save power.
 		clock_disable_pllc();
 	}
-	bpmp_clock_set = fid;
+	bpmp_fid_current = fid;
+
+	// Return old fid in case of temporary swap.
+	return prev_fid;
 }
 
 // The following functions halt BPMP to reduce power while sleeping.

bdk/soc/bpmp.h

@@ -1,7 +1,7 @@
 /*
  * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
  *
- * Copyright (c) 2019-2020 CTCaer
+ * Copyright (c) 2019-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -53,6 +53,7 @@ typedef enum
 	BPMP_CLK_MAX
 } bpmp_freq_t;
 
+#define BPMP_CLK_LOWER_BOOST   BPMP_CLK_SUPER_BOOST
 #define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_HYPER_BOOST
 
 void bpmp_mmu_maintenance(u32 op, bool force);
@@ -60,7 +61,7 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
 void bpmp_mmu_enable();
 void bpmp_mmu_disable();
 void bpmp_clk_rate_get();
-void bpmp_clk_rate_set(bpmp_freq_t fid);
+bpmp_freq_t bpmp_clk_rate_set(bpmp_freq_t fid);
 void bpmp_usleep(u32 us);
 void bpmp_msleep(u32 ms);
 void bpmp_halt();

bdk/soc/ccplex.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -15,62 +16,36 @@
  */
 
 #include <soc/ccplex.h>
+#include <soc/hw_init.h>
 #include <soc/i2c.h>
 #include <soc/clock.h>
-#include <utils/util.h>
 #include <soc/pmc.h>
 #include <soc/t210.h>
 #include <power/max77620.h>
 #include <power/max7762x.h>
+#include <power/max77812.h>
+#include <utils/util.h>
 
-void _ccplex_enable_power()
+void _ccplex_enable_power_t210()
 {
-	u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); // Get current pinmuxing
+	// Configure GPIO5 and enable output in order to power CPU pmic.
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & ~(1 << 5)); // Disable GPIO5 pinmuxing.
+	max77620_config_gpio(5, MAX77620_GPIO_OUTPUT_ENABLE);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
 
-	// Enable cores power.
+	// Configure CPU pmic.
 	// 1-3.x: MAX77621_NFSR_ENABLE.
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
-		MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE | MAX77621_RAMP_12mV_PER_US);
 	// 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL.
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
+	max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_HOS_CFG);
-		MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL);
+
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
+	// Set voltage and enable cores power.
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
+	max7762x_regulator_set_voltage(REGULATOR_CPU0, 950000);
+	max7762x_regulator_enable(REGULATOR_CPU0, true);
 }
 
-int _ccplex_pmc_enable_partition(u32 part, int enable)
+void _ccplex_enable_power_t210b01()
 {
-	u32 part_mask = 1 << part;
+	// Set voltage and enable cores power.
-	u32 desired_state = enable << part;
+	max7762x_regulator_set_voltage(REGULATOR_CPU1, 800000);
-
+	max7762x_regulator_enable(REGULATOR_CPU1, true);
-	// Check if the partition has the state we want.
-	if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
-		return 1;
-
-	u32 i = 5001;
-	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
-	{
-		usleep(1);
-		i--;
-		if (i < 1)
-			return 0;
-	}
-
-	// Toggle power gating.
-	PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | 0x100;
-
-	i = 5001;
-	while (i > 0)
-	{
-		if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
-			break;
-		usleep(1);
-		i--;
-	}
-
-	return 1;
 }
 
 void ccplex_boot_cpu0(u32 entry)
@@ -78,40 +53,33 @@ void ccplex_boot_cpu0(u32 entry)
 	// Set ACTIVE_CLUSER to FAST.
 	FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE;
 
-	_ccplex_enable_power();
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
+		_ccplex_enable_power_t210();
+	else
+		_ccplex_enable_power_t210b01();
 
-	if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
+	clock_enable_pllx();
-	{
-		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
-		usleep(2);
-		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
-		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
-		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
-		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
-	}
-	while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000))
-		;
 
-	// Configure MSELECT source and enable clock.
+	// Configure MSELECT source and enable clock to 102MHz.
 	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6;
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & 0xFFFFFFF7) | 8;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_MSELECT);
 
 	// Configure initial CPU clock frequency and enable clock.
-	CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888;
+	CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY)  = 0x20008888; // PLLX_OUT0_LJ.
 	CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000;
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = 1;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG);
 
 	clock_enable_coresight();
 
 	// CAR2PMC_CPU_ACK_WIDTH should be set to 0.
 	CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
 
-	// Enable CPU rail.
+	// Enable CPU main rail.
-	_ccplex_pmc_enable_partition(0, 1);
+	pmc_enable_partition(POWER_RAIL_CRAIL, ENABLE);
-	// Enable cluster 0 non-CPU.
+	// Enable cluster 0 non-CPU rail.
-	_ccplex_pmc_enable_partition(15, 1);
+	pmc_enable_partition(POWER_RAIL_C0NC,  ENABLE);
-	// Enable CE0.
+	// Enable CPU0 rail.
-	_ccplex_pmc_enable_partition(14, 1);
+	pmc_enable_partition(POWER_RAIL_CE0,   ENABLE);
 
 	// Request and wait for RAM repair.
 	FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;
@@ -131,7 +99,7 @@ void ccplex_boot_cpu0(u32 entry)
 	// MC(MC_TZ_SECURITY_CTRL) = 1;
 
 	// Clear MSELECT reset.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT);
 	// Clear NONCPU reset.
 	CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000;
 	// Clear CPU0 reset.

bdk/soc/clock.c

@@ -16,110 +16,118 @@
  */
 
 #include <soc/clock.h>
+#include <soc/hw_init.h>
 #include <soc/t210.h>
 #include <storage/sdmmc.h>
 #include <utils/util.h>
 
-/*
+typedef struct _clock_osc_t
- * CLOCK Peripherals:
+{
- * L   0 -  31
+	u32 freq;
- * H  32 -  63
+	u16 min;
- * U  64 -  95
+	u16 max;
- * V  96 - 127
+} clock_osc_t;
- * W 128 - 159
+
- * X 160 - 191
+static const clock_osc_t _clock_osc_cnt[] = {
- * Y 192 - 223
+	{ 12000, 706,  757 },
- */
+	{ 13000, 766,  820 },
+	{ 16800, 991,  1059 },
+	{ 19200, 1133, 1210 },
+	{ 26000, 1535, 1638 },
+	{ 38400, 2268, 2418 },
+	{ 48000, 2836, 3023 }
+};
 
 /* clock_t: reset, enable, source, index, clk_src, clk_div */
 
 static const clock_t _clock_uart[] = {
-/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA,   6,  0, 2 },
+	{ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA,   CLK_L_UARTA,   0, 2 },
-/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB,   7,  0, 2 },
+	{ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB,   CLK_L_UARTB,   0, 2 },
-/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC,   23, 0, 2 },
+	{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC,   CLK_H_UARTC,   0, 2 },
-/* UART D */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD,   1,  0, 2 },
+	{ CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD,   CLK_U_UARTD,   0, 2 },
-/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 }
+	{ CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, CLK_Y_UARTAPE, 0, 2 }
 };
 
 //I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26.
 static const clock_t _clock_i2c[] = {
-/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
+	{ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, CLK_L_I2C1, 0, 19 }, //20.4MHz -> 100KHz
-/* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4  }, //81.6MHz -> 400KHz
+	{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, CLK_H_I2C2, 0, 4  }, //81.6MHz -> 400KHz
-/* I2C3 */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, 3,  0, 4  }, //81.6MHz -> 400KHz
+	{ CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, CLK_U_I2C3, 0, 4  }, //81.6MHz -> 400KHz
-/* I2C4 */ { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, 7,  0, 19 }, //20.4MHz -> 100KHz
+	{ CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, CLK_V_I2C4, 0, 19 }, //20.4MHz -> 100KHz
-/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4  }, //81.6MHz -> 400KHz
+	{ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, CLK_H_I2C5, 0, 4  }, //81.6MHz -> 400KHz
-/* I2C6 */ { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, 6,  0, 19 }  //20.4MHz -> 100KHz
+	{ CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, CLK_X_I2C6, 0, 19 }  //20.4MHz -> 100KHz
 };
 
 static clock_t _clock_se = {
-	CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE,     31, 0, 0
+	CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE,     CLK_V_SE,       0, 0 // 408MHz.
 };
 
 static clock_t _clock_tzram = {
-	CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE,                        30, 0, 0
+	CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE,                        CLK_V_TZRAM,    0, 0
 };
 
 static clock_t _clock_host1x = {
-	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 28, 4, 3
+	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X,   4, 3 // 163.2MHz.
 };
 static clock_t _clock_tsec = {
-	CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC,   19, 0, 2
+	CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC,   CLK_U_TSEC,     0, 2 // 204MHz.
 };
 static clock_t _clock_sor_safe = {
-	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE,                        30, 0, 0
+	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE,                        CLK_Y_SOR_SAFE, 0, 0
 };
 static clock_t _clock_sor0 = {
-	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE,                        22, 0, 0
+	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NOT_USED,                         CLK_X_SOR0,     0, 0
 };
 static clock_t _clock_sor1 = {
-	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1,   23, 0, 2
+	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1,   CLK_X_SOR1,     0, 2 //204MHz.
 };
 static clock_t _clock_kfuse = {
-	CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE,                        8,  0, 0
+	CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE,                        CLK_H_KFUSE,    0, 0
 };
 
 static clock_t _clock_cl_dvfs =	{
-	CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE,                        27, 0, 0
+	CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE,                        CLK_W_DVFS,     0, 0
 };
 static clock_t _clock_coresight = {
-	CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE,   9, 0, 4
+	CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE,  CLK_U_CSITE,    0, 4 // 136MHz.
 };
 
 static clock_t _clock_pwm = {
-	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM,    17, 6, 4 // Fref: 6.2MHz.
+	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM,    CLK_L_PWM,      6, 4 // Fref: 6.4MHz. HOS: PLLP / 54 = 7.55MHz.
 };
 
 static clock_t _clock_sdmmc_legacy_tm = {
-	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66
+	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66
 };
 
 void clock_enable(const clock_t *clk)
 {
 	// Put clock into reset.
-	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
+	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
 	// Disable.
-	CLOCK(clk->enable) &= ~(1 << clk->index);
+	CLOCK(clk->enable) &= ~BIT(clk->index);
 	// Configure clock source if required.
 	if (clk->source)
 		CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
 	// Enable.
-	CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
+	CLOCK(clk->enable) = (CLOCK(clk->enable) & ~BIT(clk->index)) | BIT(clk->index);
 	usleep(2);
 
 	// Take clock off reset.
-	CLOCK(clk->reset) &= ~(1 << clk->index);
+	CLOCK(clk->reset) &= ~BIT(clk->index);
 }
 
 void clock_disable(const clock_t *clk)
 {
 	// Put clock into reset.
-	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
+	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
 	// Disable.
-	CLOCK(clk->enable) &= ~(1 << clk->index);
+	CLOCK(clk->enable) &= ~BIT(clk->index);
 }
 
 void clock_enable_fuse(bool enable)
 {
+	// Enable Fuse registers visibility.
 	CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28);
 }
 
@@ -133,7 +141,7 @@ void clock_disable_uart(u32 idx)
 	clock_disable(&_clock_uart[idx]);
 }
 
-#define UART_SRC_CLK_DIV_EN (1 << 24)
+#define UART_SRC_CLK_DIV_EN BIT(24)
 
 int clock_uart_use_src_div(u32 idx, u32 baud)
 {
@@ -164,6 +172,10 @@ void clock_disable_i2c(u32 idx)
 void clock_enable_se()
 {
 	clock_enable(&_clock_se);
+
+	// Lock clock to always enabled if T210B01.
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SE) |= 0x100;
 }
 
 void clock_enable_tzram()
@@ -223,13 +235,13 @@ void clock_disable_sor1()
 
 void clock_enable_kfuse()
 {
-	//clock_enable(&_clock_kfuse);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_KFUSE);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_KFUSE);
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_KFUSE);
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100;
+	usleep(10); // Wait 10s to prevent glitching.
-	usleep(10);
+
-	CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_KFUSE);
-	usleep(20);
+	usleep(20); // Wait 20s fo kfuse hw to init.
 }
 
 void clock_disable_kfuse()
@@ -267,6 +279,32 @@ void clock_disable_pwm()
 	clock_disable(&_clock_pwm);
 }
 
+void clock_enable_pllx()
+{
+	// Configure and enable PLLX if disabled.
+	if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & PLLX_BASE_ENABLE)) // PLLX_ENABLE.
+	{
+		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= ~PLLX_MISC3_IDDQ; // Disable IDDQ.
+		usleep(2);
+
+		// Set div configuration.
+		const u32 pllx_div_cfg = (2 << 20) | (156 << 8) | 2; // P div: 2 (3), N div: 156, M div: 2. 998.4 MHz.
+
+		// Bypass dividers.
+		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = PLLX_BASE_BYPASS | pllx_div_cfg;
+		// Disable bypass
+		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = pllx_div_cfg;
+		// Set PLLX_LOCK_ENABLE.
+		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) |= PLLX_MISC_LOCK_EN;
+		// Enable PLLX.
+		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = PLLX_BASE_ENABLE | pllx_div_cfg;
+	}
+
+	// Wait for PLL to stabilize.
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & PLLX_BASE_LOCK))
+		;
+}
+
 void clock_enable_pllc(u32 divn)
 {
 	u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
@@ -294,7 +332,7 @@ void clock_enable_pllc(u32 divn)
 		;
 
 	// Disable PLLC_OUT1, enable reset and set div to 1.5.
-	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
+	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = BIT(8);
 
 	// Enable PLLC_OUT1 and bring it out of reset.
 	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
@@ -312,7 +350,7 @@ void clock_disable_pllc()
 	usleep(10);
 }
 
-#define PLLC4_ENABLED (1 << 31)
+#define PLLC4_ENABLED BIT(31)
 #define PLLC4_IN_USE  (~PLLC4_ENABLED)
 
 u32 pllc4_enabled = 0;
@@ -362,48 +400,60 @@ static void _clock_disable_pllc4(u32 mask)
 	pllc4_enabled = 0;
 }
 
-#define L_SWR_SDMMC1_RST (1 << 14)
+void clock_enable_pllu()
-#define L_SWR_SDMMC2_RST (1 << 9)
+{
-#define L_SWR_SDMMC4_RST (1 << 15)
+	// Configure PLLU.
-#define U_SWR_SDMMC3_RST (1 << 5)
+	CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) |= BIT(29); // Disable reference clock.
+	u32 pllu_cfg = (CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & 0xFFE00000) | BIT(24) | (1 << 16) | (0x19 << 8) | 2;
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg;
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | PLLCX_BASE_ENABLE; // Enable.
 
-#define L_CLK_ENB_SDMMC1 (1 << 14)
+	// Wait for PLL to stabilize.
-#define L_CLK_ENB_SDMMC2 (1 << 9)
+	u32 timeout = (u32)TMR(TIMERUS_CNTR_1US) + 1300;
-#define L_CLK_ENB_SDMMC4 (1 << 15)
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & PLLCX_BASE_LOCK)) // PLL_LOCK.
-#define U_CLK_ENB_SDMMC3 (1 << 5)
+		if ((u32)TMR(TIMERUS_CNTR_1US) > timeout)
+			break;
+	usleep(10);
 
-#define L_SET_SDMMC1_RST (1 << 14)
+	// Enable PLLU USB/HSIC/ICUSB/48M.
-#define L_SET_SDMMC2_RST (1 << 9)
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) |= 0x2E00000;
-#define L_SET_SDMMC4_RST (1 << 15)
+}
-#define U_SET_SDMMC3_RST (1 << 5)
 
-#define L_CLR_SDMMC1_RST (1 << 14)
+void clock_disable_pllu()
-#define L_CLR_SDMMC2_RST (1 << 9)
+{
-#define L_CLR_SDMMC4_RST (1 << 15)
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x2E00000;  // Disable PLLU USB/HSIC/ICUSB/48M.
-#define U_CLR_SDMMC3_RST (1 << 5)
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x40000000; // Disable PLLU.
+	CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) &= ~0x20000000; // Enable reference clock.
+}
 
-#define L_SET_CLK_ENB_SDMMC1 (1 << 14)
+void clock_enable_utmipll()
-#define L_SET_CLK_ENB_SDMMC2 (1 << 9)
+{
-#define L_SET_CLK_ENB_SDMMC4 (1 << 15)
+	// Set UTMIPLL dividers and config based on OSC and enable it to 960 MHz.
-#define U_SET_CLK_ENB_SDMMC3 (1 << 5)
+	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0) & 0xFF0000FF) | (25 << 16) | (1 << 8); // 38.4Mhz * (25 / 1) = 960 MHz.
+	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) & 0xFF00003F) | (24 << 18); // Set delay count for 38.4Mhz osc crystal.
+	CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) &  0x7FFA000) | (1 << 15) | 375;
 
-#define L_CLR_CLK_ENB_SDMMC1 (1 << 14)
+	// Wait for UTMIPLL to stabilize.
-#define L_CLR_CLK_ENB_SDMMC2 (1 << 9)
+	u32 retries = 10; // Wait 20us
-#define L_CLR_CLK_ENB_SDMMC4 (1 << 15)
+	while (!(CLOCK(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0) & UTMIPLL_LOCK) && retries)
-#define U_CLR_CLK_ENB_SDMMC3 (1 << 5)
+	{
+		usleep(1);
+		retries--;
+	}
+}
 
 static int _clock_sdmmc_is_reset(u32 id)
 {
 	switch (id)
 	{
 	case SDMMC_1:
-		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC1_RST;
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & BIT(CLK_L_SDMMC1);
 	case SDMMC_2:
-		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC2_RST;
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & BIT(CLK_L_SDMMC2);
 	case SDMMC_3:
-		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & U_SWR_SDMMC3_RST;
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & BIT(CLK_U_SDMMC3);
 	case SDMMC_4:
-		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC4_RST;
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & BIT(CLK_L_SDMMC4);
 	}
 	return 0;
 }
@@ -413,16 +463,16 @@ static void _clock_sdmmc_set_reset(u32 id)
 	switch (id)
 	{
 	case SDMMC_1:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC1_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_SDMMC1);
 		break;
 	case SDMMC_2:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC2_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_SDMMC2);
 		break;
 	case SDMMC_3:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = U_SET_SDMMC3_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = BIT(CLK_U_SDMMC3);
 		break;
 	case SDMMC_4:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC4_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_SDMMC4);
 		break;
 	}
 }
@@ -432,16 +482,16 @@ static void _clock_sdmmc_clear_reset(u32 id)
 	switch (id)
 	{
 	case SDMMC_1:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC1_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_SDMMC1);
 		break;
 	case SDMMC_2:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC2_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_SDMMC2);
 		break;
 	case SDMMC_3:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = U_CLR_SDMMC3_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = BIT(CLK_U_SDMMC3);
 		break;
 	case SDMMC_4:
-		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC4_RST;
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_SDMMC4);
 		break;
 	}
 }
@@ -451,13 +501,13 @@ static int _clock_sdmmc_is_enabled(u32 id)
 	switch (id)
 	{
 	case SDMMC_1:
-		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC1;
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_SDMMC1);
 	case SDMMC_2:
-		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC2;
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_SDMMC2);
 	case SDMMC_3:
-		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & U_CLK_ENB_SDMMC3;
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & BIT(CLK_U_SDMMC3);
 	case SDMMC_4:
-		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC4;
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_SDMMC4);
 	}
 	return 0;
 }
@@ -467,16 +517,16 @@ static void _clock_sdmmc_set_enable(u32 id)
 	switch (id)
 	{
 	case SDMMC_1:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC1;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_SDMMC1);
 		break;
 	case SDMMC_2:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC2;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_SDMMC2);
 		break;
 	case SDMMC_3:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = U_SET_CLK_ENB_SDMMC3;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = BIT(CLK_U_SDMMC3);
 		break;
 	case SDMMC_4:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC4;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_SDMMC4);
 		break;
 	}
 }
@@ -486,16 +536,16 @@ static void _clock_sdmmc_clear_enable(u32 id)
 	switch (id)
 	{
 	case SDMMC_1:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC1;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_SDMMC1);
 		break;
 	case SDMMC_2:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC2;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_SDMMC2);
 		break;
 	case SDMMC_3:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = U_CLR_CLK_ENB_SDMMC3;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = BIT(CLK_U_SDMMC3);
 		break;
 	case SDMMC_4:
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC4;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_SDMMC4);
 		break;
 	}
 }
@@ -503,7 +553,7 @@ static void _clock_sdmmc_clear_enable(u32 id)
 static void _clock_sdmmc_config_legacy_tm()
 {
 	clock_t *clk = &_clock_sdmmc_legacy_tm;
-	if (!(CLOCK(clk->enable) & (1 << clk->index)))
+	if (!(CLOCK(clk->enable) & BIT(clk->index)))
 		clock_enable(clk);
 }
 
@@ -588,7 +638,7 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
 
 	// Enable PLLC4 if in use by any SDMMC.
 	if (source)
-		_clock_enable_pllc4(1 << id);
+		_clock_enable_pllc4(BIT(id));
 
 	// Set SDMMC legacy timeout clock.
 	_clock_sdmmc_config_legacy_tm();
@@ -680,7 +730,7 @@ void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
 		*pclock = 40800;
 		*pdivisor = 1;
 		break;
-	case SDHCI_TIMING_MMC_DDR52: // Actual IO Freq: 49.92 MHz.
+	case SDHCI_TIMING_MMC_HS102: // Actual IO Freq: 99.84 MHz.
 		*pclock = 200000;
 		*pdivisor = 2;
 		break;
@@ -712,5 +762,58 @@ void clock_sdmmc_disable(u32 id)
 	_clock_sdmmc_set_reset(id);
 	_clock_sdmmc_clear_enable(id);
 	_clock_sdmmc_is_reset(id);
-	_clock_disable_pllc4(1 << id);
+	_clock_disable_pllc4(BIT(id));
 }
+
+u32 clock_get_osc_freq()
+{
+	CLOCK(CLK_RST_CONTROLLER_OSC_FREQ_DET) = OSC_FREQ_DET_TRIG | (2 - 1); // 2 periods of 32.76KHz window.
+	while (CLOCK(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY)
+		;
+	u32 cnt = (CLOCK(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_CNT);
+	CLOCK(CLK_RST_CONTROLLER_OSC_FREQ_DET) = 0;
+
+	// Return frequency in KHz.
+	for (u32 i = 0; i < ARRAY_SIZE(_clock_osc_cnt); i++)
+		if (cnt >= _clock_osc_cnt[i].min && cnt <= _clock_osc_cnt[i].max)
+			return _clock_osc_cnt[i].freq;
+
+	return 0;
+}
+
+u32 clock_get_dev_freq(clock_pto_id_t id)
+{
+	const u32 pto_win = 16;
+	const u32 pto_osc = 32768;
+
+	u32 val = ((id & PTO_SRC_SEL_MASK) << PTO_SRC_SEL_SHIFT) | PTO_DIV_SEL_DIV1 | PTO_CLK_ENABLE | (pto_win - 1);
+	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
+	usleep(2);
+
+	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_RST;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
+	usleep(2);
+
+	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
+	usleep(2);
+
+	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_EN;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
+	usleep((1000000 * pto_win / pto_osc) + 12 + 2);
+
+	while (CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT_BUSY)
+		;
+
+	u32 cnt = CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT;
+
+	CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = 0;
+	(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
+	usleep(2);
+
+	u32 freq_khz = (u64)cnt * pto_osc / pto_win / 1000;
+
+	return freq_khz;
+}
+

bdk/soc/clock.h

@@ -35,6 +35,10 @@
 #define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
 #define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
 #define CLK_RST_CONTROLLER_OSC_CTRL 0x50
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET 0x58
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS 0x5C
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL 0x60
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS 0x64
 #define CLK_RST_CONTROLLER_PLLC_BASE 0x80
 #define CLK_RST_CONTROLLER_PLLC_OUT 0x84
 #define CLK_RST_CONTROLLER_PLLC_MISC 0x88
@@ -48,6 +52,7 @@
 #define CLK_RST_CONTROLLER_PLLA_MISC1 0xB8
 #define CLK_RST_CONTROLLER_PLLA_MISC 0xBC
 #define CLK_RST_CONTROLLER_PLLU_BASE 0xC0
+#define CLK_RST_CONTROLLER_PLLU_OUTA 0xC4
 #define CLK_RST_CONTROLLER_PLLU_MISC 0xCC
 #define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
 #define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
@@ -131,6 +136,7 @@
 #define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
 #define CLK_RST_CONTROLLER_PLLE_AUX 0x48C
 #define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
+#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3 0x4C0
 #define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
 #define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0 0x52C
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
@@ -140,6 +146,9 @@
 #define CLK_RST_CONTROLLER_PLLC_MISC_2 0x5D0
 #define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4
 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS 0x608
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV 0x60C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS 0x610
 #define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
@@ -151,32 +160,469 @@
 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
 
 #define CLK_NO_SOURCE 0x0
+#define CLK_NOT_USED  0x0
 
 /*! PLL control and status bits */
-#define PLLCX_BASE_ENABLE    (1 << 30)
+#define PLLX_BASE_LOCK       BIT(27)
-#define PLLCX_BASE_REF_DIS   (1 << 29)
+#define PLLX_BASE_REF_DIS    BIT(29)
-#define PLLCX_BASE_LOCK      (1 << 27)
+#define PLLX_BASE_ENABLE     BIT(30)
+#define PLLX_BASE_BYPASS     BIT(31)
+#define PLLX_MISC_LOCK_EN    BIT(18)
+#define PLLX_MISC3_IDDQ      BIT(3)
 
-#define PLLA_BASE_IDDQ       (1 << 25)
+#define PLLCX_BASE_LOCK      BIT(27)
-#define PLLA_OUT0_CLKEN      (1 << 1)
+#define PLLCX_BASE_REF_DIS   BIT(29)
-#define PLLA_OUT0_RSTN_CLR   (1 << 0)
+#define PLLCX_BASE_ENABLE    BIT(30)
+#define PLLCX_BASE_BYPASS    BIT(31)
 
-#define PLLC_MISC_RESET      (1 << 30)
+#define PLLA_OUT0_RSTN_CLR   BIT(0)
-#define PLLC_MISC1_IDDQ      (1 << 27)
+#define PLLA_OUT0_CLKEN      BIT(1)
-#define PLLC_OUT1_CLKEN      (1 << 1)
+#define PLLA_BASE_IDDQ       BIT(25)
-#define PLLC_OUT1_RSTN_CLR   (1 << 0)
 
-#define PLLC4_MISC_EN_LCKDET (1 << 30)
+#define PLLC_OUT1_RSTN_CLR   BIT(0)
-#define PLLC4_BASE_IDDQ      (1 << 18)
+#define PLLC_OUT1_CLKEN      BIT(1)
-#define PLLC4_OUT3_CLKEN     (1 << 1)
+#define PLLC_MISC1_IDDQ      BIT(27)
-#define PLLC4_OUT3_RSTN_CLR  (1 << 0)
+#define PLLC_MISC_RESET      BIT(30)
+
+#define PLLC4_OUT3_RSTN_CLR  BIT(0)
+#define PLLC4_OUT3_CLKEN     BIT(1)
+#define PLLC4_BASE_IDDQ      BIT(18)
+#define PLLC4_MISC_EN_LCKDET BIT(30)
+
+#define UTMIPLL_LOCK         BIT(31)
+
+/*! PTO_CLK_CNT */
+#define PTO_REF_CLK_WIN_CFG_MASK 0xF
+#define PTO_REF_CLK_WIN_CFG_16P  0xF
+#define PTO_CNT_EN               BIT(9)
+#define PTO_CNT_RST              BIT(10)
+#define PTO_CLK_ENABLE           BIT(13)
+#define PTO_SRC_SEL_SHIFT        14
+#define PTO_SRC_SEL_MASK         0x1FF
+#define PTO_DIV_SEL_MASK         (3 << 23)
+#define PTO_DIV_SEL_GATED        (0 << 23)
+#define PTO_DIV_SEL_DIV1         (1 << 23)
+#define PTO_DIV_SEL_DIV2_RISING  (2 << 23)
+#define PTO_DIV_SEL_DIV2_FALLING (3 << 23)
+#define PTO_DIV_SEL_CPU_EARLY    (0 << 23)
+#define PTO_DIV_SEL_CPU_LATE     (1 << 23)
+
+#define PTO_CLK_CNT_BUSY         BIT(31)
+#define PTO_CLK_CNT              0xFFFFFF
+
+/*! OSC_FREQ_DET */
+#define OSC_REF_CLK_WIN_CFG_MASK 0xF
+#define OSC_FREQ_DET_TRIG        BIT(31)
+
+#define OSC_FREQ_DET_BUSY        BIT(31)
+#define OSC_FREQ_DET_CNT         0xFFFF
+
+/*! PTO IDs. */
+typedef enum _clock_pto_id_t
+{
+	CLK_PTO_PCLK_SYS =          0x06,
+	CLK_PTO_HCLK_SYS =          0x07,
+
+	CLK_PTO_UTMIP_240 =         0x0C,
+
+	CLK_PTO_CCLK_G =            0x12,
+	CLK_PTO_CCLK_G_DIV2 =       0x13,
+
+	CLK_PTO_SPI1 =              0x17,
+	CLK_PTO_SPI2 =              0x18,
+	CLK_PTO_SPI3 =              0x19,
+	CLK_PTO_SPI4 =              0x1A,
+	CLK_PTO_MAUD =              0x1B,
+	CLK_PTO_SCLK =              0x1C,
+
+	CLK_PTO_SDMMC1 =            0x20,
+	CLK_PTO_SDMMC2 =            0x21,
+	CLK_PTO_SDMMC3 =            0x22,
+	CLK_PTO_SDMMC4 =            0x23,
+	CLK_PTO_EMC =               0x24,
+
+	CLK_PTO_CCLK_LP =           0x2B,
+	CLK_PTO_CCLK_LP_DIV2 =      0x2C,
+
+	CLK_PTO_MSELECT =           0x2F,
+
+	CLK_PTO_VIC =               0x36,
+
+	CLK_PTO_NVDEC =             0x39,
+
+	CLK_PTO_NVENC =             0x3A,
+	CLK_PTO_NVJPG =             0x3B,
+	CLK_PTO_TSEC =              0x3C,
+	CLK_PTO_TSECB =             0x3D,
+	CLK_PTO_SE =                0x3E,
+
+	CLK_PTO_DSIA_LP =           0x62,
+
+	CLK_PTO_ISP =               0x64,
+	CLK_PTO_MC =                0x6A,
+
+	CLK_PTO_ACTMON =            0x6B,
+	CLK_PTO_CSITE =             0x6C,
+
+	CLK_PTO_HOST1X =            0x6F,
+
+	CLK_PTO_SE_2 =              0x74, // Same as CLK_PTO_SE.
+	CLK_PTO_SOC_THERM =         0x75,
+
+	CLK_PTO_TSEC_2 =            0x77, // Same as CLK_PTO_TSEC.
+
+	CLK_PTO_ACLK =              0x7C,
+	CLK_PTO_QSPI =              0x7D,
+
+	CLK_PTO_I2S1 =              0x80,
+	CLK_PTO_I2S2 =              0x81,
+	CLK_PTO_I2S3 =              0x82,
+	CLK_PTO_I2S4 =              0x83,
+	CLK_PTO_I2S5 =              0x84,
+	CLK_PTO_AHUB =              0x85,
+	CLK_PTO_APE =               0x86,
+
+	CLK_PTO_DVFS_SOC =          0x88,
+	CLK_PTO_DVFS_REF =          0x89,
+
+	CLK_PTO_SPDIF =             0x8F,
+	CLK_PTO_SPDIF_IN =          0x90,
+	CLK_PTO_UART_FST_MIPI_CAL = 0x91,
+
+	CLK_PTO_PWM =               0x93,
+	CLK_PTO_I2C1 =              0x94,
+	CLK_PTO_I2C2 =              0x95,
+	CLK_PTO_I2C3 =              0x96,
+	CLK_PTO_I2C4 =              0x97,
+	CLK_PTO_I2C5 =              0x98,
+	CLK_PTO_I2C6 =              0x99,
+	CLK_PTO_I2C_SLOW =          0x9A,
+	CLK_PTO_UARTAPE =           0x9B,
+
+	CLK_PTO_EXTPERIPH1 =        0x9D,
+	CLK_PTO_EXTPERIPH2 =        0x9E,
+
+	CLK_PTO_ENTROPY =           0xA0,
+	CLK_PTO_UARTA =             0xA1,
+	CLK_PTO_UARTB =             0xA2,
+	CLK_PTO_UARTC =             0xA3,
+	CLK_PTO_UARTD =             0xA4,
+	CLK_PTO_OWR =               0xA5,
+
+	CLK_PTO_HDA2CODEC_2X =      0xA7,
+	CLK_PTO_HDA =               0xA8,
+
+	CLK_PTO_SDMMC_LEGACY_TM =   0xAB,
+
+	CLK_PTO_SOR0 =              0xC0,
+	CLK_PTO_SOR1 =              0xC1,
+
+	CLK_PTO_DISP2 =             0xC4,
+	CLK_PTO_DISP1 =             0xC5,
+
+	CLK_PTO_XUSB_FALCON =       0x110,
+
+	CLK_PTO_XUSB_FS =           0x136,
+	CLK_PTO_XUSB_SS_HOST_DEV =  0x137,
+	CLK_PTO_XUSB_CORE_HOST =    0x138,
+	CLK_PTO_XUSB_CORE_DEV =     0x139,
+
+	/*
+	 * PLL need PTO enabled in MISC registers.
+	 * Normal div is 2 so result is multiplied with it.
+	 */
+	CLK_PTO_PLLC_DIV2 =              0x01,
+	CLK_PTO_PLLM_DIV2 =              0x02,
+	CLK_PTO_PLLP_DIV2 =              0x03,
+	CLK_PTO_PLLA_DIV2 =              0x04,
+	CLK_PTO_PLLX_DIV2 =              0x05,
+
+	CLK_PTO_PLLMB_DIV2 =             0x25,
+
+	CLK_PTO_PLLC4_DIV2 =             0x51,
+
+	CLK_PTO_PLLA1_DIV2 =             0x55,
+	CLK_PTO_PLLC2_DIV2 =             0x58,
+	CLK_PTO_PLLC3_DIV2 =             0x5A,
+
+	CLK_PTO_PLLD_DIV2 =              0xCB,
+	CLK_PTO_PLLD2_DIV2 =             0xCD,
+	CLK_PTO_PLLDP_DIV2 =             0xCF,
+
+	CLK_PTO_PLLU_DIV2 =              0x10D,
+
+	CLK_PTO_PLLREFE_DIV2 =           0x10F,
+} clock_pto_id_t;
+
+/*
+ * CLOCK Peripherals:
+ * L   0 -  31
+ * H  32 -  63
+ * U  64 -  95
+ * V  96 - 127
+ * W 128 - 159
+ * X 160 - 191
+ * Y 192 - 223
+ */
+
+enum CLK_L_DEV
+{
+	CLK_L_CPU     = 0, // Only reset. Deprecated.
+	CLK_L_BPMP    = 1, // Only reset.
+	CLK_L_SYS     = 2, // Only reset.
+	CLK_L_ISPB    = 3,
+	CLK_L_RTC     = 4,
+	CLK_L_TMR     = 5,
+	CLK_L_UARTA   = 6,
+	CLK_L_UARTB   = 7,
+	CLK_L_GPIO    = 8,
+	CLK_L_SDMMC2  = 9,
+	CLK_L_SPDIF   = 10,
+	CLK_L_I2S2    = 11, // I2S1
+	CLK_L_I2C1    = 12,
+	CLK_L_NDFLASH = 13, // HIDDEN.
+	CLK_L_SDMMC1  = 14,
+	CLK_L_SDMMC4  = 15,
+	CLK_L_TWC     = 16, // HIDDEN.
+	CLK_L_PWM     = 17,
+	CLK_L_I2S3    = 18,
+	CLK_L_EPP     = 19, // HIDDEN.
+	CLK_L_VI      = 20,
+	CLK_L_2D      = 21, // HIDDEN.
+	CLK_L_USBD    = 22,
+	CLK_L_ISP     = 23,
+	CLK_L_3D      = 24, // HIDDEN.
+	CLK_L_IDE     = 25, // RESERVED.
+	CLK_L_DISP2   = 26,
+	CLK_L_DISP1   = 27,
+	CLK_L_HOST1X  = 28,
+	CLK_L_VCP     = 29, // HIDDEN.
+	CLK_L_I2S1    = 30, // I2S0
+	CLK_L_BPMP_CACHE_CTRL = 31, // CONTROLLER
+};
+
+enum CLK_H_DEV
+{
+	CLK_H_MEM      = 0, // MC.
+	CLK_H_AHBDMA   = 1,
+	CLK_H_APBDMA   = 2,
+	//CLK_H_       = 3,
+	CLK_H_KBC      = 4, // HIDDEN.
+	CLK_H_STAT_MON = 5,
+	CLK_H_PMC      = 6,
+	CLK_H_FUSE     = 7,
+	CLK_H_KFUSE    = 8,
+	CLK_H_SPI1     = 9,
+	CLK_H_SNOR     = 10, // HIDDEN.
+	CLK_H_JTAG2TBC = 11,
+	CLK_H_SPI2     = 12,
+	CLK_H_XIO      = 13, // HIDDEN.
+	CLK_H_SPI3     = 14,
+	CLK_H_I2C5     = 15,
+	CLK_H_DSI      = 16,
+	CLK_H_TVO      = 17, // RESERVED.
+	CLK_H_HSI      = 18, // HIDDEN.
+	CLK_H_HDMI     = 19, // HIDDEN.
+	CLK_H_CSI      = 20,
+	CLK_H_TVDAC    = 21, // RESERVED.
+	CLK_H_I2C2     = 22,
+	CLK_H_UARTC    = 23,
+	CLK_H_MIPI_CAL = 24,
+	CLK_H_EMC      = 25,
+	CLK_H_USB2     = 26,
+	CLK_H_USB3     = 27, // HIDDEN.
+	CLK_H_MPE      = 28, // HIDDEN.
+	CLK_H_VDE      = 29, // HIDDEN.
+	CLK_H_BSEA     = 30, // HIDDEN.
+	CLK_H_BSEV     = 31,
+};
+
+enum CLK_U_DEV
+{
+	CLK_U_SPEEDO         = 0, // RESERVED.
+	CLK_U_UARTD          = 1,
+	CLK_U_UARTE          = 2, // HIDDEN.
+	CLK_U_I2C3           = 3,
+	CLK_U_SPI4           = 4,
+	CLK_U_SDMMC3         = 5,
+	CLK_U_PCIE           = 6,
+	CLK_U_OWR            = 7, // RESERVED.
+	CLK_U_AFI            = 8,
+	CLK_U_CSITE          = 9,
+	CLK_U_PCIEXCLK       = 10, // Only reset.
+	CLK_U_BPMPUCQ        = 11, // HIDDEN.
+	CLK_U_LA             = 12,
+	CLK_U_TRACECLKIN     = 13, // HIDDEN.
+	CLK_U_SOC_THERM      = 14,
+	CLK_U_DTV            = 15,
+	CLK_U_NAND_SPEED     = 16, // HIDDEN.
+	CLK_U_I2C_SLOW       = 17,
+	CLK_U_DSIB           = 18,
+	CLK_U_TSEC           = 19,
+	CLK_U_IRAMA          = 20,
+	CLK_U_IRAMB          = 21,
+	CLK_U_IRAMC          = 22,
+	CLK_U_IRAMD          = 23, // EMUCIF ON RESET
+	CLK_U_BPMP_CACHE_RAM = 24,
+	CLK_U_XUSB_HOST      = 25,
+	CLK_U_CLK_M_DOUBLER  = 26,
+	CLK_U_MSENC          = 27, // HIDDEN.
+	CLK_U_SUS_OUT        = 28,
+	CLK_U_DEV2_OUT       = 29,
+	CLK_U_DEV1_OUT       = 30,
+	CLK_U_XUSB_DEV       = 31,
+};
+
+enum CLK_V_DEV
+{
+	CLK_V_CPUG          = 0,
+	CLK_V_CPULP         = 1, // Reserved.
+	CLK_V_3D2           = 2, // HIDDEN.
+	CLK_V_MSELECT       = 3,
+	CLK_V_TSENSOR       = 4,
+	CLK_V_I2S4          = 5,
+	CLK_V_I2S5          = 6,
+	CLK_V_I2C4          = 7,
+	CLK_V_SPI5          = 8, // HIDDEN.
+	CLK_V_SPI6          = 9, // HIDDEN.
+	CLK_V_AHUB          = 10, // AUDIO.
+	CLK_V_APB2APE       = 11, // APBIF.
+	CLK_V_DAM0          = 12, // HIDDEN.
+	CLK_V_DAM1          = 13, // HIDDEN.
+	CLK_V_DAM2          = 14, // HIDDEN.
+	CLK_V_HDA2CODEC_2X  = 15,
+	CLK_V_ATOMICS       = 16,
+	//CLK_V_            = 17,
+	//CLK_V_            = 18,
+	//CLK_V_            = 19,
+	//CLK_V_            = 20,
+	//CLK_V_            = 21,
+	CLK_V_SPDIF_DOUBLER = 22,
+	CLK_V_ACTMON        = 23,
+	CLK_V_EXTPERIPH1    = 24,
+	CLK_V_EXTPERIPH2    = 25,
+	CLK_V_EXTPERIPH3    = 26,
+	CLK_V_SATA_OOB      = 27,
+	CLK_V_SATA          = 28,
+	CLK_V_HDA           = 29,
+	CLK_V_TZRAM         = 30, // HIDDEN.
+	CLK_V_SE            = 31, // HIDDEN.
+};
+
+enum CLK_W_DEV
+{
+	CLK_W_HDA2HDMICODEC = 0,
+	CLK_W_RESERVED0     = 1, //satacoldrstn
+	CLK_W_PCIERX0       = 2,
+	CLK_W_PCIERX1       = 3,
+	CLK_W_PCIERX2       = 4,
+	CLK_W_PCIERX3       = 5,
+	CLK_W_PCIERX4       = 6,
+	CLK_W_PCIERX5       = 7,
+	CLK_W_CEC           = 8,
+	CLK_W_PCIE2_IOBIST  = 9,
+	CLK_W_EMC_IOBIST    = 10,
+	CLK_W_HDMI_IOBIST   = 11, // HIDDEN.
+	CLK_W_SATA_IOBIST   = 12,
+	CLK_W_MIPI_IOBIST   = 13,
+	CLK_W_XUSB_PADCTL   = 14, // Only reset.
+	CLK_W_XUSB          = 15,
+	CLK_W_CILAB         = 16,
+	CLK_W_CILCD         = 17,
+	CLK_W_CILEF         = 18,
+	CLK_W_DSIA_LP       = 19,
+	CLK_W_DSIB_LP       = 20,
+	CLK_W_ENTROPY       = 21,
+	CLK_W_DDS           = 22, // HIDDEN.
+	//CLK_W_            = 23,
+	CLK_W_DP2           = 24, // HIDDEN.
+	CLK_W_AMX0          = 25, // HIDDEN.
+	CLK_W_ADX0          = 26, // HIDDEN.
+	CLK_W_DVFS          = 27,
+	CLK_W_XUSB_SS       = 28,
+	CLK_W_EMC_LATENCY   = 29,
+	CLK_W_MC1           = 30,
+	//CLK_W_            = 31,
+};
+
+enum CLK_X_DEV
+{
+	CLK_X_SPARE             = 0,
+	CLK_X_DMIC1             = 1,
+	CLK_X_DMIC2             = 2,
+	CLK_X_ETR               = 3,
+	CLK_X_CAM_MCLK          = 4,
+	CLK_X_CAM_MCLK2         = 5,
+	CLK_X_I2C6              = 6,
+	CLK_X_MC_CAPA           = 7, // MC DAISY CHAIN1
+	CLK_X_MC_CBPA           = 8, // MC DAISY CHAIN2
+	CLK_X_MC_CPU            = 9,
+	CLK_X_MC_BBC            = 10,
+	CLK_X_VIM2_CLK          = 11,
+	//CLK_X_                = 12,
+	CLK_X_MIPIBIF           = 13, //RESERVED
+	CLK_X_EMC_DLL           = 14,
+	//CLK_X_                = 15,
+	CLK_X_HDMI_AUDIO        = 16, // HIDDEN.
+	CLK_X_UART_FST_MIPI_CAL = 17,
+	CLK_X_VIC               = 18,
+	//CLK_X_                = 19,
+	CLK_X_ADX1              = 20, // HIDDEN.
+	CLK_X_DPAUX             = 21,
+	CLK_X_SOR0              = 22,
+	CLK_X_SOR1              = 23,
+	CLK_X_GPU               = 24,
+	CLK_X_DBGAPB            = 25,
+	CLK_X_HPLL_ADSP         = 26,
+	CLK_X_PLLP_ADSP         = 27,
+	CLK_X_PLLA_ADSP         = 28,
+	CLK_X_PLLG_REF          = 29,
+	//CLK_X_ = 30,
+	//CLK_X_ = 31,
+};
+
+enum CLK_Y_DEV
+{
+	CLK_Y_SPARE1          = 0,
+	CLK_Y_SDMMC_LEGACY_TM = 1,
+	CLK_Y_NVDEC           = 2,
+	CLK_Y_NVJPG           = 3,
+	CLK_Y_AXIAP           = 4,
+	CLK_Y_DMIC3           = 5,
+	CLK_Y_APE             = 6,
+	CLK_Y_ADSP            = 7,
+	CLK_Y_MC_CDPA         = 8, // MC DAISY CHAIN4
+	CLK_Y_MC_CCPA         = 9, // MC DAISY CHAIN3
+	CLK_Y_MAUD            = 10,
+	//CLK_Y_              = 11,
+	CLK_Y_SATA_USB_UPHY   = 12, // Only reset.
+	CLK_Y_PEX_USB_UPHY    = 13, // Only reset.
+	CLK_Y_TSECB           = 14,
+	CLK_Y_DPAUX1          = 15,
+	CLK_Y_VI_I2C          = 16,
+	CLK_Y_HSIC_TRK        = 17,
+	CLK_Y_USB2_TRK        = 18,
+	CLK_Y_QSPI            = 19,
+	CLK_Y_UARTAPE         = 20,
+	CLK_Y_ADSPINTF        = 21, // Only reset.
+	CLK_Y_ADSPPERIPH      = 22, // Only reset.
+	CLK_Y_ADSPDBG         = 23, // Only reset.
+	CLK_Y_ADSPWDT         = 24, // Only reset.
+	CLK_Y_ADSPSCU         = 25, // Only reset.
+	CLK_Y_ADSPNEON        = 26,
+	CLK_Y_NVENC           = 27,
+	CLK_Y_IQC2            = 28,
+	CLK_Y_IQC1            = 29,
+	CLK_Y_SOR_SAFE        = 30,
+	CLK_Y_PLLP_OUT_CPU    = 31,
+};
 
 /*! Generic clock descriptor. */
 typedef struct _clock_t
 {
-	u32 reset;
+	u16 reset;
-	u32 enable;
+	u16 enable;
-	u32 source;
+	u16 source;
 	u8 index;
 	u8 clk_src;
 	u8 clk_div;
@@ -213,12 +659,19 @@ void clock_enable_coresight();
 void clock_disable_coresight();
 void clock_enable_pwm();
 void clock_disable_pwm();
+void clock_enable_pllx();
 void clock_enable_pllc(u32 divn);
 void clock_disable_pllc();
+void clock_enable_pllu();
+void clock_disable_pllu();
+void clock_enable_utmipll();
 void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val);
 void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type);
 int  clock_sdmmc_is_not_reset_and_enabled(u32 id);
 void clock_sdmmc_enable(u32 id, u32 val);
 void clock_sdmmc_disable(u32 id);
 
+u32 clock_get_osc_freq();
+u32 clock_get_dev_freq(clock_pto_id_t id);
+
 #endif

bdk/soc/fuse.c

@@ -2,7 +2,8 @@
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 shuffle2
  * Copyright (c) 2018 balika011
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2021 CTCaer
+ * Copyright (c) 2021 shchmue
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -19,10 +20,12 @@
 
 #include <string.h>
 
+#include <sec/se.h>
+#include <sec/se_t210.h>
 #include <soc/fuse.h>
+#include <soc/hw_init.h>
 #include <soc/t210.h>
-
+#include <utils/types.h>
-#define ARRAYSIZE(x) (sizeof(x) / sizeof(*x))
 
 static const u32 evp_thunk_template[] = {
 	0xe92d0007, //   STMFD   SP!, {R0-R2}
@@ -62,12 +65,101 @@ u32 fuse_read_odm(u32 idx)
 
 u32 fuse_read_odm_keygen_rev()
 {
-	if ((fuse_read_odm(4) & 0x800) && fuse_read_odm(0) == 0x8E61ECAE && fuse_read_odm(1) == 0xF2BA3BB2)
+	bool has_new_keygen;
+
+	// Check if it has new keygen.
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
+		has_new_keygen = true;
+	else
+		has_new_keygen = (fuse_read_odm(4) & 0x800) && fuse_read_odm(0) == 0x8E61ECAE && fuse_read_odm(1) == 0xF2BA3BB2;
+
+	if (has_new_keygen)
 		return (fuse_read_odm(2) & 0x1F);
 
 	return 0;
 }
 
+u32 fuse_read_bootrom_rev()
+{
+	u32 rev = FUSE(FUSE_SOC_SPEEDO_1_CALIB);
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
+		return rev;
+	else
+		return rev | (1 << 12);
+}
+
+u32 fuse_read_dramid(bool raw_id)
+{
+	u32 dramid = (fuse_read_odm(4) & 0xF8) >> 3;
+
+	if (raw_id)
+		return dramid;
+
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
+	{
+		if (dramid > 6)
+			dramid = 0;
+	}
+	else
+	{
+		if (dramid > 28)
+			dramid = 8;
+	}
+
+	return dramid;
+}
+
+u32 fuse_read_hw_state()
+{
+	if ((fuse_read_odm(4) & 3) != 3)
+		return FUSE_NX_HW_STATE_PROD;
+	else
+		return FUSE_NX_HW_STATE_DEV;
+}
+
+u32 fuse_read_hw_type()
+{
+	if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
+	{
+		switch ((fuse_read_odm(4) & 0xF0000) >> 16)
+		{
+		case 2:
+			return FUSE_NX_HW_TYPE_HOAG;
+		case 4:
+			return FUSE_NX_HW_TYPE_AULA;
+		case 1:
+		default:
+			return FUSE_NX_HW_TYPE_IOWA;
+		}
+	}
+
+	return FUSE_NX_HW_TYPE_ICOSA;
+}
+
+int fuse_set_sbk()
+{
+	if (FUSE(FUSE_PRIVATE_KEY0) != 0xFFFFFFFF)
+	{
+		// Read SBK from fuses.
+		u32 sbk[4] = {
+			FUSE(FUSE_PRIVATE_KEY0),
+			FUSE(FUSE_PRIVATE_KEY1),
+			FUSE(FUSE_PRIVATE_KEY2),
+			FUSE(FUSE_PRIVATE_KEY3)
+		};
+
+		// Set SBK to slot 14.
+		se_aes_key_set(14, sbk, SE_KEY_128_SIZE);
+
+		// Lock SBK from being read.
+		se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
+
+		return 1;
+	}
+
+	return 0;
+}
+
 void fuse_wait_idle()
 {
 	u32 ctrl;
@@ -82,12 +174,15 @@ u32 fuse_read(u32 addr)
 	FUSE(FUSE_ADDR) = addr;
 	FUSE(FUSE_CTRL) = (FUSE(FUSE_ADDR) & ~FUSE_CMD_MASK) | FUSE_READ;
 	fuse_wait_idle();
+
 	return FUSE(FUSE_RDATA);
 }
 
 void fuse_read_array(u32 *words)
 {
-	for (u32 i = 0; i < 192; i++)
+	u32 array_size = (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01) ? 256 : 192;
+
+	for (u32 i = 0; i < array_size; i++)
 		words[i] = fuse_read(i);
 }
 
@@ -133,7 +228,7 @@ static int _patch_hash_one(u32 *word)
 	{
 		return 3;
 	}
-	for (u32 i = 0; i < ARRAYSIZE(hash_vals); i++)
+	for (u32 i = 0; i < ARRAY_SIZE(hash_vals); i++)
 	{
 		if (hash_vals[i] == hash)
 		{
@@ -222,7 +317,7 @@ int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value))
 	while (word_count)
 	{
 		total_read += word_count;
-		if (total_read >= ARRAYSIZE(words))
+		if (total_read >= ARRAY_SIZE(words))
 		{
 			break;
 		}
@@ -279,7 +374,7 @@ int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len)
 	while (word_count)
 	{
 		total_read += word_count;
-		if (total_read >= ARRAYSIZE(words))
+		if (total_read >= ARRAY_SIZE(words))
 		{
 			break;
 		}
@@ -328,8 +423,8 @@ int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len)
 
 bool fuse_check_patched_rcm()
 {
-	// Check if XUSB in use.
+	// Check if XUSB in use or Tegra X1+.
-	if (FUSE(FUSE_RESERVED_SW) & (1<<7))
+	if (FUSE(FUSE_RESERVED_SW) & (1<<7) || hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
 		return true;
 
 	// Check if RCM is ipatched.

bdk/soc/fuse.h

@@ -2,6 +2,8 @@
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 shuffle2
  * Copyright (c) 2018 balika011
+ * Copyright (c) 2019-2021 CTCaer
+ * Copyright (c) 2021 shchmue
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -66,6 +68,8 @@
 #define FUSE_GPU_IDDQ_CALIB	0x228
 #define FUSE_USB_CALIB_EXT 0x350
 
+#define FUSE_RESERVED_ODM28_T210B01 0x240
+
 /*! Fuse commands. */
 #define FUSE_READ 0x1
 #define FUSE_WRITE 0x2
@@ -75,9 +79,28 @@
 /*! Fuse cache registers. */
 #define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
 
+enum
+{
+	FUSE_NX_HW_TYPE_ICOSA,
+	FUSE_NX_HW_TYPE_IOWA,
+	FUSE_NX_HW_TYPE_HOAG,
+	FUSE_NX_HW_TYPE_AULA
+};
+
+enum
+{
+	FUSE_NX_HW_STATE_PROD,
+	FUSE_NX_HW_STATE_DEV
+};
+
 void fuse_disable_program();
 u32  fuse_read_odm(u32 idx);
 u32  fuse_read_odm_keygen_rev();
+u32  fuse_read_bootrom_rev();
+u32  fuse_read_dramid(bool raw_id);
+u32  fuse_read_hw_state();
+u32  fuse_read_hw_type();
+int  fuse_set_sbk();
 void fuse_wait_idle();
 int  fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value));
 int  fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len);

bdk/soc/gpio.c

@@ -18,23 +18,23 @@
 #include <soc/gpio.h>
 #include <soc/t210.h>
 
-#define GPIO_BANK_IDX(port)      (port >> 2)
+#define GPIO_BANK_IDX(port)       ((port) >> 2)
 
-#define GPIO_CNF_OFFSET(port)     (0x00 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_CNF_OFFSET(port)     (0x00 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_OE_OFFSET(port)      (0x10 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OE_OFFSET(port)      (0x10 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_OUT_OFFSET(port)     (0x20 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OUT_OFFSET(port)     (0x20 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_IN_OFFSET(port)      (0x30 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_IN_OFFSET(port)      (0x30 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_INT_STA_OFFSET(port) (0x40 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_STA_OFFSET(port) (0x40 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_INT_ENB_OFFSET(port) (0x50 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_ENB_OFFSET(port) (0x50 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_INT_LVL_OFFSET(port) (0x60 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_LVL_OFFSET(port) (0x60 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_INT_CLR_OFFSET(port) (0x70 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_CLR_OFFSET(port) (0x70 + (((port) >> 2) << 8) + (((port) % 4) << 2))
 
-#define GPIO_CNF_MASKED_OFFSET(port)     (0x80 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_CNF_MASKED_OFFSET(port)     (0x80 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_OE_MASKED_OFFSET(port)      (0x90 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OE_MASKED_OFFSET(port)      (0x90 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_OUT_MASKED_OFFSET(port)     (0xA0 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OUT_MASKED_OFFSET(port)     (0xA0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_INT_STA_MASKED_OFFSET(port) (0xC0 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_STA_MASKED_OFFSET(port) (0xC0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_INT_ENB_MASKED_OFFSET(port) (0xD0 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_ENB_MASKED_OFFSET(port) (0xD0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
-#define GPIO_INT_LVL_MASKED_OFFSET(port) (0xE0 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_LVL_MASKED_OFFSET(port) (0xE0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
 
 #define GPIO_IRQ_BANK1 32
 #define GPIO_IRQ_BANK2 33

bdk/soc/gpio.h

@@ -41,14 +41,14 @@
 #define GPIO_ANY_EDGE_CHANGE 1
 
 /*! GPIO pins (0-7 for each port). */
-#define GPIO_PIN_0 (1 << 0)
+#define GPIO_PIN_0 BIT(0)
-#define GPIO_PIN_1 (1 << 1)
+#define GPIO_PIN_1 BIT(1)
-#define GPIO_PIN_2 (1 << 2)
+#define GPIO_PIN_2 BIT(2)
-#define GPIO_PIN_3 (1 << 3)
+#define GPIO_PIN_3 BIT(3)
-#define GPIO_PIN_4 (1 << 4)
+#define GPIO_PIN_4 BIT(4)
-#define GPIO_PIN_5 (1 << 5)
+#define GPIO_PIN_5 BIT(5)
-#define GPIO_PIN_6 (1 << 6)
+#define GPIO_PIN_6 BIT(6)
-#define GPIO_PIN_7 (1 << 7)
+#define GPIO_PIN_7 BIT(7)
 
 /*! GPIO ports (A-EE). */
 #define GPIO_PORT_A 0

bdk/soc/hw_init.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,7 +18,7 @@
 #include <string.h>
 
 #include <soc/hw_init.h>
-#include <gfx/di.h>
+#include <display/di.h>
 #include <input/joycon.h>
 #include <input/touch.h>
 #include <sec/se.h>
@@ -42,11 +42,23 @@
 #include <storage/nx_sd.h>
 #include <storage/sdmmc.h>
 #include <thermal/fan.h>
+#include <thermal/tmp451.h>
 #include <utils/util.h>
 
 extern boot_cfg_t b_cfg;
 extern volatile nyx_storage_t *nyx_str;
 
+u32 hw_rst_status;
+u32 hw_rst_reason;
+
+u32 hw_get_chip_id()
+{
+	if (((APB_MISC(APB_MISC_GP_HIDREV) >> 4) & 0xF) >= GP_HIDREV_MAJOR_T210B01)
+		return GP_HIDREV_MAJOR_T210B01;
+	else
+		return GP_HIDREV_MAJOR_T210;
+}
+
 /*
  * CLK_OSC - 38.4 MHz crystal.
  * CLK_M   - 19.2 MHz (osc/2).
@@ -56,7 +68,7 @@ extern volatile nyx_storage_t *nyx_str;
  * PCLK    - 68MHz  init (-> 136MHz -> OC/4).
  */
 
-void _config_oscillators()
+static void _config_oscillators()
 {
 	CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
 	SYSCTR0(SYSCTR0_CNTFID0) = 19200000;             // Set counter frequency.
@@ -73,35 +85,45 @@ void _config_oscillators()
 
 	PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz)
 
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0;              // Set SCLK div to 1.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0;              // Set BPMP/SCLK div to 1.
-	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444;  // Set clk source to Run and PLLP_OUT2 (204MHz).
+	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444;  // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz).
 	CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
 	CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2;             // Set HCLK div to 1 and PCLK div to 3.
 }
 
-void _config_gpios()
+// The uart is skipped for Copper, Hoag and Calcio. Used in Icosa, Iowa and Aula.
+static void _config_gpios(bool nx_hoag)
+{
+	// Clamp inputs when tristated.
+	APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
+
+	if (!nx_hoag)
 	{
 		PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
 		PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
 
-	// Set Joy-Con IsAttached direction.
+		// Set pin mode for UARTB/C TX pins.
-	PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
-	PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
-
-	// Set pin mode for Joy-Con IsAttached and UARTB/C TX pins.
 #if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B
 		gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
 #endif
 #if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C
 		gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
 #endif
+
+		// Enable input logic for UARTB/C TX pins.
+		gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
+		gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
+	}
+
+	// Set Joy-Con IsAttached direction.
+	PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
+	PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
+
 	// Set Joy-Con IsAttached mode.
 	gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
 	gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
 
-	// Enable input logic for Joy-Con IsAttached and UARTB/C TX pins.
+	// Enable input logic for Joy-Con IsAttached pins.
-	gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
-	gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
 	gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
 	gpio_output_enable(GPIO_PORT_H, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
 
@@ -120,27 +142,28 @@ void _config_gpios()
 	// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
 }
 
-void _config_pmc_scratch()
+static void _config_pmc_scratch()
 {
 	PMC(APBDEV_PMC_SCRATCH20)  &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
 	PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
 	PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
 }
 
-void _mbist_workaround()
+static void _mbist_workaround()
 {
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
+	// Make sure Audio clocks are enabled before accessing I2S.
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 <<  6); // Enable APE clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE);
 
 	// Set mux output to SOR1 clock switch.
 	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF;
 	// Enabled PLLD and set csi to PLLD for test pattern generation.
 	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000;
 
-	// Clear per-clock resets.
+	// Clear per-clock resets for APE/VIC/HOST1X/DISP1.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40;       // Clear reset APE.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = BIT(CLK_Y_APE);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000;    // Clear reset VIC.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = BIT(CLK_X_VIC);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
 	usleep(2);
 
 	// I2S channels to master and disable SLCG.
@@ -159,20 +182,59 @@ void _mbist_workaround()
 	VIC(0x8C) = 0xFFFFFFFF;
 	usleep(2);
 
-	// Set per-clock reset.
+	// Set per-clock reset for APE/VIC/HOST1X/DISP1.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40;       // Set reset APE.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = BIT(CLK_Y_APE);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1x.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000;    // Set reset VIC.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = BIT(CLK_X_VIC);
 
 	// Enable specific clocks and disable all others.
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0;       // Enable clock PMC, FUSE.
+	// CLK L Devices.
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130; // Enable clock RTC, TMR, GPIO, BPMP_CACHE.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) =
-	//CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80400130; // Keep USBD ON.
+		BIT(CLK_H_PMC) |
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200;  // Enable clock CSITE, IRAMA, IRAMB, IRAMC, IRAMD, BPMP_CACHE_RAM.
+		BIT(CLK_H_FUSE);
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = 0x80400808; // Enable clock MSELECT, APB2APE, SPDIF_DOUBLER, SE.
+	// CLK H Devices.
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC; // Enable clock PCIERX0, PCIERX1, PCIERX2, PCIERX3, PCIERX4, PCIERX5, ENTROPY, MC1.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) =
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780; // Enable clock MC_CAPA, MC_CAPB, MC_CPU, MC_BBC, DBGAPB, HPLL_ADSP, PLLG_REF.
+		BIT(CLK_L_RTC)  |
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300;      // Enable clock MC_CDPA, MC_CCPA.
+		BIT(CLK_L_TMR)  |
+		BIT(CLK_L_GPIO) |
+		BIT(CLK_L_BPMP_CACHE_CTRL);
+	// CLK U Devices.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) =
+		BIT(CLK_U_CSITE) |
+		BIT(CLK_U_IRAMA) |
+		BIT(CLK_U_IRAMB) |
+		BIT(CLK_U_IRAMC) |
+		BIT(CLK_U_IRAMD) |
+		BIT(CLK_U_BPMP_CACHE_RAM);
+	// CLK V Devices.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) =
+		BIT(CLK_V_MSELECT)       |
+		BIT(CLK_V_APB2APE)       |
+		BIT(CLK_V_SPDIF_DOUBLER) |
+		BIT(CLK_V_SE);
+	// CLK W Devices.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) =
+		BIT(CLK_W_PCIERX0) |
+		BIT(CLK_W_PCIERX1) |
+		BIT(CLK_W_PCIERX2) |
+		BIT(CLK_W_PCIERX3) |
+		BIT(CLK_W_PCIERX4) |
+		BIT(CLK_W_PCIERX5) |
+		BIT(CLK_W_ENTROPY) |
+		BIT(CLK_W_MC1);
+	// CLK X Devices.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) =
+		BIT(CLK_X_MC_CAPA)  |
+		BIT(CLK_X_MC_CBPA)  |
+		BIT(CLK_X_MC_CPU)   |
+		BIT(CLK_X_MC_BBC)   |
+		BIT(CLK_X_GPU)      |
+		BIT(CLK_X_DBGAPB)   |
+		BIT(CLK_X_PLLG_REF);
+	// CLK Y Devices.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) =
+		BIT(CLK_Y_MC_CDPA) |
+		BIT(CLK_Y_MC_CCPA);
 
 	// Disable clock gate overrides.
 	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0;
@@ -189,63 +251,56 @@ void _mbist_workaround()
 	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC)  = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000;  // Set clock source to PLLP_OUT.
 }
 
-void _config_se_brom()
+static void _config_se_brom()
 {
-	// Enable fuse clock.
+	// Enable Fuse visibility.
 	clock_enable_fuse(true);
 
-	// Skip SBK/SSK if sept was run.
+	// Try to set SBK from fuses. If patched, skip.
-	if (!(b_cfg.boot_cfg & BOOT_CFG_SEPT_RUN))
+	fuse_set_sbk();
-	{
-		// Bootrom part we skipped.
-		u32 sbk[4] = {
-			FUSE(FUSE_PRIVATE_KEY0),
-			FUSE(FUSE_PRIVATE_KEY1),
-			FUSE(FUSE_PRIVATE_KEY2),
-			FUSE(FUSE_PRIVATE_KEY3)
-		};
-		// Set SBK to slot 14.
-		se_aes_key_set(14, sbk, 0x10);
-
-		// Lock SBK from being read.
-		se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
 
 	// Lock SSK (although it's not set and unused anyways).
-		se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG);
+	// se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG);
-	}
 
 	// This memset needs to happen here, else TZRAM will behave weirdly later on.
-	memset((void *)TZRAM_BASE, 0, 0x10000);
+	memset((void *)TZRAM_BASE, 0, SZ_64K);
 	PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
-	SE(SE_INT_STATUS_REG_OFFSET) = 0x1F;
+	SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts.
 
-	// Clear the boot reason to avoid problems later
+	// Save reset reason.
+	hw_rst_status = PMC(APBDEV_PMC_SCRATCH200);
+	hw_rst_reason = PMC(APBDEV_PMC_RST_STATUS) & PMC_RST_STATUS_MASK;
+
+	// Clear the boot reason to avoid problems later.
 	PMC(APBDEV_PMC_SCRATCH200) = 0x0;
 	PMC(APBDEV_PMC_RST_STATUS) = 0x0;
 	APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
 }
 
-void _config_regulators()
+static void _config_regulators(bool tegra_t210)
 {
+	// Set RTC/AO domain to POR voltage.
+	if (tegra_t210)
+		max7762x_regulator_set_voltage(REGULATOR_LDO4, 1000000);
+
 	// Disable low battery shutdown monitor.
 	max77620_low_battery_monitor_config(false);
 
 	// Disable SDMMC1 IO power.
-	gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
+	gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW);
-	max77620_regulator_enable(REGULATOR_LDO2, 0);
+	max7762x_regulator_enable(REGULATOR_LDO2, false);
 	sd_power_cycle_time_start = get_tmr_ms();
 
 	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
 	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
-		(1 << 6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
+		MAX77620_ONOFFCNFG1_RSVD | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
 
-	// Configure all Flexible Power Sequencers.
+	if (tegra_t210)
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
+	{
-		(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
+		// Configure all Flexible Power Sequencers for MAX77620.
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1,
+		i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
-		(7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
+		i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2,
+		i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
-		(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
 		max77620_regulator_config_fps(REGULATOR_LDO4);
 		max77620_regulator_config_fps(REGULATOR_LDO8);
 		max77620_regulator_config_fps(REGULATOR_SD0);
@@ -256,96 +311,120 @@ void _config_regulators()
 			(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
 
 		// Set vdd_core voltage to 1.125V.
-	max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
+		max7762x_regulator_set_voltage(REGULATOR_SD0, 1125000);
 
-	// Fix CPU/GPU after a L4T warmboot.
+		// Fix CPU/GPU after L4T warmboot.
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
+		max77620_config_gpio(5, MAX77620_GPIO_OUTPUT_DISABLE);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
+		max77620_config_gpio(6, MAX77620_GPIO_OUTPUT_DISABLE);
 
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
+		// Set POR configuration.
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
+		max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_POR_CFG);
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
+		max77621_config_default(REGULATOR_GPU0, MAX77621_CTRL_POR_CFG);
-	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
+	}
-		MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
+	else // Tegra X1+ set vdd_core voltage to 1.05V.
-		MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
+		max7762x_regulator_set_voltage(REGULATOR_SD0, 1050000);
-
-	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
-	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
-	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
-	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL2_REG,
-		MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
-		MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
 }
 
-void config_hw()
+void hw_init()
 {
+	// Get Chip ID.
+	bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
+	bool nx_hoag = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG;
+
 	// Bootrom stuff we skipped by going through rcm.
 	_config_se_brom();
 	//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
 	SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN.
 	PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC;
 
+	// Perform Memory Built-In Self Test WAR if T210.
+	if (tegra_t210)
 		_mbist_workaround();
+
+	// Enable Security Engine clock.
 	clock_enable_se();
 
-	// Enable fuse clock.
+	// Enable Fuse visibility.
 	clock_enable_fuse(true);
 
-	// Disable fuse programming.
+	// Disable Fuse programming.
 	fuse_disable_program();
 
+	// Enable clocks to Memory controllers and disable AHB redirect.
 	mc_enable();
 
+	// Initialize counters, CLKM, BPMP and other clocks based on 38.4MHz oscillator.
 	_config_oscillators();
-	APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
+
-	_config_gpios();
+	// Initialize pin configuration.
+	_config_gpios(nx_hoag);
 
 #ifdef DEBUG_UART_PORT
 	clock_enable_uart(DEBUG_UART_PORT);
-	uart_init(DEBUG_UART_PORT, 115200);
+	uart_init(DEBUG_UART_PORT, DEBUG_UART_BAUDRATE);
+	uart_invert(DEBUG_UART_PORT, DEBUG_UART_INVERT, UART_INVERT_TXD);
 #endif
 
+	// Enable Dynamic Voltage and Frequency Scaling device clock.
 	clock_enable_cl_dvfs();
 
+	// Enable clocks to I2C1 and I2CPWR.
 	clock_enable_i2c(I2C_1);
 	clock_enable_i2c(I2C_5);
 
+	// Enable clock to TZRAM.
 	clock_enable_tzram();
 
-	i2c_init(I2C_1);
+	// Initialize I2C5, mandatory for PMIC.
 	i2c_init(I2C_5);
 
+	//! TODO: Why? Device is NFC MCU on Lite.
+	if (nx_hoag)
+	{
+		max7762x_regulator_set_voltage(REGULATOR_LDO8, 2800000);
+		max7762x_regulator_enable(REGULATOR_LDO8, true);
+	}
+
+	// Initialize I2C1 for various power related devices.
+	i2c_init(I2C_1);
+
+	// Initialize various regulators based on Erista/Mariko platform.
+	_config_regulators(tegra_t210);
+
 	// Enable charger in case it's disabled.
 	bq24193_enable_charger();
 
-	_config_regulators();
-
 	_config_pmc_scratch(); // Missing from 4.x+
 
-	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz).
+	// Set BPMP/SCLK to PLLP_OUT (408MHz).
+	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333;
 
+	// Disable TZRAM shutdown control and lock the regs.
+	if (!tegra_t210)
+	{
+		PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= 0xFFFFFFFE;
+		PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = 3;
+		PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = 3;
+	}
+
+	// Initialize External memory controller and configure DRAM parameters.
 	sdram_init();
 
 	bpmp_mmu_enable();
-	mc_enable_ahb_redirect();
-
-	// Clear flags from PMC_SCRATCH0
-	PMC(APBDEV_PMC_SCRATCH0) &= ~PMC_SCRATCH0_MODE_PAYLOAD;
 }
 
-void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
+void hw_reinit_workaround(bool coreboot, u32 bl_magic)
 {
 	// Disable BPMP max clock.
 	bpmp_clk_rate_set(BPMP_CLK_NORMAL);
 
 #ifdef NYX
-	// Deinit touchscreen, 5V regulators and Joy-Con.
+	// Disable temperature sensor, touchscreen, 5V regulators and Joy-Con.
-	touch_power_off();
+	tmp451_end();
 	set_fan_duty(0);
+	touch_power_off();
 	jc_deinit();
-	regulator_disable_5v(REGULATOR_5V_ALL);
+	regulator_5v_disable(REGULATOR_5V_ALL);
-	clock_disable_uart(UART_B);
-	clock_disable_uart(UART_C);
 #endif
 
 	// Flush/disable MMU cache and set DRAM clock to 204MHz.
@@ -354,13 +433,13 @@ void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
 	nyx_str->mtc_cfg.init_done = 0;
 
 	// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
-	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 <<  6); // Enable APE clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE);
 
-	if (extra_reconfig)
+	// Do coreboot mitigations.
+	if (coreboot)
 	{
 		msleep(10);
-		PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN;
 
 		clock_disable_cl_dvfs();
 
@@ -369,15 +448,29 @@ void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
 		gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
 		gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO);
 		gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO);
+
+		// Reinstate SD controller power.
+		PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN);
 	}
 
-	// Power off display.
+	// Seamless display or display power off.
+	switch (bl_magic)
+	{
+	case BL_MAGIC_CRBOOT_SLD:;
+		// Set pwm to 0%, switch to gpio mode and restore pwm duty.
+		u32 brightness = display_get_backlight_brightness();
+		display_backlight_brightness(0, 1000);
+		gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_GPIO);
+		display_backlight_brightness(brightness, 0);
+		break;
+	default:
 		display_end();
+	}
 
 	// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
-	if (magic == 0xBAADF00D)
+	if (bl_magic == BL_MAGIC_BROKEN_HWI)
 	{
-		CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) |= (1 << 22);
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD);
 		sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0);
 		clock_disable_cl_dvfs();
 

bdk/soc/hw_init.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -20,7 +20,14 @@
 
 #include <utils/types.h>
 
-void config_hw();
+#define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0.
-void reconfig_hw_workaround(bool extra_reconfig, u32 magic);
+#define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit.
+
+extern u32 hw_rst_status;
+extern u32 hw_rst_reason;
+
+void hw_init();
+void hw_reinit_workaround(bool coreboot, u32 magic);
+u32  hw_get_chip_id();
 
 #endif

bdk/soc/i2c.c

@@ -20,31 +20,98 @@
 #include <soc/i2c.h>
 #include <utils/util.h>
 
+#define I2C_PACKET_PROT_I2C  BIT(4)
+#define I2C_HEADER_CONT_XFER BIT(15)
+#define I2C_HEADER_REP_START BIT(16)
+#define I2C_HEADER_IE_ENABLE BIT(17)
+#define I2C_HEADER_READ      BIT(19)
+
+#define I2C_CNFG              (0x00 / 4)
+#define  CMD1_WRITE           (0 << 6)
+#define  CMD1_READ            BIT(6)
+#define  NORMAL_MODE_GO       BIT(9)
+#define  PACKET_MODE_GO       BIT(10)
+#define  NEW_MASTER_FSM       BIT(11)
+#define  DEBOUNCE_CNT_4T      (2 << 12)
+
+#define I2C_CMD_ADDR0         (0x04 / 4)
+#define  ADDR0_WRITE          0
+#define  ADDR0_READ           1
+
+#define I2C_CMD_DATA1         (0x0C / 4)
+#define I2C_CMD_DATA2         (0x10 / 4)
+
+#define I2C_STATUS            (0x1C / 4)
+#define  I2C_STATUS_NOACK     (0xF << 0)
+#define  I2C_STATUS_BUSY      BIT(8)
+
+#define I2C_TX_FIFO           (0x50 / 4)
+#define I2C_RX_FIFO           (0x54 / 4)
+
+#define I2C_FIFO_CONTROL      (0x5C / 4)
+#define  RX_FIFO_FLUSH        BIT(0)
+#define  TX_FIFO_FLUSH        BIT(1)
+
+#define I2C_FIFO_STATUS       (0x60 / 4)
+#define  RX_FIFO_FULL_CNT     (0xF << 0)
+#define  TX_FIFO_EMPTY_CNT    (0xF << 4)
+
+#define I2C_INT_EN            (0x64 / 4)
+#define I2C_INT_STATUS        (0x68 / 4)
+#define I2C_INT_SOURCE        (0x70 / 4)
+#define  RX_FIFO_DATA_REQ     BIT(0)
+#define  TX_FIFO_DATA_REQ     BIT(1)
+#define  ARB_LOST             BIT(2)
+#define  NO_ACK               BIT(3)
+#define  RX_FIFO_UNDER        BIT(4)
+#define  TX_FIFO_OVER         BIT(5)
+#define  ALL_PACKETS_COMPLETE BIT(6)
+#define  PACKET_COMPLETE      BIT(7)
+#define  BUS_CLEAR_DONE       BIT(11)
+
+#define I2C_CLK_DIVISOR       (0x6C / 4)
+
+#define I2C_BUS_CLEAR_CONFIG  (0x84 / 4)
+#define  BC_ENABLE            BIT(0)
+#define  BC_TERMINATE         BIT(1)
+
+#define I2C_BUS_CLEAR_STATUS  (0x88 / 4)
+
+#define I2C_CONFIG_LOAD       (0x8C / 4)
+#define  MSTR_CONFIG_LOAD     BIT(0)
+#define  TIMEOUT_CONFIG_LOAD  BIT(2)
+
 static const u32 i2c_addrs[] = {
-	0x7000C000, 0x7000C400, 0x7000C500,
+	0x7000C000, // I2C_1.
-	0x7000C700, 0x7000D000, 0x7000D100
+	0x7000C400, // I2C_2.
+	0x7000C500, // I2C_3.
+	0x7000C700, // I2C_4.
+	0x7000D000, // I2C_5.
+	0x7000D100  // I2C_6.
 };
 
-static void _i2c_wait(vu32 *base)
+static void _i2c_load_cfg_wait(vu32 *base)
 {
-	base[I2C_CONFIG_LOAD] = 0x25;
+	base[I2C_CONFIG_LOAD] = BIT(5) | TIMEOUT_CONFIG_LOAD | MSTR_CONFIG_LOAD;
 	for (u32 i = 0; i < 20; i++)
 	{
 		usleep(1);
-		if (!(base[I2C_CONFIG_LOAD] & 1))
+		if (!(base[I2C_CONFIG_LOAD] & MSTR_CONFIG_LOAD))
 			break;
 	}
 }
 
-static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
+static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
 {
 	if (size > 8)
 		return 0;
 
 	u32 tmp = 0;
 
-	vu32 *base = (vu32 *)i2c_addrs[idx];
+	vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
-	base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode).
+
+	// Set device address and send mode.
+	base[I2C_CMD_ADDR0] = dev_addr << 1 | ADDR0_WRITE;
 
 	if (size > 4)
 	{
@@ -60,44 +127,55 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
 		base[I2C_CMD_DATA1] = tmp; //Set value.
 	}
 
-	base[I2C_CNFG] = ((size - 1) << 1) | 0x2800; //Set size and send mode.
+	// Set size and send mode.
-	_i2c_wait(base);                             //Kick transaction.
+	base[I2C_CNFG] = ((size - 1) << 1) | DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_WRITE;
 
-	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
+	// Load configuration.
+	_i2c_load_cfg_wait(base);
 
-	u32 timeout = get_tmr_ms() + 1500;
+	// Initiate transaction on normal mode.
-	while (base[I2C_STATUS] & 0x100)
+	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
+
+	u32 timeout = get_tmr_us() + 200000; // Actual for max 8 bytes at 100KHz is 0.74ms.
+	while (base[I2C_STATUS] & I2C_STATUS_BUSY)
 	{
-		if (get_tmr_ms() > timeout)
+		if (get_tmr_us() > timeout)
 			return 0;
 	}
 
-	if (base[I2C_STATUS] << 28)
+	if (base[I2C_STATUS] & I2C_STATUS_NOACK)
 		return 0;
 
 	return 1;
 }
 
-static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
+static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 {
 	if (size > 8)
 		return 0;
 
-	vu32 *base = (vu32 *)i2c_addrs[idx];
+	vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
-	base[I2C_CMD_ADDR0] = (x << 1) | 1;          // Set x (recv mode).
-	base[I2C_CNFG] = ((size - 1) << 1) | 0x2840; // Set size and recv mode.
-	_i2c_wait(base);                             // Kick transaction.
 
-	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
+	// Set device address and recv mode.
+	base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
 
-	u32 timeout = get_tmr_ms() + 1500;
+	// Set size and recv mode.
-	while (base[I2C_STATUS] & 0x100)
+	base[I2C_CNFG] = ((size - 1) << 1) | DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_READ;
+
+	// Load configuration.
+	_i2c_load_cfg_wait(base);
+
+	// Initiate transaction on normal mode.
+	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
+
+	u32 timeout = get_tmr_us() + 200000; // Actual for max 8 bytes at 100KHz is 0.74ms.
+	while (base[I2C_STATUS] & I2C_STATUS_BUSY)
 	{
-		if (get_tmr_ms() > timeout)
+		if (get_tmr_us() > timeout)
 			return 0;
 	}
 
-	if (base[I2C_STATUS] << 28)
+	if (base[I2C_STATUS] & I2C_STATUS_NOACK)
 		return 0;
 
 	u32 tmp = base[I2C_CMD_DATA1]; // Get LS value.
@@ -113,60 +191,234 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
 	return 1;
 }
 
-void i2c_init(u32 idx)
+static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 {
-	vu32 *base = (vu32 *)i2c_addrs[idx];
+	if (size > 32)
+		return 0;
 
-	base[I2C_CLK_DIVISOR_REGISTER] = 0x50001;
+	int res = 0;
-	base[I2C_BUS_CLEAR_CONFIG] = 0x90003;
+
-	_i2c_wait(base);
+	vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
+
+	// Enable interrupts.
+	base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
+		ARB_LOST | TX_FIFO_OVER | RX_FIFO_UNDER | TX_FIFO_DATA_REQ;
+	base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
+
+	// Set device address and recv mode.
+	base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
+
+	// Set recv mode.
+	base[I2C_CNFG] = DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_WRITE;
+
+	// Set and flush FIFO.
+	base[I2C_FIFO_CONTROL] = RX_FIFO_FLUSH | TX_FIFO_FLUSH;
+
+	// Load configuration.
+	_i2c_load_cfg_wait(base);
+
+	// Initiate transaction on packet mode.
+	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | PACKET_MODE_GO;
+
+	u32 hdr[3];
+	hdr[0] = I2C_PACKET_PROT_I2C;
+	hdr[1] = size - 1;
+	hdr[2] = I2C_HEADER_IE_ENABLE | I2C_HEADER_CONT_XFER | (dev_addr << 1);
+
+	// Send header with request.
+	base[I2C_TX_FIFO] = hdr[0];
+	base[I2C_TX_FIFO] = hdr[1];
+	base[I2C_TX_FIFO] = hdr[2];
+
+	u32 timeout = get_tmr_ms() + 400;
+	while (size)
+	{
+		if (base[I2C_FIFO_STATUS] & TX_FIFO_EMPTY_CNT)
+		{
+			u32 tmp = 0;
+			u32 snd_size = MIN(size, 4);
+			memcpy(&tmp, buf, snd_size);
+			base[I2C_TX_FIFO] = tmp;
+			buf += snd_size;
+			size -= snd_size;
+		}
+
+		if (get_tmr_ms() > timeout)
+		{
+			res = 1;
+			break;
+		}
+	}
+
+	if (base[I2C_STATUS] & I2C_STATUS_NOACK || base[I2C_INT_STATUS] & NO_ACK)
+		res = 1;
+
+	// Disable packet mode.
+	usleep(20);
+	base[I2C_CNFG] &= 0xFFFFF9FF;
+
+	// Disable interrupts.
+	base[I2C_INT_EN] = 0;
+
+	return res;
+}
+
+static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
+{
+	if (size > 32)
+		return 0;
+
+	int res = 0;
+
+	vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
+
+	// Enable interrupts.
+	base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
+		ARB_LOST | TX_FIFO_OVER | RX_FIFO_UNDER | RX_FIFO_DATA_REQ;
+	base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
+
+	// Set device address and recv mode.
+	base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
+
+	// Set recv mode.
+	base[I2C_CNFG] = DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_READ;
+
+	// Set and flush FIFO.
+	base[I2C_FIFO_CONTROL] = RX_FIFO_FLUSH | TX_FIFO_FLUSH;
+
+	// Load configuration.
+	_i2c_load_cfg_wait(base);
+
+	// Initiate transaction on packet mode.
+	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | PACKET_MODE_GO;
+
+	// Send reg request.
+	u32 hdr[3];
+	hdr[0] = I2C_PACKET_PROT_I2C;
+	hdr[1] = 1 - 1;
+	hdr[2] = I2C_HEADER_REP_START | (dev_addr << 1);
+
+	// Send header with reg request.
+	base[I2C_TX_FIFO] = hdr[0];
+	base[I2C_TX_FIFO] = hdr[1];
+	base[I2C_TX_FIFO] = hdr[2];
+	base[I2C_TX_FIFO] = reg;
+
+	u32 timeout = get_tmr_ms() + 400;
+	while (!(base[I2C_FIFO_STATUS] & TX_FIFO_EMPTY_CNT))
+		if (get_tmr_ms() > timeout)
+			break;
+
+	// Send read request.
+	hdr[1] = size - 1;
+	hdr[2] = I2C_HEADER_READ | (dev_addr << 1);
+
+	// Send header with read request.
+	base[I2C_TX_FIFO] = hdr[0];
+	base[I2C_TX_FIFO] = hdr[1];
+	base[I2C_TX_FIFO] = hdr[2];
+
+	timeout = get_tmr_ms() + 400;
+	while (size)
+	{
+		if (base[I2C_FIFO_STATUS] & RX_FIFO_FULL_CNT)
+		{
+			u32 rcv_size = MIN(size, 4);
+			u32 tmp = base[I2C_RX_FIFO];
+			memcpy(buf, &tmp, rcv_size);
+			buf += rcv_size;
+			size -= rcv_size;
+		}
+
+		if (get_tmr_ms() > timeout)
+		{
+			res = 1;
+			break;
+		}
+	}
+
+	if (base[I2C_STATUS] & I2C_STATUS_NOACK || base[I2C_INT_STATUS] & NO_ACK)
+		res = 1;
+
+	// Disable packet mode.
+	usleep(20);
+	base[I2C_CNFG] &= 0xFFFFF9FF;
+
+	// Disable interrupts.
+	base[I2C_INT_EN] = 0;
+
+	return res;
+}
+
+void i2c_init(u32 i2c_idx)
+{
+	vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
+
+	base[I2C_CLK_DIVISOR] = (5 << 16) | 1; // SF mode Div: 6, HS mode div: 2.
+	base[I2C_BUS_CLEAR_CONFIG] = (9 << 16) | BC_TERMINATE | BC_ENABLE;
+
+	// Load configuration.
+	_i2c_load_cfg_wait(base);
 
 	for (u32 i = 0; i < 10; i++)
 	{
 		usleep(20000);
-		if (base[INTERRUPT_STATUS_REGISTER] & 0x800)
+		if (base[I2C_INT_STATUS] & BUS_CLEAR_DONE)
 			break;
 	}
 
 	(vu32)base[I2C_BUS_CLEAR_STATUS];
-	base[INTERRUPT_STATUS_REGISTER] = base[INTERRUPT_STATUS_REGISTER];
+	base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
 }
 
-int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size)
+int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr)
+{
+	return _i2c_recv_single(i2c_idx, buf, size, dev_addr);
+}
+
+int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
+{
+	if (size > 32)
+		return 0;
+
+	return _i2c_send_pkt(i2c_idx, buf, size, dev_addr);
+}
+
+int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg)
+{
+	return _i2c_recv_pkt(i2c_idx, buf, size, dev_addr, reg);
+}
+
+int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size)
 {
 	u8 tmp[4];
 
 	if (size > 7)
 		return 0;
 
-	tmp[0] = y;
+	tmp[0] = reg;
 	memcpy(tmp + 1, buf, size);
 
-	return _i2c_send_pkt(idx, x, tmp, size + 1);
+	return _i2c_send_single(i2c_idx, dev_addr, tmp, size + 1);
 }
 
-int i2c_recv_buf(u8 *buf, u32 size, u32 idx, u32 x)
+int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg)
 {
-	return _i2c_recv_pkt(idx, buf, size, x);
+	int res = _i2c_send_single(i2c_idx, dev_addr, (u8 *)&reg, 1);
-}
-
-int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y)
-{
-	int res = _i2c_send_pkt(idx, x, (u8 *)&y, 1);
 	if (res)
-		res = _i2c_recv_pkt(idx, buf, size, x);
+		res = _i2c_recv_single(i2c_idx, buf, size, dev_addr);
 	return res;
 }
 
-int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b)
+int i2c_send_byte(u32 i2c_idx, u32 dev_addr, u32 reg, u8 val)
 {
-	return i2c_send_buf_small(idx, x, y, &b, 1);
+	return i2c_send_buf_small(i2c_idx, dev_addr, reg, &val, 1);
 }
 
-u8 i2c_recv_byte(u32 idx, u32 x, u32 y)
+u8 i2c_recv_byte(u32 i2c_idx, u32 dev_addr, u32 reg)
 {
 	u8 tmp = 0;
-	i2c_recv_buf_small(&tmp, 1, idx, x, y);
+	i2c_recv_buf_small(&tmp, 1, i2c_idx, dev_addr, reg);
 	return tmp;
 }
 

bdk/soc/i2c.h

@@ -27,22 +27,13 @@
 #define I2C_5 4
 #define I2C_6 5
 
-#define I2C_CNFG        0x00
+void i2c_init(u32 i2c_idx);
-#define I2C_CMD_ADDR0   0x01
+int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr);
-#define I2C_CMD_DATA1   0x03
+int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size);
-#define I2C_CMD_DATA2   0x04
+int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg);
-#define I2C_STATUS 0x07
+int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size);
-#define INTERRUPT_STATUS_REGISTER 0x1A
+int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg);
-#define I2C_CLK_DIVISOR_REGISTER 0x1B
+int i2c_send_byte(u32 i2c_idx, u32 dev_addr, u32 reg, u8 val);
-#define I2C_BUS_CLEAR_CONFIG 0x21
+u8  i2c_recv_byte(u32 i2c_idx, u32 dev_addr, u32 reg);
-#define I2C_BUS_CLEAR_STATUS 0x22
-#define I2C_CONFIG_LOAD 0x23
-
-void i2c_init(u32 idx);
-int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size);
-int i2c_recv_buf(u8 *buf, u32 size, u32 idx, u32 x);
-int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y);
-int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b);
-u8 i2c_recv_byte(u32 idx, u32 x, u32 y);
 
 #endif

bdk/soc/irq.c

@@ -47,10 +47,10 @@ static void _irq_enable_source(u32 irq)
 	u32 bit = irq % 32;
 
 	// Set as normal IRQ.
-	ICTLR(ctrl_idx, PRI_ICTLR_COP_IEP_CLASS) &= ~(1 << bit);
+	ICTLR(ctrl_idx, PRI_ICTLR_COP_IEP_CLASS) &= ~BIT(bit);
 
 	// Enable IRQ source.
-	ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_SET) = 1 << bit;
+	ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_SET) = BIT(bit);
 }
 
 static void _irq_disable_source(u32 irq)
@@ -59,7 +59,7 @@ static void _irq_disable_source(u32 irq)
 	u32 bit = irq % 32;
 
 	// Disable IRQ source.
-	ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = 1 << bit;
+	ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = BIT(bit);
 }
 
 static void _irq_disable_and_ack_all()
@@ -79,7 +79,7 @@ static void _irq_ack_source(u32 irq)
 	u32 bit = irq % 32;
 
 	// Force stop the interrupt as it's serviced here.
-	ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = 1 << bit;
+	ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = BIT(bit);
 }
 
 void irq_free(u32 irq)
@@ -133,6 +133,10 @@ static irq_status_t _irq_handle_source(u32 irq)
 		}
 	}
 
+	// Do not re-enable if not handled.
+	if (status == IRQ_NONE)
+		return status;
+
 	if (irqs[idx].flags & IRQ_FLAG_ONE_OFF)
 		irq_free(irq);
 	else
@@ -148,7 +152,9 @@ void irq_handler()
 
 	if (!irq_init_done)
 	{
+		_irq_disable_source(irq);
 		_irq_ack_source(irq);
+
 		return;
 	}
 
@@ -156,9 +162,10 @@ void irq_handler()
 
 	int err = _irq_handle_source(irq);
 
-	//TODO: disable if unhandhled.
 	if (err == IRQ_NONE)
-		gfx_printf("Unhandled IRQ: %d\n", irq);
+	{
+		DPRINTF("Unhandled IRQ got disabled: %d!\n", irq);
+	}
 }
 
 static void _irq_init()
@@ -170,6 +177,9 @@ static void _irq_init()
 
 void irq_end()
 {
+	if (!irq_init_done)
+		return;
+
 	_irq_free_all();
 	irq_disable_cpu_irq_exceptions();
 	irq_init_done = false;

bdk/soc/irq.h

@@ -209,8 +209,8 @@ typedef enum _irq_status_t
 typedef enum _irq_flags_t
 {
 	IRQ_FLAG_NONE        = 0,
-	IRQ_FLAG_ONE_OFF     = (1 << 0),
+	IRQ_FLAG_ONE_OFF     = BIT(0),
-	IRQ_FLAG_REPLACEABLE = (1 << 1)
+	IRQ_FLAG_REPLACEABLE = BIT(1)
 } irq_flags_t;
 
 void irq_end();

bdk/soc/kfuse.h

@@ -19,16 +19,16 @@
 
 #include <utils/types.h>
 
-#define KFUSE_STATE_SOFTRESET      (1 << 31)
-#define KFUSE_STATE_STOP           (1 << 25)
-#define KFUSE_STATE_RESTART        (1 << 24)
-#define KFUSE_STATE_CRCPASS        (1 << 17)
-#define KFUSE_STATE_DONE           (1 << 16)
-#define KFUSE_STATE_ERRBLOCK_MASK  0x3F00
-#define KFUSE_STATE_ERRBLOCK_SHIFT 8
 #define KFUSE_STATE_CURBLOCK_MASK  0x3F
+#define KFUSE_STATE_ERRBLOCK_SHIFT 8
+#define KFUSE_STATE_ERRBLOCK_MASK  0x3F00
+#define KFUSE_STATE_DONE           BIT(16)
+#define KFUSE_STATE_CRCPASS        BIT(17)
+#define KFUSE_STATE_RESTART        BIT(24)
+#define KFUSE_STATE_STOP           BIT(25)
+#define KFUSE_STATE_SOFTRESET      BIT(31)
 
-#define KFUSE_KEYADDR_AUTOINC (1<<16)
+#define KFUSE_KEYADDR_AUTOINC      BIT(16)
 
 #define KFUSE_STATE 0x80
 #define KFUSE_KEYADDR 0x88

bdk/soc/pinmux.h

@@ -71,6 +71,18 @@
 #define PINMUX_AUX_GPIO_PH6        0x250
 #define PINMUX_AUX_GPIO_PK3        0x260
 #define PINMUX_AUX_GPIO_PZ1        0x280
+/* Only in T210B01 */
+#define PINMUX_AUX_SDMMC2_DAT0     0x294
+#define PINMUX_AUX_SDMMC2_DAT1     0x298
+#define PINMUX_AUX_SDMMC2_DAT2     0x29C
+#define PINMUX_AUX_SDMMC2_DAT3     0x2A0
+#define PINMUX_AUX_SDMMC2_DAT4     0x2A4
+#define PINMUX_AUX_SDMMC2_DAT5     0x2A8
+#define PINMUX_AUX_SDMMC2_DAT6     0x2AC
+#define PINMUX_AUX_SDMMC2_DAT7     0x2B0
+#define PINMUX_AUX_SDMMC2_CLK      0x2B4
+#define PINMUX_AUX_SDMMC2_CMD      0x2BC
+
 /*! 0:UART-A, 1:UART-B, 3:UART-C, 3:UART-D */
 #define PINMUX_AUX_UARTX_TX(x)  (0xE4 + 0x10 * (x))
 #define PINMUX_AUX_UARTX_RX(x)  (0xE8 + 0x10 * (x))
@@ -87,17 +99,18 @@
 #define PINMUX_PULL_DOWN    (1 << 2)
 #define PINMUX_PULL_UP      (2 << 2)
 
-#define PINMUX_TRISTATE     (1 << 4)
+#define PINMUX_TRISTATE     BIT(4)
-#define PINMUX_PARKED       (1 << 5)
+#define PINMUX_PARKED       BIT(5)
-#define PINMUX_INPUT_ENABLE (1 << 6)
+#define PINMUX_INPUT_ENABLE BIT(6)
-#define PINMUX_LOCK         (1 << 7)
+#define PINMUX_LOCK         BIT(7)
-#define PINMUX_LPDR         (1 << 8)
+#define PINMUX_LPDR         BIT(8)
-#define PINMUX_HSM          (1 << 9)
+#define PINMUX_HSM          BIT(9)
 
-#define PINMUX_IO_HV        (1 << 10)
+#define PINMUX_IO_HV        BIT(10)
-#define PINMUX_OPEN_DRAIN   (1 << 11)
+#define PINMUX_OPEN_DRAIN   BIT(11)
-#define PINMUX_SCHMT        (1 << 12)
+#define PINMUX_SCHMT        BIT(12)
 
+#define PINMUX_DRIVE_MASK   (3 << 13)
 #define PINMUX_DRIVE_1X     (0 << 13)
 #define PINMUX_DRIVE_2X     (1 << 13)
 #define PINMUX_DRIVE_3X     (2 << 13)

bdk/soc/pmc.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/hw_init.h>
+#include <soc/pmc.h>
+#include <soc/t210.h>
+#include <utils/util.h>
+
+void pmc_scratch_lock(pmc_sec_lock_t lock_mask)
+{
+	// Lock Private key disable, Fuse write enable, MC carveout, Warmboot PA id and Warmboot address.
+	if (lock_mask & PMC_SEC_LOCK_MISC)
+	{
+		PMC(APBDEV_PMC_SEC_DISABLE)  |= 0x700FF0;   // RW lock: 0-3.
+		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0xFC000000; // RW lock: 21-23.
+		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0x3F0FFF00; // RW lock: 28-33, 36-38.
+		PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xC000000;  // RW lock: 85.
+		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF00FF00; // RW lock: 108-111, 116-119.
+
+		// SE2 context.
+		if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
+		{
+			PMC(APBDEV_PMC_SEC_DISABLE9) |= 0x3FF;      // RW lock: 120-124. (0xB38)
+			PMC(APBDEV_PMC_SEC_DISABLE10) = 0xFFFFFFFF; // RW lock: 135-150.
+		}
+ 	}
+
+	if (lock_mask & PMC_SEC_LOCK_LP0_PARAMS)
+	{
+		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x3FCFFFF;  // RW lock: 8-15, 17-20.
+		PMC(APBDEV_PMC_SEC_DISABLE4) |= 0x3F3FFFFF; // RW lock: 40-50, 52-54.
+		PMC(APBDEV_PMC_SEC_DISABLE5)  = 0xFFFFFFFF; // RW lock: 56-71.
+		PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xF3FFC00F; // RW lock: 72-73, 79-84, 86-87.
+		PMC(APBDEV_PMC_SEC_DISABLE7) |= 0x3FFFFF;   // RW lock: 88-98.
+		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF;       // RW lock: 104-107.
+	}
+
+	if (lock_mask & PMC_SEC_LOCK_RST_VECTOR)
+		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xF00000;   // RW lock: 34-35.
+
+	if (lock_mask & PMC_SEC_LOCK_CARVEOUTS)
+	{
+		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x30000;    // RW lock: 16.
+		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xC0000000; // RW lock: 39.
+		PMC(APBDEV_PMC_SEC_DISABLE4) |= 0xC0C00000; // RW lock: 51, 55.
+		PMC(APBDEV_PMC_SEC_DISABLE6) |= 0x3FF0;     // RW lock: 74-78.
+		PMC(APBDEV_PMC_SEC_DISABLE7) |= 0xFFC00000; // RW lock: 99-103.
+	}
+
+	if (lock_mask & PMC_SEC_LOCK_TZ_CMAC_W)
+		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0x550000;   // W lock: 112-115.
+
+	if (lock_mask & PMC_SEC_LOCK_TZ_CMAC_R)
+		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xAA0000;   // R lock: 112-115.
+
+	if (lock_mask & PMC_SEC_LOCK_TZ_KEK_W)
+		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0x55;       // W lock: 24-27.
+
+	if (lock_mask & PMC_SEC_LOCK_TZ_KEK_R)
+		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xAA;       // R lock: 24-27.
+
+	if (lock_mask & PMC_SEC_LOCK_SE_SRK)
+		PMC(APBDEV_PMC_SEC_DISABLE)  |= 0xFF000;    // RW lock: 4-7
+}
+
+int pmc_enable_partition(pmc_power_rail_t part, u32 enable)
+{
+	u32 part_mask = BIT(part);
+	u32 desired_state = enable << part;
+
+	// Check if the partition has the state we want.
+	if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
+		return 1;
+
+	u32 i = 5001;
+	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
+	{
+		usleep(1);
+		i--;
+		if (i < 1)
+			return 0;
+	}
+
+	// Toggle power gating.
+	PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | 0x100;
+
+	i = 5001;
+	while (i > 0)
+	{
+		if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
+			break;
+		usleep(1);
+		i--;
+	}
+
+	return 1;
+}

bdk/soc/pmc.h

@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 st4rk
+ * Copyright (c) 2018-2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,44 +19,61 @@
 #ifndef _PMC_H_
 #define _PMC_H_
 
+#include <utils/types.h>
+
 /*! PMC registers. */
 #define APBDEV_PMC_CNTRL 0x0
-#define  PMC_CNTRL_MAIN_RST (1 << 4)
+#define  PMC_CNTRL_MAIN_RST BIT(4)
 #define APBDEV_PMC_SEC_DISABLE 0x4
 #define APBDEV_PMC_PWRGATE_TOGGLE 0x30
 #define APBDEV_PMC_PWRGATE_STATUS 0x38
 #define APBDEV_PMC_NO_IOPOWER 0x44
-#define  PMC_NO_IOPOWER_GPIO_IO_EN   (1 << 21)
+#define  PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
-#define  PMC_NO_IOPOWER_AUDIO_HV     (1 << 18)
+#define  PMC_NO_IOPOWER_AUDIO_HV     BIT(18)
-#define  PMC_NO_IOPOWER_SDMMC1_IO_EN (1 << 12)
+#define  PMC_NO_IOPOWER_GPIO_IO_EN   BIT(21)
 #define APBDEV_PMC_SCRATCH0 0x50
-#define  PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
+#define  PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
-#define  PMC_SCRATCH0_MODE_FASTBOOT (1 << 30)
+#define  PMC_SCRATCH0_MODE_RCM      BIT(1)
-#define  PMC_SCRATCH0_MODE_PAYLOAD  (1 << 29)
+#define  PMC_SCRATCH0_MODE_PAYLOAD  BIT(29)
-#define  PMC_SCRATCH0_MODE_RCM      (1 << 1)
+#define  PMC_SCRATCH0_MODE_FASTBOOT BIT(30)
-#define  PMC_SCRATCH0_MODE_WARMBOOT (1 << 0)
+#define  PMC_SCRATCH0_MODE_RECOVERY BIT(31)
+#define  PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | PMC_SCRATCH0_MODE_FASTBOOT | PMC_SCRATCH0_MODE_PAYLOAD)
 #define APBDEV_PMC_SCRATCH1 0x54
 #define APBDEV_PMC_SCRATCH20 0xA0
+#define APBDEV_PMC_SECURE_SCRATCH4 0xC0
+#define APBDEV_PMC_SECURE_SCRATCH5 0xC4
 #define APBDEV_PMC_PWR_DET_VAL 0xE4
-#define  PMC_PWR_DET_GPIO_IO_EN   (1 << 21)
+#define  PMC_PWR_DET_SDMMC1_IO_EN BIT(12)
-#define  PMC_PWR_DET_AUDIO_HV     (1 << 18)
+#define  PMC_PWR_DET_AUDIO_HV     BIT(18)
-#define  PMC_PWR_DET_SDMMC1_IO_EN (1 << 12)
+#define  PMC_PWR_DET_GPIO_IO_EN   BIT(21)
 #define APBDEV_PMC_DDR_PWR 0xE8
 #define APBDEV_PMC_USB_AO 0xF0
 #define APBDEV_PMC_CRYPTO_OP 0xF4
 #define  PMC_CRYPTO_OP_SE_ENABLE  0
 #define  PMC_CRYPTO_OP_SE_DISABLE 1
 #define APBDEV_PMC_SCRATCH33 0x120
+#define APBDEV_PMC_SCRATCH37 0x130
+#define  PMC_SCRATCH37_KERNEL_PANIC_FLAG BIT(24)
 #define APBDEV_PMC_SCRATCH40 0x13C
 #define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
 #define  PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
 #define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
-#define  PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN (1 << 2)
+#define  PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2)
 #define APBDEV_PMC_RST_STATUS 0x1B4
+#define  PMC_RST_STATUS_MASK 0x7
+#define  PMC_RST_STATUS_POR 0
+#define  PMC_RST_STATUS_WATCHDOG 1
+#define  PMC_RST_STATUS_SENSOR 2
+#define  PMC_RST_STATUS_SW_MAIN 3
+#define  PMC_RST_STATUS_LP0 4
+#define  PMC_RST_STATUS_AOTAG 5
 #define APBDEV_PMC_IO_DPD_REQ 0x1B8
+#define  PMC_IO_DPD_REQ_DPD_OFF BIT(30)
 #define APBDEV_PMC_IO_DPD2_REQ 0x1C0
 #define APBDEV_PMC_VDDP_SEL 0x1CC
 #define APBDEV_PMC_DDR_CFG 0x1D0
+#define APBDEV_PMC_SECURE_SCRATCH6 0x224
+#define APBDEV_PMC_SECURE_SCRATCH7 0x228
 #define APBDEV_PMC_SCRATCH45 0x234
 #define APBDEV_PMC_SCRATCH46 0x238
 #define APBDEV_PMC_SCRATCH49 0x244
@@ -80,8 +98,63 @@
 #define APBDEV_PMC_SEC_DISABLE6 0x5B8
 #define APBDEV_PMC_SEC_DISABLE7 0x5BC
 #define APBDEV_PMC_SEC_DISABLE8 0x5C0
+#define APBDEV_PMC_SEC_DISABLE9 0x5C4
+#define APBDEV_PMC_SEC_DISABLE10 0x5C8
 #define APBDEV_PMC_SCRATCH188 0x810
 #define APBDEV_PMC_SCRATCH190 0x818
 #define APBDEV_PMC_SCRATCH200 0x840
+#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
+#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
+#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
+
+typedef enum _pmc_sec_lock_t
+{
+	PMC_SEC_LOCK_MISC       = BIT(0),
+	PMC_SEC_LOCK_LP0_PARAMS = BIT(1),
+	PMC_SEC_LOCK_RST_VECTOR = BIT(2),
+	PMC_SEC_LOCK_CARVEOUTS  = BIT(3),
+	PMC_SEC_LOCK_TZ_CMAC_W  = BIT(4),
+	PMC_SEC_LOCK_TZ_CMAC_R  = BIT(5),
+	PMC_SEC_LOCK_TZ_KEK_W   = BIT(6),
+	PMC_SEC_LOCK_TZ_KEK_R   = BIT(7),
+	PMC_SEC_LOCK_SE_SRK     = BIT(8),
+} pmc_sec_lock_t;
+
+typedef enum _pmc_power_rail_t
+{
+	POWER_RAIL_CRAIL = 0,
+	POWER_RAIL_3D0   = 1,
+	POWER_RAIL_VENC  = 2,
+	POWER_RAIL_PCIE  = 3,
+	POWER_RAIL_VDEC  = 4,
+	POWER_RAIL_L2C   = 5,
+	POWER_RAIL_MPE   = 6,
+	POWER_RAIL_HEG   = 7,
+	POWER_RAIL_SATA  = 8,
+	POWER_RAIL_CE1   = 9,
+	POWER_RAIL_CE2   = 10,
+	POWER_RAIL_CE3   = 11,
+	POWER_RAIL_CELP  = 12,
+	POWER_RAIL_3D1   = 13,
+	POWER_RAIL_CE0   = 14,
+	POWER_RAIL_C0NC  = 15,
+	POWER_RAIL_C1NC  = 16,
+	POWER_RAIL_SOR   = 17,
+	POWER_RAIL_DIS   = 18,
+	POWER_RAIL_DISB  = 19,
+	POWER_RAIL_XUSBA = 20,
+	POWER_RAIL_XUSBB = 21,
+	POWER_RAIL_XUSBC = 22,
+	POWER_RAIL_VIC   = 23,
+	POWER_RAIL_IRAM  = 24,
+	POWER_RAIL_NVDEC = 25,
+	POWER_RAIL_NVJPG = 26,
+	POWER_RAIL_AUD   = 27,
+	POWER_RAIL_DFD   = 28,
+	POWER_RAIL_VE2   = 29
+} pmc_power_rail_t;
+
+void pmc_scratch_lock(pmc_sec_lock_t lock_mask);
+int  pmc_enable_partition(pmc_power_rail_t part, u32 enable);
 
 #endif

bdk/soc/t210.h

@@ -61,6 +61,9 @@
 #define EMC_BASE 0x7001B000
 #define EMC0_BASE 0x7001E000
 #define EMC1_BASE 0x7001F000
+#define XUSB_HOST_BASE 0x70090000
+#define XUSB_PADCTL_BASE 0x7009F000
+#define XUSB_DEV_BASE 0x700D0000
 #define MIPI_CAL_BASE 0x700E3000
 #define CL_DVFS_BASE 0x70110000
 #define I2S_BASE 0x702D1000
@@ -79,7 +82,7 @@
 #define VIC(off) _REG(VIC_BASE, off)
 #define TSEC(off) _REG(TSEC_BASE, off)
 #define SOR1(off) _REG(SOR1_BASE, off)
-#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * cidx), off)
+#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * (cidx)), off)
 #define TMR(off) _REG(TMR_BASE, off)
 #define CLOCK(off) _REG(CLOCK_BASE, off)
 #define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
@@ -109,6 +112,12 @@
 #define EMC(off) _REG(EMC_BASE, off)
 #define EMC_CH0(off) _REG(EMC0_BASE, off)
 #define EMC_CH1(off) _REG(EMC1_BASE, off)
+#define XUSB_HOST(off) _REG(XUSB_HOST_BASE, off)
+#define XUSB_PADCTL(off) _REG(XUSB_PADCTL_BASE, off)
+#define XUSB_DEV(off) _REG(XUSB_DEV_BASE, off)
+#define XUSB_DEV_XHCI(off) _REG(XUSB_DEV_BASE, off)
+#define XUSB_DEV_PCI(off) _REG(XUSB_DEV_BASE + 0x8000, off)
+#define XUSB_DEV_DEV(off) _REG(XUSB_DEV_BASE + 0x9000, off)
 #define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
 #define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
 #define I2S(off) _REG(I2S_BASE, off)
@@ -149,14 +158,33 @@
 
 /*! AHB Gizmo registers. */
 #define AHB_ARBITRATION_PRIORITY_CTRL 0x8
-#define  ARBITRATION_PRIORITY_CTRL_ENB_FAST_REARBITRATE (1 << 6)
+#define  PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29)
+#define  PRIORITY_SELECT_USB BIT(6)   // USB-OTG.
+#define  PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC.
+#define  PRIORITY_SELECT_USB3 BIT(17) // XUSB.
 #define AHB_GIZMO_AHB_MEM 0x10
-#define  AHB_MEM_ENB_FAST_REARBITRATE (1 << 2)
+#define  AHB_MEM_ENB_FAST_REARBITRATE BIT(2)
+#define  AHB_MEM_DONT_SPLIT_AHB_WR    BIT(7)
+#define  AHB_MEM_IMMEDIATE            BIT(18)
+#define AHB_GIZMO_APB_DMA 0x14
 #define AHB_GIZMO_USB 0x20
-#define  AHB_GIZMO_USB_IMMEDIATE (1 << 18)
+#define AHB_GIZMO_SDMMC4 0x48
+#define AHB_GIZMO_USB2 0x7C
+#define AHB_GIZMO_USB3 0x80
+#define  AHB_GIZMO_IMMEDIATE BIT(18)
+#define AHB_ARBITRATION_XBAR_CTRL 0xE0
+#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4
+#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8
 #define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
-#define  MEM_PREFETCH_ENABLE (1 << 31)
+#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4
-#define  MEM_PREFETCH_AHB_MST_USB 6
+#define  MST_ID(x) (((x) & 0x1F) << 26)
+#define  MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5)
+#define  MEM_PREFETCH_USB_MST_ID MST_ID(6)   // USB-OTG.
+#define  MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC.
+#define  MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
+#define  MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
+#define  MEM_PREFETCH_ENABLE BIT(31)
+#define AHB_AHB_SPARE_REG 0x110
 
 /*! Misc registers. */
 #define APB_MISC_PP_STRAPPING_OPT_A 0x08
@@ -170,19 +198,16 @@
 #define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
 #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
 #define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
+#define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0
 #define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
 #define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
 
-/*! System registers. */
-#define AHB_ARBITRATION_XBAR_CTRL 0xE0
-#define AHB_AHB_SPARE_REG 0x110
-
 /*! Secure boot registers. */
 #define SB_CSR 0x0
-#define  SB_CSR_NS_RST_VEC_WR_DIS    (1 << 1)
+#define  SB_CSR_NS_RST_VEC_WR_DIS    BIT(1)
-#define  SB_CSR_PIROM_DISABLE        (1 << 4)
+#define  SB_CSR_PIROM_DISABLE        BIT(4)
 #define SB_AA64_RESET_LOW  0x30
-#define  SB_AA64_RST_AARCH64_MODE_EN (1 << 0)
+#define  SB_AA64_RST_AARCH64_MODE_EN BIT(0)
 #define SB_AA64_RESET_HIGH 0x34
 
 /*! SOR registers. */
@@ -217,20 +242,20 @@
 #define TIMERUS_USEC_CFG          (0x10 + 0x4)
 #define TIMER_TMR8_TMR_PTV        0x78
 #define TIMER_TMR9_TMR_PTV        0x80
-#define  TIMER_EN          (1 << 31)
+#define  TIMER_PER_EN      BIT(30)
-#define  TIMER_PER_EN      (1 << 30)
+#define  TIMER_EN          BIT(31)
 #define TIMER_TMR8_TMR_PCR        0x7C
 #define TIMER_TMR9_TMR_PCR        0x8C
-#define  TIMER_INTR_CLR    (1 << 30)
+#define  TIMER_INTR_CLR    BIT(30)
 
 #define TIMER_WDT4_CONFIG         (0x100 + 0x80)
-#define  TIMER_SRC(TMR) (TMR & 0xF)
+#define  TIMER_SRC(TMR) ((TMR) & 0xF)
-#define  TIMER_PER(PER) ((PER & 0xFF) << 4)
+#define  TIMER_PER(PER) (((PER) & 0xFF) << 4)
-#define  TIMER_SYSRESET_EN (1 << 14)
+#define  TIMER_SYSRESET_EN BIT(14)
-#define  TIMER_PMCRESET_EN (1 << 15)
+#define  TIMER_PMCRESET_EN BIT(15)
 #define TIMER_WDT4_COMMAND        (0x108 + 0x80)
-#define  TIMER_START_CNT   (1 << 0)
+#define  TIMER_START_CNT   BIT(0)
-#define  TIMER_CNT_DISABLE (1 << 1)
+#define  TIMER_CNT_DISABLE BIT(1)
 #define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
 #define  TIMER_MAGIC_PTRN 0xC45A
 
@@ -245,29 +270,28 @@
 #define I2S4_CTRL 0x3A0
 #define I2S5_CG   0x488
 #define I2S5_CTRL 0x4A0
-#define  I2S_CG_SLCG_ENABLE (1 << 0)
+#define  I2S_CG_SLCG_ENABLE BIT(0)
-#define  I2S_CTRL_MASTER_EN (1 << 10)
+#define  I2S_CTRL_MASTER_EN BIT(10)
 
 /*! PWM registers. */
 #define PWM_CONTROLLER_PWM_CSR_0 0x00
 #define PWM_CONTROLLER_PWM_CSR_1 0x10
-#define  PWM_CSR_EN (1 << 31)
+#define  PWM_CSR_EN BIT(31)
 
 /*! Special registers. */
 #define EMC_SCRATCH0 0x324
-#define  EMC_HEKA_UPD (1 << 30)
+#define  EMC_HEKA_UPD BIT(30)
-#define  EMC_SEPT_RUN (1 << 31)
 
 /*! Flow controller registers. */
 #define FLOW_CTLR_HALT_COP_EVENTS  0x4
-#define  HALT_COP_GIC_IRQ        (1 << 9)
+#define  HALT_COP_GIC_IRQ        BIT(9)
-#define  HALT_COP_LIC_IRQ        (1 << 11)
+#define  HALT_COP_LIC_IRQ        BIT(11)
-#define  HALT_COP_SEC            (1 << 23)
+#define  HALT_COP_SEC            BIT(23)
-#define  HALT_COP_MSEC           (1 << 24)
+#define  HALT_COP_MSEC           BIT(24)
-#define  HALT_COP_USEC           (1 << 25)
+#define  HALT_COP_USEC           BIT(25)
-#define  HALT_COP_JTAG           (1 << 28)
+#define  HALT_COP_JTAG           BIT(28)
-#define  HALT_COP_WAIT_EVENT     (1 << 30)
+#define  HALT_COP_WAIT_EVENT     BIT(30)
-#define  HALT_COP_STOP_UNTIL_IRQ (1 << 31)
+#define  HALT_COP_STOP_UNTIL_IRQ BIT(31)
 #define  HALT_COP_MAX_CNT        0xFF
 #define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
 #define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
@@ -280,9 +304,4 @@
 #define FLOW_CTLR_RAM_REPAIR 0x40
 #define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
 
-/*! USB controller registers. */
-#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
-#define  BAT_CHRG_CFG0_OP_SRC_EN    (1 << 3)
-#define  BAT_CHRG_CFG0_PWRDOWN_CHRG (1 << 0)
-
 #endif

bdk/soc/uart.c

@@ -122,7 +122,12 @@ u32 uart_get_IIR(u32 idx)
 {
 	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
 
-	return uart->UART_IIR_FCR;
+	u32 iir = uart->UART_IIR_FCR & UART_IIR_INT_MASK;
+
+	if (iir & UART_IIR_NO_INT)
+		return 0;
+	else
+		return ((iir >> 1) + 1); // Return encoded interrupt.
 }
 
 void uart_set_IIR(u32 idx)

bdk/soc/uart.h

@@ -54,6 +54,17 @@
 #define UART_IIR_FCR_RX_CLR 0x2
 #define UART_IIR_FCR_EN_FIFO 0x1
 
+#define UART_IIR_NO_INT BIT(0)
+#define UART_IIR_INT_MASK 0xF
+/* Custom returned interrupt results. Actual interrupts are -1 */
+#define UART_IIR_NOI   0 // No interrupt.
+#define UART_IIR_MSI   1 // Modem status interrupt.
+#define UART_IIR_THRI  2 // Transmitter holding register empty.
+#define UART_IIR_RDI   3 // Receiver data interrupt.
+#define UART_IIR_ERROR 4 // Overrun Error, Parity Error, Framing Error, Break.
+#define UART_IIR_REDI  5 // Receiver end of data interrupt.
+#define UART_IIR_RDTI  7 // Receiver data timeout interrupt.
+
 #define UART_MCR_RTS 0x2
 #define UART_MCR_DTR 0x1
 

bdk/storage/mmc.h

@@ -2,6 +2,7 @@
  * Header for MultiMediaCard (MMC)
  *
  * Copyright 2002 Hewlett-Packard Company
+ * Copyright 2018-2021 CTCaer
  *
  * Use consistent with the GNU GPL is permitted,
  * provided that this copyright notice is
@@ -21,8 +22,8 @@
  *          15 May 2002
  */
 
-#ifndef LINUX_MMC_MMC_H
+#ifndef MMC_H
-#define LINUX_MMC_MMC_H
+#define MMC_H
 
 /* Standard MMC commands (4.1)           type  argument     response */
 /* class 1 */
@@ -84,6 +85,11 @@
 #define MMC_APP_CMD              55   /* ac   [31:16] RCA        R1  */
 #define MMC_GEN_CMD              56   /* adtc [0] RD/WR          R1  */
 
+#define MMC_VENDOR_60_CMD        60   /* Vendor Defined              */
+#define MMC_VENDOR_61_CMD        61   /* Vendor Defined              */
+#define MMC_VENDOR_62_CMD        62   /* Vendor Defined              */
+#define MMC_VENDOR_63_CMD        63   /* Vendor Defined              */
+
 /* class 11 */
 #define MMC_QUE_TASK_PARAMS      44   /* ac   [20:16] task id    R1  */
 #define MMC_QUE_TASK_ADDR        45   /* ac   [31:0] data addr   R1  */
@@ -103,18 +109,18 @@
  */
 
 /*
-MMC status in R1, for native mode (SPI bits are different)
+ * MMC status in R1, for native mode (SPI bits are different)
-Type
+ * Type
-e : error bit
+ * e : error bit
-s : status bit
+ * s : status bit
-r : detected and set for the actual command response
+ * r : detected and set for the actual command response
-x : detected and set during command execution. the host must poll
+ * x : detected and set during command execution. the host must poll
-the card by sending status command in order to read these bits.
+ *     the card by sending status command in order to read these bits.
-Clear condition
+ * Clear condition
-a : according to the card state
+ * a : according to the card state
-b : always related to the previous command. Reception of
+ * b : always related to the previous command. Reception of a valid
-a valid command will clear it (with a delay of one command)
+ *     command will clear it (with a delay of one command)
-c : clear by read
+ * c : clear by read
 */
 
 #define R1_OUT_OF_RANGE		(1 << 31)	/* er, c */
@@ -136,13 +142,17 @@ c : clear by read
 #define R1_WP_ERASE_SKIP	(1 << 15)	/* sx, c */
 #define R1_CARD_ECC_DISABLED	(1 << 14)	/* sx, a */
 #define R1_ERASE_RESET		(1 << 13)	/* sr, c */
-#define R1_STATUS(x)            (x & 0xFFFFE000)
+#define R1_STATUS(x)            ((x) & 0xFFFFE000)
-#define R1_CURRENT_STATE(x)	((x & 0x00001E00) >> 9)	/* sx, b (4 bits) */
+#define R1_CURRENT_STATE(x)	(((x) & 0x00001E00) >> 9)	/* sx, b (4 bits) */
 #define R1_READY_FOR_DATA	(1 << 8)	/* sx, a */
 #define R1_SWITCH_ERROR		(1 << 7)	/* sx, c */
 #define R1_EXCEPTION_EVENT	(1 << 6)	/* sr, a */
 #define R1_APP_CMD		(1 << 5)	/* sr, c */
+#define R1_SKIP_STATE_CHECK	(1 << 4)	/* Custom state to skip expected state check */
+#define R1_AKE_SEQ_ERROR	(1 << 3)
 
+/* R1_CURRENT_STATE 12:9 */
+#define R1_STATE(x)     ((x) << 9)
 #define R1_STATE_IDLE	0
 #define R1_STATE_READY	1
 #define R1_STATE_IDENT	2
@@ -179,7 +189,10 @@ c : clear by read
 /*
  * OCR bits are mostly in host.h
  */
-#define MMC_CARD_BUSY	0x80000000	/* Card Power up status bit */
+#define MMC_CARD_VDD_18		(1 << 7)	/* Card VDD voltage 1.8 */
+#define MMC_CARD_VDD_27_34	(0x7F << 15)	/* Card VDD voltage 2.7 ~ 3.4 */
+#define MMC_CARD_CCS		(1 << 30)	/* Card Capacity status bit */
+#define MMC_CARD_BUSY		(1 << 31)	/* Card Power up status bit */
 
 /*
  * Card Command Classes (CCC)
@@ -241,6 +254,7 @@ c : clear by read
 #define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
 #define EXT_CSD_PARTITION_SETTING_COMPLETED 155	/* R/W */
 #define EXT_CSD_PARTITION_ATTRIBUTE	156	/* R/W */
+#define EXT_CSD_MAX_ENH_SIZE_MULT	157	/* RO, 3 bytes */
 #define EXT_CSD_PARTITION_SUPPORT	160	/* RO */
 #define EXT_CSD_HPI_MGMT		161	/* R/W */
 #define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
@@ -429,4 +443,9 @@ c : clear by read
 #define MMC_SECURE_ARGS			0x80000000
 #define MMC_TRIM_ARGS			0x00008001
 
-#endif /* LINUX_MMC_MMC_H */
+/*
+ * Vendor definitions and structs
+ */
+#define MMC_SANDISK_HEALTH_REPORT 0x96C9D71C
+
+#endif /* MMC_H */

bdk/storage/nx_sd.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2021 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -45,12 +45,15 @@ extern FATFS sd_fs;
 void sd_error_count_increment(u8 type);
 u16 *sd_get_error_count();
 bool sd_get_card_removed();
+bool sd_get_card_initialized();
+bool sd_get_card_mounted();
 u32  sd_get_mode();
 int  sd_init_retry(bool power_cycle);
 bool sd_initialize(bool power_cycle);
 bool sd_mount();
 void sd_unmount();
 void sd_end();
+bool sd_is_gpt();
 void *sd_file_read(const char *path, u32 *fsize);
 int  sd_save_to_file(void *buf, u32 size, const char *filename);