mirror of
https://github.com/Decscots/Lockpick_RCM.git
synced 2025-06-22 00:57:20 +02:00
Apply hekate 5.2.1 and gcc 10 changes, -fno-inline
This commit is contained in:
shchmue
parent
a5fe954ce7
commit
64d7e5cebd
64 changed files with 4676 additions and 3360 deletions
164
source/gfx/di.c
164
source/gfx/di.c
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 CTCaer
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* Copyright (c) 2018-2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -31,7 +31,11 @@
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#include "di.inl"
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static u32 _display_ver = 0;
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extern volatile nyx_storage_t *nyx_str;
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static u32 _display_id = 0;
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void display_end();
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static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
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{
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@ -41,8 +45,21 @@ static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
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usleep(5);
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}
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static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
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{
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DSI(_DSIREG(DSI_WR_DATA)) = (param << 8) | cmd;
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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if (wait)
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usleep(wait);
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}
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void display_init()
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{
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// Check if display is already initialized.
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if (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) & 0x18000000)
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display_end();
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// Power on.
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max77620_regulator_set_volt_and_flags(REGULATOR_LDO0, 1200000, MAX77620_POWER_MODE_NORMAL); // Configure to 1.2V.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL);
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@ -60,16 +77,16 @@ void display_init()
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000; // Set enable clock DSIA_LP.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz).
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// Disable deap power down.
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// Disable deep power down.
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PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
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PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
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// Config LCD and Backlight pins.
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PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN
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PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; // PULL_DOWN
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1
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PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN
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PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; // PULL_DOWN
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// Set Backlight +-5V pins mode and direction
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gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO);
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@ -87,14 +104,18 @@ void display_init()
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gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Enable Backlight EN.
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// Power up supply regulator for display interface.
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MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
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MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0;
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// Set DISP1 clock source and parrent clock.
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exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4);
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// Set DISP1 clock source and parent clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT.
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u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 96 MHz.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
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CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; // PLLD_SETUP.
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CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2D0AAA; // PLLD_ENABLE_CLK.
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// Setup display communication interfaces.
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94);
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exec_cfg((u32 *)DSI_BASE, _display_config_3, 61);
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94);
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exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config, 61);
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usleep(10000);
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// Enable Backlight Reset.
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@ -103,12 +124,10 @@ void display_init()
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// Setups DSI packet configuration and request display id.
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DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x337; // MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 3, 0);
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x406; // MIPI_DCS_GET_DISPLAY_ID
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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_display_dsi_send_cmd(MIPI_DSI_DCS_READ, MIPI_DCS_GET_DISPLAY_ID, 0);
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
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@ -116,37 +135,71 @@ void display_init()
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usleep(5000);
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_display_ver = DSI(_DSIREG(DSI_RD_DATA));
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if (_display_ver == 0x10)
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exec_cfg((u32 *)DSI_BASE, _display_config_4, 43);
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// MIPI_DCS_GET_DISPLAY_ID reply is a long read, size 3 u32.
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for (u32 i = 0; i < 3; i++)
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_display_id = DSI(_DSIREG(DSI_RD_DATA)); // Skip ack and msg type info and get the payload (display id).
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; // MIPI_DCS_EXIT_SLEEP_MODE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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// Save raw Display ID to Nyx storage.
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nyx_str->info.disp_id = _display_id;
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usleep(180000);
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// Decode Display ID.
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_display_id = ((_display_id >> 8) & 0xFF00) | (_display_id & 0xFF);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2905; // MIPI_DCS_SET_DISPLAY_ON
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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if ((_display_id & 0xFF) == PANEL_JDI_LPM062M)
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_display_id = PANEL_JDI_LPM062M;
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usleep(20000);
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// Initialize display panel.
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switch (_display_id)
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{
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case PANEL_JDI_LPM062M:
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exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43);
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
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break;
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case PANEL_INL_P062CCA_AZ1:
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case PANEL_AUO_A062TAN01:
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x439; // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
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DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9; // Enable extension cmd. (Pass: FF 83 94).
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(5000);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x739; // MIPI_DSI_DCS_LONG_WRITE: 7 bytes.
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if (_display_id == PANEL_INL_P062CCA_AZ1)
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DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
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else
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DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
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DSI(_DSIREG(DSI_WR_DATA)) = 0x143209; // (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32).
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(5000);
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break;
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case PANEL_INL_P062CCA_AZ2:
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case PANEL_AUO_A062TAN02:
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default: // Allow spare part displays to work.
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 120000);
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break;
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}
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000);
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// Configure PLLD for DISP1.
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exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3);
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plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 460.8 MHz.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
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CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;
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CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN.
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// Finalize DSI configuration.
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exec_cfg((u32 *)DSI_BASE, _display_config_5, 21);
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DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4;
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exec_cfg((u32 *)DSI_BASE, _display_config_7, 10);
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exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 21);
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DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; // PCD1 | div3.
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exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10);
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usleep(10000);
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// Calibrate display communication pads.
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6);
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exec_cfg((u32 *)DSI_BASE, _display_config_9, 4);
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16);
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 6);
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exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config, 4);
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 16);
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usleep(10000);
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// Enable video display controller.
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113);
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113);
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}
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void display_backlight_pwm_init()
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@ -197,25 +250,50 @@ void display_end()
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{
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display_backlight_brightness(0, 1000);
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
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DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet.
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// De-initialize video controller.
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17);
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exec_cfg((u32 *)DSI_BASE, _display_config_13, 16);
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17);
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exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16);
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usleep(10000);
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// De-initialize display panel.
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if (_display_ver == 0x10)
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exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
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switch (_display_id)
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{
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case PANEL_JDI_LPM062M:
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exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22);
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break;
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case PANEL_AUO_A062TAN01:
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exec_cfg((u32 *)DSI_BASE, _display_deinit_config_auo, 37);
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break;
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case PANEL_INL_P062CCA_AZ2:
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case PANEL_AUO_A062TAN02:
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DSI(_DSIREG(DSI_WR_DATA)) = 0x439; // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
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DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9; // Enable extension cmd. (Pass: FF 83 94).
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(5000);
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// Set Power.
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DSI(_DSIREG(DSI_WR_DATA)) = 0xB39; // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
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if (_display_id == PANEL_INL_P062CCA_AZ2)
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DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
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else
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DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
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// Set Power control. (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
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DSI(_DSIREG(DSI_WR_DATA)) = 0x71143209;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x114D31; // Set Power control. (Unknown).
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(5000);
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break;
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case PANEL_INL_P062CCA_AZ1:
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default:
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break;
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}
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; // MIPI_DCS_ENTER_SLEEP_MODE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(50000);
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_ENTER_SLEEP_MODE, 50000);
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// Disable display and backlight pins.
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gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
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