mirror of
https://github.com/Decscots/Lockpick_RCM.git
synced 2025-06-21 20:37:18 +02:00
Apply hekate 5.2.1 and gcc 10 changes, -fno-inline
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shchmue
parent
a5fe954ce7
commit
64d7e5cebd
64 changed files with 4676 additions and 3360 deletions
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@ -16,6 +16,8 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "mc.h"
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#include "emc.h"
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#include "sdram_param_t210.h"
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@ -29,7 +31,7 @@
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#include "../soc/t210.h"
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#include "../utils/util.h"
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#define CONFIG_SDRAM_COMPRESS_CFG
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#define CONFIG_SDRAM_KEEP_ALIVE
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#ifdef CONFIG_SDRAM_COMPRESS_CFG
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#include "../libs/compr/lz.h"
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@ -40,13 +42,57 @@
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static u32 _get_sdram_id()
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{
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u32 sdram_id = (fuse_read_odm(4) & 0x38) >> 3;
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return ((fuse_read_odm(4) & 0x38) >> 3);
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}
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// Check if id is proper.
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if (sdram_id > 7)
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sdram_id = 0;
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static bool _sdram_wait_emc_status(u32 reg_offset, u32 bit_mask, bool updated_state, s32 emc_channel)
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{
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bool err = true;
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return sdram_id;
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for (s32 i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++)
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{
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if (emc_channel)
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{
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if (emc_channel != 1)
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goto done;
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if (((EMC_CH1(reg_offset) & bit_mask) != 0) == updated_state)
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{
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err = false;
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break;
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}
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}
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else if (((EMC(reg_offset) & bit_mask) != 0) == updated_state)
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{
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err = false;
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break;
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}
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usleep(1);
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}
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done:
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return err;
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}
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static void _sdram_req_mrr_data(u32 data, bool dual_channel)
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{
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EMC(EMC_MRR) = data;
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_sdram_wait_emc_status(EMC_EMC_STATUS, EMC_STATUS_MRR_DIVLD, true, EMC_CHAN0);
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if (dual_channel)
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_sdram_wait_emc_status(EMC_EMC_STATUS, EMC_STATUS_MRR_DIVLD, true, EMC_CHAN1);
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}
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emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
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{
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emc_mr_data_t data;
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_sdram_req_mrr_data((1 << 31) | (mrx << 16), EMC_CHAN0);
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data.dev0_ch0 = EMC(EMC_MRR) & 0xFF;
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data.dev0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
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_sdram_req_mrr_data((1 << 30) | (mrx << 16), EMC_CHAN1);
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data.dev1_ch0 = EMC(EMC_MRR) & 0xFF;
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data.dev1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
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return data;
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}
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static void _sdram_config(const sdram_params_t *params)
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@ -73,10 +119,14 @@ static void _sdram_config(const sdram_params_t *params)
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CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control;
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CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0;
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// u32 tmp = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20);
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// CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp;
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// CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = tmp | 0x40000000;
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CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20);
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#ifdef CONFIG_SDRAM_KEEP_ALIVE
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CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) =
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(params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20) | PLLCX_BASE_ENABLE;
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#else
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u32 pllm_div = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20);
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CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = pllm_div;
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CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = pllm_div | PLLCX_BASE_ENABLE;
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#endif
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u32 wait_end = get_tmr_us() + 300;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000))
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@ -91,7 +141,7 @@ break_nosleep:
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if (params->emc_clock_source_dll)
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll;
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if (params->clear_clock2_mc1)
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000; // Clear Reset to MC1.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x2000001; // Enable EMC and MEM clocks.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x4000; // Enable EMC_DLL clock.
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@ -509,9 +559,9 @@ break_nosleep:
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// ZQ CAL setup (not actually issuing ZQ CAL now).
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if (params->emc_zcal_warm_cold_boot_enables & 1)
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{
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if (params->memory_type == 2)
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if (params->memory_type == MEMORY_TYPE_DDR3L)
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EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt << 3;
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if (params->memory_type == 3)
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if (params->memory_type == MEMORY_TYPE_LPDDR4)
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{
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EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
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EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd;
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@ -527,7 +577,7 @@ break_nosleep:
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// Set clock enable signal.
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u32 pin_gpio_cfg = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12);
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if (params->memory_type == 2 || params->memory_type == 3)
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if (params->memory_type == MEMORY_TYPE_DDR3L || params->memory_type == MEMORY_TYPE_LPDDR4)
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{
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EMC(EMC_PIN) = pin_gpio_cfg;
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(void)EMC(EMC_PIN);
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@ -536,9 +586,9 @@ break_nosleep:
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(void)EMC(EMC_PIN);
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}
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if (params->memory_type == 3)
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if (params->memory_type == MEMORY_TYPE_LPDDR4)
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usleep(params->emc_pin_extra_wait + 2000);
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else if (params->memory_type == 2)
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else if (params->memory_type == MEMORY_TYPE_DDR3L)
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usleep(params->emc_pin_extra_wait + 500);
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// Enable clock enable signal.
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@ -547,15 +597,15 @@ break_nosleep:
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usleep(params->emc_pin_program_wait);
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// Send NOP (trigger just needs to be non-zero).
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if (params->memory_type != 3)
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if (params->memory_type != MEMORY_TYPE_LPDDR4)
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EMC(EMC_NOP) = (params->emc_dev_select << 30) + 1;
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// On coldboot w/LPDDR2/3, wait 200 uSec after asserting CKE high.
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if (params->memory_type == 1)
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if (params->memory_type == MEMORY_TYPE_LPDDR2)
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usleep(params->emc_pin_extra_wait + 200);
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// Init zq calibration,
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if (params->memory_type == 3)
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if (params->memory_type == MEMORY_TYPE_LPDDR4)
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{
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// Patch 6 using BCT spare variables.
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if (params->emc_bct_spare10)
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@ -596,7 +646,7 @@ break_nosleep:
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PMC(APBDEV_PMC_DDR_CFG) = params->pmc_ddr_cfg;
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// Start periodic ZQ calibration (LPDDRx only).
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if (params->memory_type - 1 <= 2)
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if (params->memory_type && params->memory_type <= MEMORY_TYPE_LPDDR4)
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{
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EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval;
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EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
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@ -641,18 +691,47 @@ break_nosleep:
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MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access;
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MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl;
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//Disable write access to a bunch of EMC registers.
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// Disable write access to a bunch of EMC registers.
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MC(MC_EMEM_CFG_ACCESS_CTRL) = 1;
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}
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#ifndef CONFIG_SDRAM_COMPRESS_CFG
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static void _sdram_patch_model_params(u32 dramid, u32 *params)
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{
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for (u32 i = 0; i < sizeof(sdram_cfg_vendor_patches) / sizeof(sdram_vendor_patch_t); i++)
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if (sdram_cfg_vendor_patches[i].dramid & DRAM_ID(dramid))
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params[sdram_cfg_vendor_patches[i].addr] = sdram_cfg_vendor_patches[i].val;
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}
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#endif
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sdram_params_t *sdram_get_params()
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{
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// Check if id is proper.
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u32 dramid = _get_sdram_id();
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if (dramid > 6)
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dramid = 0;
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#ifdef CONFIG_SDRAM_COMPRESS_CFG
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u8 *buf = (u8 *)SDRAM_PARAMS_ADDR;
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LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz));
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return (sdram_params_t *)&buf[sizeof(sdram_params_t) * _get_sdram_id()];
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return (sdram_params_t *)&buf[sizeof(sdram_params_t) * dramid];
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#else
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return _dram_cfgs[_get_sdram_id()];
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sdram_params_t *buf = (sdram_params_t *)SDRAM_PARAMS_ADDR;
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memcpy(buf, &_dram_cfg_0_samsung_4gb, sizeof(sdram_params_t));
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switch (dramid)
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{
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case DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH:
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case DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT:
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break;
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case DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN:
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case DRAM_4GB_COPPER_UNK_3:
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case DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH:
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case DRAM_4GB_COPPER_UNK_5:
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case DRAM_4GB_COPPER_UNK_6:
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_sdram_patch_model_params(dramid, (u32 *)buf);
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break;
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}
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return buf;
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#endif
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}
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