mirror of
https://github.com/Decscots/Lockpick_RCM.git
synced 2025-06-21 20:37:18 +02:00
Apply hekate 5.2.1 and gcc 10 changes, -fno-inline
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shchmue
parent
a5fe954ce7
commit
64d7e5cebd
64 changed files with 4676 additions and 3360 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -19,6 +20,17 @@
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#include "../utils/util.h"
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#include "../storage/sdmmc.h"
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/*
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* CLOCK Peripherals:
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* L 0 - 31
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* H 32 - 63
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* U 64 - 95
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* V 96 - 127
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* W 128 - 159
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* X 160 - 191
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* Y 192 - 223
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*/
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/* clock_t: reset, enable, source, index, clk_src, clk_div */
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static const clock_t _clock_uart[] = {
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@ -29,7 +41,7 @@ static const clock_t _clock_uart[] = {
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/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 }
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};
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//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0 FM_DIV: 26.
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//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26.
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static const clock_t _clock_i2c[] = {
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/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
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/* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz
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@ -77,6 +89,10 @@ static clock_t _clock_pwm = {
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CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Fref: 6.2MHz.
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};
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static clock_t _clock_sdmmc_legacy_tm = {
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CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66
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};
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void clock_enable(const clock_t *clk)
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{
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// Put clock into reset.
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@ -112,6 +128,29 @@ void clock_enable_uart(u32 idx)
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clock_enable(&_clock_uart[idx]);
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}
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void clock_disable_uart(u32 idx)
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{
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clock_disable(&_clock_uart[idx]);
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}
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#define UART_SRC_CLK_DIV_EN (1 << 24)
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int clock_uart_use_src_div(u32 idx, u32 baud)
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{
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u32 clk_src_div = CLOCK(_clock_uart[idx].source) & 0xE0000000;
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if (baud == 1000000)
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CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | 49;
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else
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{
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CLOCK(_clock_uart[idx].source) = clk_src_div | 2;
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return 1;
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}
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return 0;
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}
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void clock_enable_i2c(u32 idx)
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{
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clock_enable(&_clock_i2c[idx]);
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@ -228,6 +267,51 @@ void clock_disable_pwm()
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clock_disable(&_clock_pwm);
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}
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void clock_enable_pllc(u32 divn)
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{
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u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
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// Check if already enabled and configured.
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if ((CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_ENABLE) && (pll_divn_curr == divn))
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return;
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// Take PLLC out of reset and set basic misc parameters.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
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((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
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usleep(10);
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// Set PLLC dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) = (divn << 10) | 4; // DIVM: 4, DIVP: 1.
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// Enable PLLC and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_ENABLE;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_LOCK))
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;
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// Disable PLLC_OUT1, enable reset and set div to 1.5.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
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// Enable PLLC_OUT1 and bring it out of reset.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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msleep(1); // Wait a bit for PLL to stabilize.
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}
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void clock_disable_pllc()
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{
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// Disable PLLC and PLLC_OUT1.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
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usleep(10);
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}
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC4_RST (1 << 15)
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@ -366,56 +450,78 @@ static void _clock_sdmmc_clear_enable(u32 id)
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}
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}
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static u32 _clock_sdmmc_table[8] = { 0 };
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static void _clock_sdmmc_config_legacy_tm()
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{
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clock_t *clk = &_clock_sdmmc_legacy_tm;
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if (!(CLOCK(clk->enable) & (1 << clk->index)))
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clock_enable(clk);
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}
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#define PLLP_OUT0 0x0
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static int _clock_sdmmc_config_clock_host(u32 *pout, u32 id, u32 val)
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typedef struct _clock_sdmmc_t
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{
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u32 clock;
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u32 real_clock;
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} clock_sdmmc_t;
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static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 };
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#define SDMMC_CLOCK_SRC_PLLP_OUT0 0x0
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#define SDMMC_CLOCK_SRC_PLLC4_OUT2 0x3
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#define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1
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static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
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{
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u32 divisor = 0;
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u32 source = PLLP_OUT0;
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u32 source = SDMMC_CLOCK_SRC_PLLP_OUT0;
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if (id > SDMMC_4)
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return 0;
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// Get IO clock divisor.
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switch (val)
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{
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case 25000:
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*pout = 24728;
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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break;
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case 26000:
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*pout = 25500;
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*pclock = 25500;
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divisor = 30; // 16 div.
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break;
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case 40800:
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*pout = 40800;
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*pclock = 40800;
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divisor = 18; // 10 div.
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break;
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case 50000:
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*pout = 48000;
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*pclock = 48000;
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divisor = 15; // 8.5 div.
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break;
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case 52000:
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*pout = 51000;
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*pclock = 51000;
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divisor = 14; // 8 div.
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break;
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case 100000:
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*pout = 90667;
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*pclock = 90667;
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divisor = 7; // 4.5 div.
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break;
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case 200000:
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*pout = 163200;
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case 164000:
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*pclock = 163200;
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divisor = 3; // 2.5 div.
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break;
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case 208000:
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*pout = 204000;
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case 200000:
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*pclock = 204000;
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divisor = 2; // 2 div.
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break;
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default:
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*pout = 24728;
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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}
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_clock_sdmmc_table[2 * id] = val;
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_clock_sdmmc_table[2 * id + 1] = *pout;
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_clock_sdmmc_table[id].clock = val;
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_clock_sdmmc_table[id].real_clock = *pclock;
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// Set SDMMC legacy timeout clock.
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_clock_sdmmc_config_legacy_tm();
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// Set SDMMC clock.
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switch (id)
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@ -437,70 +543,75 @@ static int _clock_sdmmc_config_clock_host(u32 *pout, u32 id, u32 val)
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return 1;
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}
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
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void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val)
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{
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if (_clock_sdmmc_table[2 * id] == val)
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if (_clock_sdmmc_table[id].clock == val)
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{
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*pout = _clock_sdmmc_table[2 * id + 1];
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*pclock = _clock_sdmmc_table[id].real_clock;
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}
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else
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{
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int is_enabled = _clock_sdmmc_is_enabled(id);
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if (is_enabled)
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_config_clock_host(pout, id, val);
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_clock_sdmmc_config_clock_host(pclock, id, val);
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if (is_enabled)
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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}
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}
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type)
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void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
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{
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// Get Card clock divisor.
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switch (type)
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{
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case 0:
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*pout = 26000;
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case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz.
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*pclock = 26000;
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*pdivisor = 66;
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break;
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case 1:
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*pout = 26000;
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case SDHCI_TIMING_MMC_LS26:
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*pclock = 26000;
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*pdivisor = 1;
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break;
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case 2:
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*pout = 52000;
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case SDHCI_TIMING_MMC_HS52:
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*pclock = 52000;
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*pdivisor = 1;
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break;
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case 3:
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case 4:
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case 11:
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*pout = 200000;
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case SDHCI_TIMING_MMC_HS200:
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case SDHCI_TIMING_MMC_HS400:
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case SDHCI_TIMING_UHS_SDR104:
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*pclock = 200000;
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*pdivisor = 1;
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break;
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case 5:
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*pout = 25000;
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case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz.
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*pclock = 25000;
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*pdivisor = 64;
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break;
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case 6:
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case 8:
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*pout = 25000;
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case SDHCI_TIMING_SD_DS12:
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case SDHCI_TIMING_UHS_SDR12:
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*pclock = 25000;
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*pdivisor = 1;
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break;
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case 7:
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*pout = 50000;
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case SDHCI_TIMING_SD_HS25:
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case SDHCI_TIMING_UHS_SDR25:
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*pclock = 50000;
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*pdivisor = 1;
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break;
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case 10:
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*pout = 100000;
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case SDHCI_TIMING_UHS_SDR50:
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*pclock = 100000;
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*pdivisor = 1;
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break;
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case 13:
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*pout = 40800;
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case SDHCI_TIMING_UHS_SDR82:
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*pclock = 164000;
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*pdivisor = 1;
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break;
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case 14:
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*pout = 200000;
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case SDHCI_TIMING_UHS_DDR50:
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*pclock = 40800;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_DDR52: // Actual IO Freq: 49.92 MHz.
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*pclock = 200000;
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*pdivisor = 2;
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break;
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}
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@ -513,15 +624,15 @@ int clock_sdmmc_is_not_reset_and_enabled(u32 id)
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void clock_sdmmc_enable(u32 id, u32 val)
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{
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u32 div = 0;
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u32 clock = 0;
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if (_clock_sdmmc_is_enabled(id))
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_set_reset(id);
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_clock_sdmmc_config_clock_host(&div, id, val);
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_clock_sdmmc_config_clock_host(&clock, id, val);
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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usleep((100000 + div - 1) / div);
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usleep((100000 + clock - 1) / clock);
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_clock_sdmmc_clear_reset(id);
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_clock_sdmmc_is_reset(id);
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}
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