mirror of
https://github.com/Decscots/Lockpick_RCM.git
synced 2025-06-21 20:37:18 +02:00
Add BPMP overclock, add hekate fixes, fix sprintf
This commit is contained in:
shchmue
parent
34890f0025
commit
82bea6be8f
39 changed files with 1130 additions and 544 deletions
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@ -18,6 +18,7 @@
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#include <string.h>
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#include "hw_init.h"
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#include "bpmp.h"
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#include "clock.h"
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#include "fuse.h"
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#include "gpio.h"
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@ -38,22 +39,36 @@
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extern sdmmc_t sd_sdmmc;
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extern boot_cfg_t b_cfg;
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/*
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* CLK_OSC - 38.4 MHz crystal.
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* CLK_M - 19.2 MHz (osc/2).
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* CLK_S - 32.768 KHz (from PMIC).
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* SCLK - 204MHz init (-> 408MHz -> OC).
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* HCLK - 204MHz init (-> 408MHz -> OC).
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* PCLK - 68MHz init (-> 136MHz -> OC/4).
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*/
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void _config_oscillators()
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{
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4;
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000;
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TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m.
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CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071;
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE;
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | 0x400000;
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PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | 0x1000;
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PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | 0x2000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10;
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CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF;
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency.
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TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m.
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CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER;
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PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN;
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PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | (4 << 23); // LP0 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL_RANGE.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable.
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PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz)
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444;
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CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz).
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CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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void _config_gpios()
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@ -61,11 +76,22 @@ void _config_gpios()
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PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
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PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
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// Set Joy-Con IsAttached direction.
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PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE;
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PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE;
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// Set pin mode for Joy-Con IsAttached and UARTB/C TX pins.
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B
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gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
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#endif
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C
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gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
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#endif
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// Set Joy-Con IsAttached mode.
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gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
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gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
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// Enable input logic for Joy-Con IsAttached and UARTB/C TX pins.
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gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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@ -80,27 +106,36 @@ void _config_gpios()
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gpio_config(GPIO_PORT_X, GPIO_PIN_7, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_X, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_X, GPIO_PIN_7, GPIO_OUTPUT_DISABLE);
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// Configure HOME as inputs.
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// PINMUX_AUX(PINMUX_AUX_BUTTON_HOME) = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE;
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// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
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}
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void _config_pmc_scratch()
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{
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PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF;
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE;
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PMC(APBDEV_PMC_SECURE_SCRATCH21) |= 0x10;
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PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
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PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
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}
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void _mbist_workaround()
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{
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
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// Set mux output to SOR1 clock switch.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF;
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000u;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
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// Enabled PLLD and set csi to PLLD for test pattern generation.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000;
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// Clear per-clock resets.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40; // Clear reset APE.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000; // Clear reset VIC.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X.
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usleep(2);
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// I2S channels to master and disable SLCG.
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I2S(I2S1_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S1_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S2_CTRL) |= I2S_CTRL_MASTER_EN;
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@ -111,30 +146,39 @@ void _mbist_workaround()
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I2S(I2S4_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE;
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DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4;
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DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; // DSC_SLCG_OVERRIDE.
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VIC(0x8C) = 0xFFFFFFFF;
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = 0x80400808;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300;
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// Set per-clock reset.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40; // Set reset APE.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1x.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000; // Set reset VIC.
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// Enable specific clocks and disable all others.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0; // Enable clock PMC, FUSE.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130; // Enable clock RTC, TMR, GPIO, BPMP_CACHE.
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//CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80400130; // Keep USB data ON.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200; // Enable clock CSITE, IRAMA, IRAMB, IRAMC, IRAMD, BPMP_CACHE_RAM.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = 0x80400808; // Enable clock MSELECT, APB2APE, SPDIF_DOUBLER, SE.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC; // Enable clock PCIERX0, PCIERX1, PCIERX2, PCIERX3, PCIERX4, PCIERX5, ENTROPY, MC1.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780; // Enable clock MC_CAPA, MC_CAPB, MC_CPU, MC_BBC, DBGAPB, HPLL_ADSP, PLLG_REF.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300; // Enable clock MC_CDPA, MC_CCPA.
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// Disable clock gate overrides.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE) = 0;
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000;
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// Set child clock sources.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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}
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void _config_se_brom()
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@ -170,13 +214,59 @@ void _config_se_brom()
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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}
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void _config_regulators()
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{
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
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(1 << 6) | (1 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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max77620_regulator_config_fps(REGULATOR_LDO4);
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max77620_regulator_config_fps(REGULATOR_LDO8);
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max77620_regulator_config_fps(REGULATOR_SD0);
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max77620_regulator_config_fps(REGULATOR_SD1);
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max77620_regulator_config_fps(REGULATOR_SD3);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
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(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
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// Set vdd_core voltage to 1.125V
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max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
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// Fix CPU/GPU after a Linux warmboot.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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// Disable low battery shutdown monitor.
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max77620_low_battery_monitor_config();
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}
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void config_hw()
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{
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// Bootrom stuff we skipped by going through rcm.
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_config_se_brom();
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//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
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SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F;
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PMC(APBDEV_PMC_SCRATCH49) = ((PMC(APBDEV_PMC_SCRATCH49) >> 1) << 1) & 0xFFFFFFFD;
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SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN.
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PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC;
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_mbist_workaround();
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clock_enable_se();
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@ -197,49 +287,29 @@ void config_hw()
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clock_enable_i2c(I2C_1);
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clock_enable_i2c(I2C_5);
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clock_enable_unk2();
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clock_enable_tzram();
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i2c_init(I2C_1);
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i2c_init(I2C_5);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
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(1 << 6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
|
||||
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
|
||||
(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1,
|
||||
(7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2,
|
||||
(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
|
||||
max77620_regulator_config_fps(REGULATOR_LDO4);
|
||||
max77620_regulator_config_fps(REGULATOR_LDO8);
|
||||
max77620_regulator_config_fps(REGULATOR_SD0);
|
||||
max77620_regulator_config_fps(REGULATOR_SD1);
|
||||
max77620_regulator_config_fps(REGULATOR_SD3);
|
||||
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
|
||||
(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
|
||||
|
||||
max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
|
||||
|
||||
// Fix GPU after warmboot for Linux.
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
|
||||
|
||||
// Disable low battery shutdown monitor.
|
||||
max77620_low_battery_monitor_config();
|
||||
_config_regulators();
|
||||
|
||||
_config_pmc_scratch(); // Missing from 4.x+
|
||||
|
||||
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333;
|
||||
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz).
|
||||
|
||||
sdram_init();
|
||||
|
||||
bpmp_mmu_enable();
|
||||
mc_enable_ahb_redirect();
|
||||
}
|
||||
|
||||
void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
|
||||
{
|
||||
// Flush and disable MMU.
|
||||
bpmp_mmu_disable();
|
||||
bpmp_clk_rate_set(BPMP_CLK_NORMAL);
|
||||
|
||||
// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
|
||||
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
|
||||
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue