mirror of
https://github.com/Decscots/Lockpick_RCM.git
synced 2025-06-21 22:37:19 +02:00
Add BPMP overclock, add hekate fixes, fix sprintf
This commit is contained in:
shchmue
parent
34890f0025
commit
82bea6be8f
39 changed files with 1130 additions and 544 deletions
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@ -21,6 +21,7 @@
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#include "sdmmc.h"
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#include "../gfx/gfx.h"
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#include "../power/max7762x.h"
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#include "../soc/bpmp.h"
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#include "../soc/clock.h"
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#include "../soc/gpio.h"
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#include "../soc/pinmux.h"
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@ -31,8 +32,6 @@
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//#define DPRINTF(...) gfx_printf(__VA_ARGS__)
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#define DPRINTF(...)
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extern boot_cfg_t b_cfg;
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/*! SCMMC controller base addresses. */
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static const u32 _sdmmc_bases[4] = {
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0x700B0000,
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@ -123,6 +122,7 @@ static int _sdmmc_config_ven_ceata_clk(sdmmc_t *sdmmc, u32 id)
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{
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if (!sdmmc->venclkctl_set)
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return 0;
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tap_val = sdmmc->venclkctl_tap;
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}
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else
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@ -201,7 +201,7 @@ out:;
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int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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{
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//Disable the SD clock if it was enabled, and reenable it later.
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// Disable the SD clock if it was enabled, and reenable it later.
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bool should_enable_sd_clock = false;
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if (sdmmc->regs->clkcon & TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE)
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{
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@ -217,7 +217,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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case 1:
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case 5:
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case 6:
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sdmmc->regs->hostctl &= 0xFB; //Should this be 0xFFFB (~4) ?
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sdmmc->regs->hostctl &= 0xFB; // Should this be 0xFFFB (~4) ?
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sdmmc->regs->hostctl2 &= SDHCI_CTRL_VDD_330;
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break;
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case 2:
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@ -233,7 +233,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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case 4:
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//Non standard
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// Non standard.
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | HS400_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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@ -242,7 +242,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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case 10:
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//T210 Errata for SDR50, the host must be set to SDR104.
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// T210 Errata for SDR50, the host must be set to SDR104.
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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@ -264,7 +264,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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divisor = div >> 8;
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sdmmc->regs->clkcon = (sdmmc->regs->clkcon & 0x3F) | (div << 8) | (divisor << 6);
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//Enable the SD clock again.
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// Enable the SD clock again.
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if (should_enable_sd_clock)
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sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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@ -398,7 +398,7 @@ static int _sdmmc_wait_prnsts_type0(sdmmc_t *sdmmc, u32 wait_dat)
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr_ms() + 2000;
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while(sdmmc->regs->prnsts & 1) //CMD inhibit.
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while(sdmmc->regs->prnsts & 1) // CMD inhibit.
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if (get_tmr_ms() > timeout)
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{
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_sdmmc_reset(sdmmc);
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@ -408,7 +408,7 @@ static int _sdmmc_wait_prnsts_type0(sdmmc_t *sdmmc, u32 wait_dat)
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if (wait_dat)
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{
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timeout = get_tmr_ms() + 2000;
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while (sdmmc->regs->prnsts & 2) //DAT inhibit.
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while (sdmmc->regs->prnsts & 2) // DAT inhibit.
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if (get_tmr_ms() > timeout)
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{
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_sdmmc_reset(sdmmc);
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@ -424,7 +424,7 @@ static int _sdmmc_wait_prnsts_type1(sdmmc_t *sdmmc)
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr_ms() + 2000;
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while (!(sdmmc->regs->prnsts & 0x100000)) //DAT0 line level.
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while (!(sdmmc->regs->prnsts & 0x100000)) // DAT0 line level.
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if (get_tmr_ms() > timeout)
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{
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_sdmmc_reset(sdmmc);
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@ -511,13 +511,17 @@ static int _sdmmc_config_tuning_once(sdmmc_t *sdmmc, u32 cmd)
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return 0;
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_sdmmc_setup_read_small_block(sdmmc);
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sdmmc->regs->norintstsen |= TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY;
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sdmmc->regs->norintsts = sdmmc->regs->norintsts;
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sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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_sdmmc_parse_cmd_48(sdmmc, cmd);
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_sdmmc_get_clkcon(sdmmc);
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usleep(1);
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_sdmmc_reset(sdmmc);
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sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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_sdmmc_get_clkcon(sdmmc);
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@ -533,10 +537,13 @@ static int _sdmmc_config_tuning_once(sdmmc_t *sdmmc, u32 cmd)
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return 1;
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}
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}
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_sdmmc_reset(sdmmc);
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sdmmc->regs->norintstsen &= 0xFFDF;
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_sdmmc_get_clkcon(sdmmc);
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usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor);
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return 0;
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}
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@ -563,8 +570,8 @@ int sdmmc_config_tuning(sdmmc_t *sdmmc, u32 type, u32 cmd)
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return 0;
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}
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sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag;
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sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | 0x40;
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sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag; // Tries.
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sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | 0x40; // Multiplier.
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sdmmc->regs->ventunctl0 |= 0x20000;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_EXEC_TUNING;
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@ -577,6 +584,7 @@ int sdmmc_config_tuning(sdmmc_t *sdmmc, u32 type, u32 cmd)
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if (sdmmc->regs->hostctl2 & SDHCI_CTRL_TUNED_CLK)
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return 1;
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return 0;
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}
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@ -666,7 +674,7 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power)
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{
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if (get_tmr_ms() > timeout)
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{
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//In case autocalibration fails, we load suggested standard values.
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// In case autocalibration fails, we load suggested standard values.
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_sdmmc_pad_config_fallback(sdmmc, power);
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sdmmc->regs->autocalcfg &= 0xDFFFFFFF;
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break;
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@ -703,7 +711,7 @@ static int _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
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if (pout)
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*pout = norintsts;
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//Check for error interrupt.
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// Check for error interrupt.
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if (norintsts & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT)
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{
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sdmmc->regs->errintsts = errintsts;
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@ -746,11 +754,14 @@ static int _sdmmc_stop_transmission_inner(sdmmc_t *sdmmc, u32 *rsp)
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return 0;
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_sdmmc_enable_interrupts(sdmmc);
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cmd.cmd = MMC_STOP_TRANSMISSION;
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cmd.arg = 0;
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cmd.rsp_type = SDMMC_RSP_TYPE_1;
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cmd.check_busy = 1;
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_sdmmc_parse_cmdbuf(sdmmc, &cmd, false);
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int res = _sdmmc_wait_request(sdmmc);
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_sdmmc_mask_interrupts(sdmmc);
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@ -758,6 +769,7 @@ static int _sdmmc_stop_transmission_inner(sdmmc_t *sdmmc, u32 *rsp)
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return 0;
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_sdmmc_cache_rsp(sdmmc, rsp, 4, SDMMC_RSP_TYPE_1);
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return _sdmmc_wait_prnsts_type1(sdmmc);
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}
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@ -777,6 +789,7 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp)
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int res = _sdmmc_stop_transmission_inner(sdmmc, rsp);
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usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
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if (should_disable_sd_clock)
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sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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@ -793,7 +806,7 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
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blkcnt = 0xFFFF;
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u32 admaaddr = (u32)req->buf;
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//Check alignment.
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// Check alignment.
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if (admaaddr << 29)
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return 0;
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@ -817,7 +830,7 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
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trnmode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
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if (req->is_auto_cmd12)
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trnmode = (trnmode & 0xFFF3) | TEGRA_MMC_TRNMOD_AUTO_CMD12;
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY);
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sdmmc->regs->trnmod = trnmode;
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return 1;
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@ -836,15 +849,18 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc)
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while (1)
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{
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u16 intr = 0;
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res = _sdmmc_check_mask_interrupt(sdmmc, &intr,
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res = _sdmmc_check_mask_interrupt(sdmmc, &intr,
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TEGRA_MMC_NORINTSTS_XFER_COMPLETE | TEGRA_MMC_NORINTSTS_DMA_INTERRUPT);
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if (res < 0)
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break;
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if (intr & TEGRA_MMC_NORINTSTS_XFER_COMPLETE)
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return 1; //Transfer complete.
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{
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY);
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return 1; // Transfer complete.
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}
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if (intr & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT)
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{
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//Update DMA.
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// Update DMA.
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sdmmc->regs->admaaddr = sdmmc->dma_addr_next;
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sdmmc->regs->admaaddr_hi = 0;
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sdmmc->dma_addr_next += 0x80000;
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@ -906,6 +922,7 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
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{
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if (blkcnt_out)
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*blkcnt_out = blkcnt;
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if (req->is_auto_cmd12)
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sdmmc->rsp3 = sdmmc->regs->rspreg3;
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}
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@ -919,12 +936,14 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
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static int _sdmmc_config_sdmmc1()
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{
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//Configure SD card detect.
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// Configure SD card detect.
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PINMUX_AUX(PINMUX_AUX_GPIO_PZ1) = PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | 1; //GPIO control, pull up.
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APB_MISC(APB_MISC_GP_VGPIO_GPIO_MUX_SEL) = 0;
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gpio_config(GPIO_PORT_Z, GPIO_PIN_1, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_Z, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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usleep(100);
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// Check if SD card is inserted.
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if(!!gpio_read(GPIO_PORT_Z, GPIO_PIN_1))
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return 0;
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@ -937,8 +956,8 @@ static int _sdmmc_config_sdmmc1()
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* APB_MISC_GP_SDMMCx_CLK_LPBK_CONTROL = SDMMCx_CLK_PAD_E_LPBK for CLK
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*/
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//Configure SDMMC1 pinmux.
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APB_MISC(APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL) = 1;
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// Configure SDMMC1 pinmux.
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APB_MISC(APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL) = 1; // Enable deep loopback for SDMMC1 CLK pad.
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PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PARKED;
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PINMUX_AUX(PINMUX_AUX_SDMMC1_CMD) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_PULL_UP;
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PINMUX_AUX(PINMUX_AUX_SDMMC1_DAT3) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_PULL_UP;
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@ -946,12 +965,12 @@ static int _sdmmc_config_sdmmc1()
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PINMUX_AUX(PINMUX_AUX_SDMMC1_DAT1) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_PULL_UP;
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PINMUX_AUX(PINMUX_AUX_SDMMC1_DAT0) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_PULL_UP;
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//Make sure the SDMMC1 controller is powered.
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// Make sure the SDMMC1 controller is powered.
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PMC(APBDEV_PMC_NO_IOPOWER) &= ~(1 << 12);
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//Assume 3.3V SD card voltage.
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// Assume 3.3V SD card voltage.
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PMC(APBDEV_PMC_PWR_DET_VAL) |= (1 << 12);
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//Set enable SD card power.
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// Set enable SD card power.
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PINMUX_AUX(PINMUX_AUX_DMIC3_CLK) = PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN | 1; //GPIO control, pull down.
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gpio_config(GPIO_PORT_E, GPIO_PIN_4, GPIO_MODE_GPIO);
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gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH);
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@ -959,13 +978,13 @@ static int _sdmmc_config_sdmmc1()
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usleep(1000);
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//Enable SD card power.
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// Enable SD card power.
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max77620_regulator_set_voltage(REGULATOR_LDO2, 3300000);
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max77620_regulator_enable(REGULATOR_LDO2, 1);
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usleep(1000);
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//For good measure.
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// For good measure.
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APB_MISC(APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL) = 0x10000000;
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usleep(1000);
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@ -1009,18 +1028,23 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int n
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sdmmc->regs->sdmemcmppadctl = (sdmmc->regs->sdmemcmppadctl & 0xF) | 7;
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if (!_sdmmc_autocal_config_offset(sdmmc, power))
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return 0;
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_sdmmc_autocal_execute(sdmmc, power);
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if (_sdmmc_enable_internal_clock(sdmmc))
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{
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sdmmc_set_bus_width(sdmmc, bus_width);
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_sdmmc_set_voltage(sdmmc, power);
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if (sdmmc_setup_clock(sdmmc, type))
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{
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sdmmc_sd_clock_ctrl(sdmmc, no_sd);
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_sdmmc_sd_clock_enable(sdmmc);
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_sdmmc_get_clkcon(sdmmc);
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return 1;
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}
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return 0;
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}
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return 0;
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@ -1039,8 +1063,8 @@ void sdmmc_end(sdmmc_t *sdmmc)
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{
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gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
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max77620_regulator_enable(REGULATOR_LDO2, 0);
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b_cfg.sd_timeoff = get_tmr_ms(); // Some sandisc U1 cards need 100ms for a power cycle.
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msleep(1); // To power cycle, min 1ms without power is needed.
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sd_power_cycle_time_start = get_tmr_ms(); // Some sandisc U1 cards need 100ms for a power cycle.
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usleep(1000); // To power cycle, min 1ms without power is needed.
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}
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_sdmmc_get_clkcon(sdmmc);
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@ -1062,7 +1086,7 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b
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if (!sdmmc->sd_clock_enabled)
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return 0;
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//Recalibrate periodically for SDMMC1.
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// Recalibrate periodically for SDMMC1.
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if (sdmmc->id == SDMMC_1 && sdmmc->no_sd)
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_sdmmc_autocal_execute(sdmmc, sdmmc_get_voltage(sdmmc));
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@ -1077,6 +1101,7 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b
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int res = _sdmmc_execute_cmd_inner(sdmmc, cmd, req, blkcnt_out);
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usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
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if (should_disable_sd_clock)
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sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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@ -1093,6 +1118,14 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
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_sdmmc_get_clkcon(sdmmc);
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// Enable schmitt trigger for better duty cycle and low jitter clock.
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PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) |= PINMUX_SCHMT;
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PINMUX_AUX(PINMUX_AUX_SDMMC1_CMD) |= PINMUX_SCHMT;
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PINMUX_AUX(PINMUX_AUX_SDMMC1_DAT3) |= PINMUX_SCHMT;
|
||||
PINMUX_AUX(PINMUX_AUX_SDMMC1_DAT2) |= PINMUX_SCHMT;
|
||||
PINMUX_AUX(PINMUX_AUX_SDMMC1_DAT1) |= PINMUX_SCHMT;
|
||||
PINMUX_AUX(PINMUX_AUX_SDMMC1_DAT0) |= PINMUX_SCHMT;
|
||||
|
||||
max77620_regulator_set_voltage(REGULATOR_LDO2, 1800000);
|
||||
PMC(APBDEV_PMC_PWR_DET_VAL) &= ~(1 << 12);
|
||||
|
||||
|
|
@ -1106,7 +1139,7 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
|
|||
{
|
||||
sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
|
||||
_sdmmc_get_clkcon(sdmmc);
|
||||
msleep(1);
|
||||
usleep(1000);
|
||||
if ((sdmmc->regs->prnsts & 0xF00000) == 0xF00000)
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue