mirror of
https://github.com/Decscots/Lockpick_RCM.git
synced 2025-06-22 01:17:18 +02:00
Update to hekate bdk 5.5.6
This commit is contained in:
shchmue
parent
93909f149e
commit
a7712b173c
95 changed files with 2720 additions and 1684 deletions
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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* Copyright (c) 2018-2021 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -18,7 +18,7 @@
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#include <string.h>
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#include <soc/hw_init.h>
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#include <gfx/di.h>
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#include <display/di.h>
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#include <input/joycon.h>
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#include <input/touch.h>
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#include <sec/se.h>
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@ -42,6 +42,7 @@
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#include <storage/nx_sd.h>
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#include <storage/sdmmc.h>
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#include <thermal/fan.h>
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#include <thermal/tmp451.h>
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#include <utils/util.h>
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extern boot_cfg_t b_cfg;
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@ -87,6 +88,7 @@ static void _config_oscillators()
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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// The uart is skipped for Copper, Hoag and Calcio. Used in Icosa, Iowa and Aula.
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static void _config_gpios(bool nx_hoag)
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{
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// Clamp inputs when tristated.
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@ -263,7 +265,7 @@ static void _config_se_brom()
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FUSE(FUSE_PRIVATE_KEY3)
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};
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// Set SBK to slot 14.
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se_aes_key_set(14, sbk, 0x10);
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se_aes_key_set(14, sbk, SE_KEY_128_SIZE);
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// Lock SBK from being read.
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se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
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@ -275,7 +277,7 @@ static void _config_se_brom()
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// This memset needs to happen here, else TZRAM will behave weirdly later on.
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memset((void *)TZRAM_BASE, 0, 0x10000);
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PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
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SE(SE_INT_STATUS_REG_OFFSET) = 0x1F;
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SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts.
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// Clear the boot reason to avoid problems later
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PMC(APBDEV_PMC_SCRATCH200) = 0x0;
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@ -285,17 +287,21 @@ static void _config_se_brom()
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static void _config_regulators(bool tegra_t210)
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{
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// Set RTC/AO domain to POR voltage.
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if (tegra_t210)
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max7762x_regulator_set_voltage(REGULATOR_LDO4, 1000000);
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// Disable low battery shutdown monitor.
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max77620_low_battery_monitor_config(false);
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// Disable SDMMC1 IO power.
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gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW);
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max77620_regulator_enable(REGULATOR_LDO2, 0);
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max7762x_regulator_enable(REGULATOR_LDO2, false);
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sd_power_cycle_time_start = get_tmr_ms();
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
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BIT(6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
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MAX77620_ONOFFCNFG1_RSVD | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
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if (tegra_t210)
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{
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@ -313,28 +319,18 @@ static void _config_regulators(bool tegra_t210)
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(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
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// Set vdd_core voltage to 1.125V.
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max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
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max7762x_regulator_set_voltage(REGULATOR_SD0, 1125000);
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// Fix CPU/GPU after a L4T warmboot.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
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// Fix CPU/GPU after L4T warmboot.
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max77620_config_gpio(5, MAX77620_GPIO_OUTPUT_DISABLE);
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max77620_config_gpio(6, MAX77620_GPIO_OUTPUT_DISABLE);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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// Set POR configuration.
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max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_POR_CFG);
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max77621_config_default(REGULATOR_GPU0, MAX77621_CTRL_POR_CFG);
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}
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else // Tegra X1+ set vdd_core voltage to 1.05V.
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max77620_regulator_set_voltage(REGULATOR_SD0, 1050000);
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max7762x_regulator_set_voltage(REGULATOR_SD0, 1050000);
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}
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void hw_init()
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@ -373,7 +369,8 @@ void hw_init()
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#ifdef DEBUG_UART_PORT
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clock_enable_uart(DEBUG_UART_PORT);
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uart_init(DEBUG_UART_PORT, 115200);
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uart_init(DEBUG_UART_PORT, DEBUG_UART_BAUDRATE);
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uart_invert(DEBUG_UART_PORT, DEBUG_UART_INVERT, UART_INVERT_TXD);
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#endif
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// Enable Dynamic Voltage and Frequency Scaling device clock.
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@ -391,17 +388,20 @@ void hw_init()
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//! TODO: Why? Device is NFC MCU on Lite.
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if (nx_hoag)
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max77620_regulator_set_volt_and_flags(REGULATOR_LDO8, 2800000, MAX77620_POWER_MODE_NORMAL);
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{
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max7762x_regulator_set_voltage(REGULATOR_LDO8, 2800000);
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max7762x_regulator_enable(REGULATOR_LDO8, true);
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}
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// Initialize I2C1 for various power related devices.
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i2c_init(I2C_1);
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// Enable charger in case it's disabled.
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bq24193_enable_charger();
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// Initialize various regulators based on Erista/Mariko platform.
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_config_regulators(tegra_t210);
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// Enable charger in case it's disabled.
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bq24193_enable_charger();
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_config_pmc_scratch(); // Missing from 4.x+
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// Set BPMP/SCLK to PLLP_OUT (408MHz).
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@ -421,19 +421,18 @@ void hw_init()
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bpmp_mmu_enable();
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}
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void hw_reinit_workaround(bool extra_reconfig, u32 magic)
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void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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{
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// Disable BPMP max clock.
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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#ifdef NYX
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// Deinit touchscreen, 5V regulators and Joy-Con.
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touch_power_off();
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// Disable temperature sensor, touchscreen, 5V regulators and Joy-Con.
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tmp451_end();
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set_fan_duty(0);
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touch_power_off();
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jc_deinit();
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regulator_disable_5v(REGULATOR_5V_ALL);
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clock_disable_uart(UART_B);
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clock_disable_uart(UART_C);
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regulator_5v_disable(REGULATOR_5V_ALL);
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#endif
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// Flush/disable MMU cache and set DRAM clock to 204MHz.
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@ -445,10 +444,10 @@ void hw_reinit_workaround(bool extra_reconfig, u32 magic)
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE);
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if (extra_reconfig)
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// Do coreboot mitigations.
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if (coreboot)
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{
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msleep(10);
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PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN;
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clock_disable_cl_dvfs();
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@ -457,13 +456,27 @@ void hw_reinit_workaround(bool extra_reconfig, u32 magic)
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gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
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gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO);
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gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO);
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// Reinstate SD controller power.
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PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN);
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}
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// Power off display.
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display_end();
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// Seamless display or display power off.
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switch (bl_magic)
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{
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case BL_MAGIC_CRBOOT_SLD:;
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// Set pwm to 0%, switch to gpio mode and restore pwm duty.
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u32 brightness = display_get_backlight_brightness();
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display_backlight_brightness(0, 1000);
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_GPIO);
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display_backlight_brightness(brightness, 0);
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break;
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default:
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display_end();
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}
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// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
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if (magic == 0xBAADF00D)
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if (bl_magic == BL_MAGIC_BROKEN_HWI)
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{
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD);
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sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0);
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